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| latticeecp2/m family handbook hb1003 version 04.7, june 2010
june 2010 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 1 section i. latticeecp2/m family data sheet introduction features ....................................................................................................................... ...................................... 1-1 introduction ................................................................................................................... ..................................... 1-2 architecture architecture overview .......................................................................................................... .............................. 2-1 pfu blocks ..................................................................................................................... ................................... 2-3 slice .......................................................................................................................... ................................ 2-3 modes of operation............................................................................................................. ...................... 2-5 routing........................................................................................................................ ....................................... 2-6 sysclock phase locked loops (gpll/spll) ........................................................................................ ........ 2-6 general purpose pll (gpll) ..................................................................................................... .............. 2-6 standard pll (spll) ............................................................................................................ .................... 2-7 delay locked loops (dll)....................................................................................................... .......................... 2-8 dlldela delay block ............................................................................................................ .................. 2-9 pll/dll cascading .............................................................................................................. .................... 2-9 gpll/spll/gdll pio input pin connections (latticeecp2m family only) .................................................. 2-10 clock dividers ................................................................................................................. ................................. 2-10 clock distribution network ..................................................................................................... .......................... 2-11 primary clock sources.......................................................................................................... .................. 2-11 secondary clock/control sources ................................................................................................ .......... 2-13 edge clock sources............................................................................................................. ................... 2-14 primary clock routing .......................................................................................................... .................. 2-15 dynamic clock select (dcs) ..................................................................................................... ............. 2-15 secondary clock/control routing ................................................................................................ ........... 2-15 slice clock selection.......................................................................................................... ..................... 2-17 edge clock routing ............................................................................................................. ................... 2-18 sysmem memory .................................................................................................................. ........................... 2-19 sysmem memory block............................................................................................................ ............... 2-19 bus size matching .............................................................................................................. .................... 2-19 ram initialization and rom operation ........................................................................................... ........ 2-19 memory cascading ............................................................................................................... .................. 2-19 single, dual and pseudo-dual port modes........................................................................................ ..... 2-19 memory core reset .............................................................................................................. .................. 2-20 ebr asynchronous reset......................................................................................................... .............. 2-20 sysdsp? block .................................................................................................................. ............................. 2-21 sysdsp block approach compared to general dsp ............................................................................. 2-21 sysdsp block capabilities ...................................................................................................... ................ 2-21 mult sysdsp element ............................................................................................................ .............. 2-23 mac sysdsp element ............................................................................................................. ............... 2-24 multaddsub sysdsp element ...................................................................................................... ..... 2-25 multaddsubsum sysdsp element ................................................................................................... 2-26 clock, clock enable and reset resources ........................................................................................ .... 2-26 signed and unsigned with different widths...................................................................................... ...... 2-27 overflow flag from mac ......................................................................................................... ......... 2-27 ipexpress?..................................................................................................................... ........................ 2-28 optimized dsp functions ........................................................................................................ ........................ 2-28 resources available in the latticeecp2/m family ................................................................................ .2-28 latticeecp2/m family handbook table of contents table of contents lattice semiconductor latti ceecp2/m family handbook 2 latticeecp2/m dsp performance .................................................................................................. ........ 2-29 programmable i/o cells (pic) ................................................................................................... ...................... 2-29 pio ............................................................................................................................ ....................................... 2-31 input register block ........................................................................................................... ..................... 2-31 output register block .......................................................................................................... ................... 2-33 tristate register block ........................................................................................................ .................... 2-35 control logic block ............................................................................................................ ..................... 2-35 ddr memory support............................................................................................................. ......................... 2-35 left and right edges........................................................................................................... .................... 2-35 bottom edge .................................................................................................................... ....................... 2-35 top edge....................................................................................................................... .......................... 2-36 dll calibrated dqs delay block ................................................................................................. .......... 2-37 polarity control logic ......................................................................................................... ..................... 2-39 dqsxfer........................................................................................................................ ....................... 2-40 sysi/o buffer .................................................................................................................. .................................. 2-40 sysi/o buffer banks ............................................................................................................ .................... 2-40 typical sysi/o i/o behavior during power-up.................................................................................... ..... 2-43 supported sysi/o standards ..................................................................................................... .............. 2-43 hot socketing.................................................................................................................. ........................ 2-45 serdes and pcs (physical coding sublayer)...................................................................................... ......... 2-46 serdes block................................................................................................................... ..................... 2-46 pcs............................................................................................................................ ............................. 2-47 sci (serdes client interface) bus.............................................................................................. .......... 2-47 ieee 1149.1-comp liant boundary scan te stability............ ................ ............. ............. ............. ............. ......... 2-48 device configuration........................................................................................................... ............................. 2-48 soft error detect (sed) support ................................................................................................ ............. 2-48 external resistor.............................................................................................................. ....................... 2-49 on-chip oscillator............................................................................................................. ...................... 2-49 density shifting ............................................................................................................... ................................. 2-49 dc and switching characteristics absolute maximum ratings ....................................................................................................... ........................ 3-1 recommended operating conditions ............................................................................................... ................. 3-1 hot socketing specifications .............................................................................................................................. 3-2 dc electrical characteristics.................................................................................................. ............................ 3-3 latticeecp2 supply current (standby) .............................................................................................................. 3-4 latticeecp2m supply current (standby) ........................................................................................................... 3-5 latticeecp2 initializat ion supply current .......................................................................................................... 3-6 latticeecp2m initializ ation supply current ....................................................................................................... 3-7 serdes power supply requirements (latticeecp2m family only) ............................................................... 3-8 serdes power (latticeecp2m family only)........................................................................................ ........... 3-8 sysi/o recommended operating conditions........................................................................................ ............. 3-9 sysi/o single-ended dc electrical characteristics.............................................................................. ............ 3-10 sysi/o differential electrical characteristics ................................................................................. ................... 3-11 lvds........................................................................................................................... ............................ 3-11 differential hstl and sstl..................................................................................................... ............... 3-11 lvds25e ........................................................................................................................ ........................ 3-12 lvcmos33d ...................................................................................................................... .................... 3-12 blvds .......................................................................................................................... .......................... 3-13 lvpecl ......................................................................................................................... ......................... 3-14 rsds ........................................................................................................................... ........................... 3-15 mlvds.......................................................................................................................... .......................... 3-16 typical building block function performance .................................................................................................. 3-17 pin-to-pin performance (lvcmos25 12ma drive) ................................................................................ 3-1 7 register-to-register performance ............................................................................................... ........... 3-17 table of contents lattice semiconductor latti ceecp2/m family handbook 3 derating timing tables ......................................................................................................... ........................... 3-18 latticeecp2/m external switching characteristics .......................................................................................... 3-19 latticeecp2/m internal switching characteristics ........................................................................................... 3-28 timing diagrams ................................................................................................................ .............................. 3-30 latticeecp2/m family timing adders ............................................................................................................. 3-32 sysclock gpll timing ........................................................................................................... ...................... 3-35 sysclock spll timing........................................................................................................... ....................... 3-36 dll timing..................................................................................................................... .................................. 3-37 serdes high-speed data transmitter (latticeecp2m family only) ............................................................ 3-38 serdes high speed data receiver (latticeecp2m family only) ................................................................ 3-41 input data jitter tolerance.................................................................................................... .................. 3-41 serdes external reference clock (latticeecp2m family only) ......................................................... 3-43 serdes power-down/power-up specification ....................................................................................... ....... 3-43 pci express electrical and timing characteristics .............................................................................. ............ 3-44 ac and dc characteristics ...................................................................................................... ............... 3-44 latticeecp2/m sysconfig port timing specifications ............................................................................. ..... 3-46 jtag port timing specifications ................................................................................................ ..................... 3-51 switching test conditions...................................................................................................... .......................... 3-52 pinout information signal descriptions ............................................................................................................ ................................ 4-1 pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin .................................................... 4-4 latticeecp2 pin information summary, lfe2-6 and lfe2-12 ........................................................................ .. 4-5 latticeecp2 pin information summary, lfe2-20 and lfe2-35 ....................................................................... .4-7 latticeecp2 pin information summary, lfe2-50 and lfe2-70 ....................................................................... .4-9 latticeecp2m pin information summary, lfe2m20 and lfe2m35 ............................................................... 4-11 latticeecp2m pin information summary, lfe2m50, lfe2m70 and lfe2m100............................................ 4-13 available device resources by package, latticeecp2............................................................................. ...... 4-15 available device resources by package, latticeecp2m............................................................................ .... 4-15 latticeecp2 power supply and nc................................................................................................ ................. 4-16 latticeecp2 power supply and nc (cont.)........................................................................................ ............. 4-17 latticeecp2m power supply and nc............................................................................................... ............... 4-18 latticeecp2m power supply and nc (cont.)....................................................................................... ........... 4-19 latticeecp2m power supply and nc (cont.)....................................................................................... ........... 4-21 lfe2-6e/se and lfe2-12e/se logic signal connections: 144 tqfp ........................................................... 4-22 lfe2-12e/se and lfe2-20e/se logic signal connections: 208 pqfp......................................................... 4-26 lfe2-6e/se and lfe2-12e/se logic signal connections: 256 fpbga .......................................................... 4-31 lfe2-20e/se logic signal connections: 256 fpbga ................................................................................ ...... 4-39 lfe2-12e/se and lfe2-20e/se logic signal connections: 484 fpbga ........................................................ 4-47 lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga ........................................................ 4-60 lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga ........................................................ 4-73 lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga ........................................................ 4-91 lfe2-70e/se logic signal connections: 900 fpbga ................................................................................ .... 4-109 lfe2m-20e/se and lfe2m-35e/se logic signal connections: 256 fpbga ................................................ 4-134 lfe2m20e/se and lfe2m35e/se logic signal connections: 484 fpbga .................................................. 4-141 lfe2m50e/se logic signal connections: 484 fpbga ................................................................................ .. 4-153 lfe2m35e/se and lfe2m50e/se logic signal connections: 672 fpbga .................................................. 4-167 lfe2m50e/se and lfe2m70e/se logic signal connections: 900 fpbga .................................................. 4-184 lfe2m100e/se logic signal connections: 900 fpbga ............................................................................... . 4-206 lfe2m70e/se and lfe2m100e/se logic signal connections: 1152 fpbga .............................................. 4-231 ordering information latticeecp2 part number description............................................................................................ ................... 5-1 ordering information ........................................................................................................... ............................... 5-1 latticeecp2 standard series devices, conventional packaging............................................................. 5-2 latticeecp2 standard series devices, lead-free packaging ....................................................................... ... 5-5 table of contents lattice semiconductor latti ceecp2/m family handbook 4 latticeecp2 s-series devices, conventional packaging......................................................................... 5- 8 latticeecp2 s-series devices, lead-free packaging ........................................................................... 5-1 1 latticeecp2m part number description........................................................................................... ............... 5-14 ordering information ........................................................................................................... ............................. 5-14 latticeecp2m standard series devices, conventional packaging........................................................ 5-15 latticeecp2m standard series devices, lead-free packaging ............................................................ 5-18 latticeecp2m s-series devices, lead-free packaging ........................................................................ 5-23 supplemental information for further information ........................................................................................................ .............................. 6-1 latticeecp2/m family data sheet revision history revision history ............................................................................................................... .................................. 7-1 section ii. latticeecp2/ m family technical notes latticeecp2m serdes/pcs usage guide introduction to pcs ............................................................................................................ ................................ 8-1 features ....................................................................................................................... ...................................... 8-1 supported standards ............................................................................................................ ............................. 8-2 architecture overview .......................................................................................................... .............................. 8-2 pcs quad ....................................................................................................................... .......................... 8-2 pcs quad and channels.......................................................................................................... ................ 8-3 per channel pcs/fpga interface ports........................................................................................... ........ 8-4 locating a pcs quad ............................................................................................................ ................... 8-4 detailed channel block diagram ................................................................................................. ............. 8-4 sci (serdes client interface) bus.............................................................................................. ............ 8-7 using this technical note ...................................................................................................... .................. 8-7 serdes/pcs ..................................................................................................................... ............................... 8-7 i/o definitions................................................................................................................ ............................ 8-9 serdes/pcs functional description .............................................................................................. ............... 8-12 serdes ......................................................................................................................... ........................ 8-12 reference clock usage .......................................................................................................... ................ 8-13 transmit data.................................................................................................................. ........................ 8-16 receive data................................................................................................................... ........................ 8-16 configuration guis............................................................................................................. .............................. 8-27 configuration file description ................................................................................................. ................ 8-38 latticeecp2m pcs in gigabit ethernet mode ...................................................................................... ........... 8-39 gigabit ethernet (100 0base-x) idle insert......... ................. ................ ................ ................ ............ ....... 8-39 gigabit ethernet idle insert and ff_correct_disp_ch[3:0] signal usage................................................... 8-39 latticeecp2m pcs in pci express mode ........................................................................................... ............ 8-39 pcs loopback modes ............................................................................................................. ........................ 8-41 serial loopback mode ........................................................................................................... ................. 8-41 serdes parallel loopback mode.................................................................................................. ........ 8-41 pcs parallel loopback mode ..................................................................................................... ............ 8-41 fpga interface clocks usage .................................................................................................... ..................... 8-42 2-to-1 gearing ................................................................................................................. ........................ 8-44 serdes/pcs block latency....................................................................................................... .................... 8-49 serdes client interface (sci).................................................................................................. ...................... 8-50 interrupts and status.......................................................................................................... ..................... 8-52 serdes client interface application example.................................................................................... ... 8-53 dynamic configuration of serdes/pcs quad...................................................................................... 8 -54 serdes debug capabilities ...................................................................................................... ............ 8-54 control boxes and buttons, status boxes and the text window ........................................................... 8-56 other design considerations .................................................................................................... ....................... 8-56 latticeecp2m-35 vs. all other latticeecp2m devices.......................................................................... 8-5 6 engineering samples vs. production devices ..................................................................................... ... 8-56 table of contents lattice semiconductor latti ceecp2/m family handbook 5 simulation of the serdes/pcs ................................................................................................... .......... 8-56 reset usage in simulation...................................................................................................... ................ 8-57 16/20-bit word alignment....................................................................................................... ................. 8-57 switching between 10xh, 10x and 20x reference clock multiplier modes using sci ......................... 8-58 switching between 20x to 20xh or 10x to 10xh mode in 16-bit interface............................................ 8-58 off-chip ac coupling........................................................................................................... ................... 8-58 unused quad/channel and power supply ........................................................................................... .. 8-59 reset and power-down control................................................................................................... ........... 8-59 power-down controls description ................................................................................................ .......... 8-61 serdes/pcs reset............................................................................................................... ......................... 8-62 reset sequence and reset state diagram ......................................................................................... ... 8-62 lock status signals definitions................................................................................................ ............... 8-62 power supply sequencing requirements........................................................................................... ............. 8-64 references..................................................................................................................... .................................. 8-64 technical support assistance................................................................................................... ....................... 8-64 revision history ............................................................................................................... ................................ 8-65 appendix a. memory map......................................................................................................... ....................... 8-66 configuration register definition .............................................................................................. .............. 8-66 per quad register overview ..................................................................................................... ............. 8-67 per quad pcs control register details .......................................................................................... ....... 8-68 per quad serdes control register details ....................................................................................... ... 8-71 per quad reset and clock control register details .............................................................................. 8-73 per quad pcs status register details........................................................................................... ........ 8-74 per quad serdes status register details ........................................................................................ ... 8-76 per channel register overview.................................................................................................. ............ 8-77 per channel serdes control register details .................................................................................... .8-80 per channel pcs status register details ........................................................................................ ...... 8-83 per channel serdes status register details..................................................................................... .. 8-84 appendix b. 8b10b symbol codes ................................................................................................. ................. 8-87 appendix c. attribute cross-reference table .................................................................................... ............. 8-88 appendix d. protocol specific serdes setup options ............................................................................. ..... 8-93 appendix e. lattice diamond usage overview ..................................................................................... .......... 8-94 converting an isplever project to lattice diamond ................ ................ ................ ................ ............. 8 -94 importing an isplever design project ........................................................................................... ....... 8-94 adjusting pcs modules .......................................................................................................... ................ 8-94 regenerate pcs modules ......................................................................................................... ............. 8-94 using ipexpress with lattice diamond........................................................................................... ......... 8-95 creating a new simulation project using simulation wizard ................................................................. 8-96 latticeecp2/m sysio usage guide introduction ................................................................................................................... ..................................... 9-1 sysio buffer overview .......................................................................................................... ............................. 9-1 supported sysio standards ...................................................................................................... ......................... 9-1 sysio banking scheme........................................................................................................... ........................... 9-3 v ccio (1.2v/1.5v/1.8v/2.5v/3.3v) .................................................................................................... ........ 9-4 v ccaux (3.3v) ........................................................................................................................ ................... 9-4 v ccj (1.2v/1.5v/1.8v/2.5v/3.3v).................................................................................................... .......... 9-4 input reference voltage (v ref1, v ref2 )................................................................................................... 9-4 v ref1 for ddr memory interface ...................................................................................................... ....... 9-4 mixed voltage support in a bank................................................................................................ .............. 9-4 sysio standards supported by bank .............................................................................................. .......... 9-5 lvcmos buffer configurations ................................................................................................... ...................... 9-6 bus maintenance circuit ........................................................................................................ ................... 9-6 programmable drive ............................................................................................................. .................... 9-6 programmable slew rate ......................................................................................................... ................ 9-6 table of contents lattice semiconductor latti ceecp2/m family handbook 6 open-drain control ............................................................................................................. ...................... 9-6 differential sstl and hstl support ............................................................................................. ........... 9-6 pci support with programmable pciclamp ......................................................................................... .. 9-7 programmable input delay ....................................................................................................... ................ 9-7 software sysio attributes...................................................................................................... ............................. 9-7 io_type ........................................................................................................................ ........................... 9-7 opendrain...................................................................................................................... ....................... 9-8 drive .......................................................................................................................... ............................. 9-8 pullmode ....................................................................................................................... ....................... 9-9 pciclamp....................................................................................................................... ......................... 9-9 slewrate ....................................................................................................................... ....................... 9-9 fixeddelay..................................................................................................................... ..................... 9-10 inbuf .......................................................................................................................... ........................... 9-10 din/dout....................................................................................................................... ........................ 9-10 loc............................................................................................................................ ............................. 9-10 design considerations and usage................................................................................................ ................... 9-10 banking rules .................................................................................................................. ....................... 9-10 differential i/o rules ......................................................................................................... ...................... 9-10 assigning v ref1 / v ref2 groups for referenced inputs.......................................................................... 9-11 differential i/o implementation................................................................................................ ......................... 9-11 lvds........................................................................................................................... ............................ 9-11 blvds .......................................................................................................................... .......................... 9-11 rsds ........................................................................................................................... ........................... 9-11 lvpecl ......................................................................................................................... ......................... 9-12 differential sstl and hstl..................................................................................................... ............... 9-12 technical support assistance................................................................................................... ....................... 9-12 revision history ............................................................................................................... ................................ 9-12 appendix a. hdl attributes for synplicity ? and precision ? rtl synthesis...................................................... 9-13 vhdl synplicity/precision rtl synthesis ........................................................................................ ...... 9-13 verilog synplicity............................................................................................................. ........................ 9-15 verilog precision .............................................................................................................. ....................... 9-16 appendix b. sysio attributes using the isplever design planner user interface... ................ ................ ...... 9-17 appendix c. sysio attributes using preference file (ascii file) ................................................................ .... 9-18 iobuf .......................................................................................................................... ........................... 9-18 locate......................................................................................................................... ......................... 9-18 use din cell................................................................................................................... ..................... 9-19 use dout cell.................................................................................................................. .................. 9-19 pgroup vref .................................................................................................................... .................. 9-19 appendix d. assigning sysio attributes using lattice diamond spreadsheet view ....................................... 9-21 latticeecp2/m sysclock pll/dll design and usage guide introduction ................................................................................................................... ................................... 10-1 clock/control distribution network ............................................................................................. ..................... 10-1 latticeecp2/m top level view................................................................................................... ..................... 10-2 primary clocks ................................................................................................................. ....................... 10-3 secondary clocks ............................................................................................................... .................... 10-3 edge clocks .................................................................................................................... ........................ 10-3 note on primary clocks ......................................................................................................... ................. 10-4 specifying clocks in the design tools .......................................................................................... .......... 10-5 primary-pure and primary-dcs................................................................................................... ........... 10-5 global primary clock and quadrant primary clock ................................................................................ 10-5 note on edge clocks ............................................................................................................ .................. 10-5 sysclock pll ................................................................................................................... ............................. 10-6 functional description......................................................................................................... ............................. 10-6 pll divider and delay blocks................................................................................................... .............. 10-6 table of contents lattice semiconductor latti ceecp2/m family handbook 7 pll inputs and outputs ......................................................................................................... ................. 10-7 pll attributes................................................................................................................. ......................... 10-9 latticeecp2/m pll modules ...................................................................................................... .......... 10-10 latticeecp2/m pll library definitions .......................................................................................... ....... 10-10 dynamic delay adjustment (ehxplld only)....................................................................................... 1 0-11 dynamic phase/duty mode........................................................................................................ ........... 10-11 dynamic phase adjustment/duty cycle select..................................................................................... 10-12 optional external capacitor .................................................................................................... .............. 10-13 pll usage in ipexpress......................................................................................................... ........................ 10-14 configuration tab.............................................................................................................. .................... 10-14 modes .......................................................................................................................... ......................... 10-15 frequency calculation .......................................................................................................... ......................... 10-17 pll modes of operation ......................................................................................................... ....................... 10-17 pll clock injection removal .................................................................................................... ............ 10-17 pll clock phase adjustment..................................................................................................... ........... 10-18 sysclock dll................................................................................................................... ........................... 10-18 dll overview................................................................................................................... ..................... 10-19 dll inputs and outputs ......................................................................................................... ............... 10-19 dll attributes ................................................................................................................. ...................... 10-20 dll library definitions........................................................................................................ .................. 10-21 dll library element i/os....................................................................................................... ............... 10-21 dll modes of operation ......................................................................................................... .............. 10-22 dll usage in ipexpress ......................................................................................................... .............. 10-23 clock dividers (clkdiv)........................................................................................................ ........................ 10-23 clkdiv library element definition .............................................................................................. ......... 10-23 clkdiv declaration in vhdl source code......................................................................................... .10-24 clkdiv usage with verilog - example ............................................................................................ ..... 10-25 clkdiv example circuits ........................................................................................................ ............. 10-25 release behavior............................................................................................................... ................... 10-26 dlldel (slave delay line) ...................................................................................................... ............ 10-27 dqsdll and dqsdel .............................................................................................................. .................... 10-29 dcs (dynamic clock select) ..................................................................................................... .................... 10-29 dcs library element definition ................................................................................................. ........... 10-30 dcs timing diagrams ............................................................................................................ .............. 10-30 dcs usage with vhdl - example .................................................................................................. ...... 10-33 dcs usage with verilog - example ............................................................................................... ....... 10-34 oscillator (oscd) .............................................................................................................. ............................ 10-34 osc library symbol (oscd)...................................................................................................... ................... 10-34 osc usage with vhdl - example.................................................................................................. ...... 10-35 osc usage with verilog - example ............................................................................................... ....... 10-35 input clock sharing............................................................................................................ ............................ 10-36 setting clock preferences...................................................................................................... ........................ 10-37 power supplies ................................................................................................................. ............................. 10-37 technical support assistance................................................................................................... ..................... 10-38 revision history ............................................................................................................... .............................. 10-38 appendix a. primary clock sources and distribution ............................................................................. ....... 10-39 appendix b. pll, dll, clkidv and eclk locations and connectivity ....................................................... 10-42 appendix c. clock preferences .................................................................................................. ................... 10-43 appendix d. lattice diamond usage overview ..................................................................................... ........ 10-46 converting an isplever project to lattice diamond ................ ................ ................ ................ ........... 10- 46 importing an isplever design project ........................................................................................... ..... 10-46 adjusting pcs modules .......................................................................................................... .............. 10-46 regenerate pcs modules ......................................................................................................... ........... 10-46 using ipexpress with lattice diamond........................................................................................... ....... 10-47 table of contents lattice semiconductor latti ceecp2/m family handbook 8 creating a new simulation project using simulation wizard ............................................................... 10-48 latticeecp2/m memory usage guide introduction ................................................................................................................... ................................... 11-1 memories in latticeecp2/m devices.............................................................................................. ................. 11-1 utilizing ipexpress............................................................................................................ ................................ 11-2 ipexpress flow................................................................................................................. ....................... 11-2 memory modules................................................................................................................. ............................. 11-6 single port ram (ram_dq) ? ebr based ........................................................................................... .11-6 true dual port ram (ram_dp_true) ? ebr based ......................................................................... 11-11 pseudo dual port ram (ram_dp) ? ebr based ................................................................................ 11-17 read only memory (rom) - ebr based............................................................................................. .11-20 first in first out (fifo, fifo_dc) ? ebr based................................................................................. 11-23 distributed single port ram (distributed_spram) ? pfu based........................................................ 11-35 distributed dual port ram (distributed_dpram) ? pfu based .......................................................... 11-36 distributed rom (distributed_rom) ? pfu based .............................................................................. 11-3 9 initializing memory ............................................................................................................ ............................. 11-41 initialization file format ..................................................................................................... ................... 11-41 binary file .................................................................................................................... ......................... 11-41 hex file ....................................................................................................................... .......................... 11-42 addressed hex.................................................................................................................. .................... 11-42 technical support assistance................................................................................................... ..................... 11-42 revision history ............................................................................................................... .............................. 11-43 appendix a. attribute definitions.............................................................................................. ...................... 11-44 data_width..................................................................................................................... .................. 11-44 regmode........................................................................................................................ .................... 11-44 resetmode ........ ................ ................. ................ ................ ................ ................ ............. ................. 11-44 csdecode....................................................................................................................... ................... 11-44 writemode...................................................................................................................... .................. 11-44 gsr ............................................................................................................................ .......................... 11-44 latticeecp2/m high-speed i/o interface introduction ................................................................................................................... ................................... 12-1 ddr and ddr2 sdram interfaces overview......................................................................................... ........ 12-1 implementing ddr memory interfaces with latticeecp2/m devices.............................................................. 12-3 dqs grouping................................................................................................................... ...................... 12-3 ddr software primitives........................................................................................................ ................. 12-5 memory read implementation ..................................................................................................... .................. 12-14 dll compensated dqs delay elements ............................................................................................. 12-14 dqs transition detect or automatic clock polarity select ................................................................... 12-1 4 data valid module.............................................................................................................. ................... 12-15 ddr i/o register implementation................................................................................................ ......... 12-15 memory read implementation in software ......................................................................................... .. 12-15 read timing waveforms.......................................................................................................... ............. 12-16 memory write implementation .................................................................................................... .......... 12-19 generic high speed ddr implementation .......................................................................................... .......... 12-22 generic ddr software primitives ................................................................................................ ......... 12-23 design rules/guidelines........................................................................................................ ............... 12-34 ddr usage in isplever ipexpress ................ ................ ................ ................ ................ ................ .............. 12-34 ddr generic.................................................................................................................... ..................... 12-35 configuration tab.............................................................................................................. .................... 12-36 ddr_mem ........................................................................................................................ .................... 12-36 configuration tab.............................................................................................................. .................... 12-37 fcram (?fast cycle random access memory?) interface ........................................................................... 1 2-39 board design guidelines ........................................................................................................ ....................... 12-39 references..................................................................................................................... ................................ 12-39 table of contents lattice semiconductor latti ceecp2/m family handbook 9 technical support assistance................................................................................................... ..................... 12-40 revision history ............................................................................................................... .............................. 12-40 appendix a. ddr generation using ipexpress with lattice diamond........................................................... 12-41 ddr generic.................................................................................................................... ..................... 12-41 configuration tab.............................................................................................................. .................... 12-42 ddr_mem ........................................................................................................................ .................... 12-42 configuration tab.............................................................................................................. .................... 12-43 power estimation and management for latticeecp2/m devices introduction ................................................................................................................... ................................... 13-1 power supply sequencing ........................................................................................................ ....................... 13-1 power-up sequencing ............................................................................................................ ................ 13-1 power-down sequencing.......................................................................................................... .............. 13-1 power sequencing recommendations ............................................................................................... .... 13-1 power calculator hardware assumptions.......................................................................................... .............. 13-2 static power or dc power ....................................................................................................... ............... 13-2 power calculator............................................................................................................... ...................... 13-3 power calculation equations .................................................................................................... .............. 13-3 activity factor calculation.................................................................................................... ............................ 13-5 ambient and junction temperatures and airflow .................................................................................. .......... 13-5 managing power consumption ..................................................................................................... ................... 13-5 power calculator assumptions ................................................................................................... ..................... 13-6 technical support assistance................................................................................................... ....................... 13-7 revision history ............................................................................................................... ................................ 13-7 latticeecp2/m sysdsp usage guide introduction ................................................................................................................... ................................... 14-1 sysdsp block hardware .......................................................................................................... ........................ 14-1 sysdsp block software .......................................................................................................... ......................... 14-2 overview ....................................................................................................................... .......................... 14-2 targeting sysdsp block using ipexpress ......................................................................................... ..... 14-2 targeting the sysdsp block by inference.............. .......................................................................... ................ 14-9 sysdsp blocks in the report file ............................................................................................... ................... 14-11 map report file................................................................................................................ .................... 14-11 place & route (par) report file................................................................................................ .......... 14-12 targeting the sysdsp block using simulink...................................................................................... ............ 14-13 simulink overview.............................................................................................................. ................... 14-13 targeting the sysdsp block by instan tiating primitives......................................................................... ........ 14-14 sysdsp block control signal and data signal descriptions....................................................................... ... 14-14 technical support assistance................................................................................................... ..................... 14-15 revision history ............................................................................................................... .............................. 14-15 appendix a. dsp block primitives ............................................................................................... .................. 14-16 mult18x18b..................................................................................................................... ................... 14-16 mult18x18addsubb............................................................................................................... .......... 14-16 mult18x18addsubsumb............................................................................................................ ..... 14-17 mult18x18macb.................................................................................................................. .............. 14-19 mult36x36b..................................................................................................................... ................... 14-20 mult9x9b....................................................................................................................... ..................... 14-21 mult9x9addsubb................................................................................................................. ............ 14-21 mult9x9addsubsumb.............................................................................................................. ....... 14-22 appendix b. using ipexpress for diamond ........................................................................................ ............ 14-24 invoking ipexpress for diamond ................................................................................................. .......... 14-24 latticeecp2/m sysconfig usage guide introduction ................................................................................................................... ................................... 15-1 general configuration flow ..................................................................................................... ........................ 15-1 configuration pins............................................................................................................. ............................... 15-2 table of contents lattice semiconductor latti ceecp2/m family handbook 10 dedicated control pins ......................................................................................................... .................. 15-3 dual-purpose sysconfig pins.................................................................................................... .......... 15-4 ispjtag pins ................................................................................................................... ....................... 15-6 configuration modes ............................................................................................................ ............................ 15-7 spi mode ....................................................................................................................... ......................... 15-8 spim mode ...................................................................................................................... ..................... 15-10 programming spi serial flash................................................................................................... ........... 15-13 slave serial mode .............................................................................................................. ................... 15-13 slave parallel mode ............................................................................................................ .................. 15-14 ispjtag mode ................................................................................................................... ................... 15-18 configuration options .......................................................................................................... ................. 15-18 device wake-up ................................................................................................................. ........................... 15-21 synchronizing wake-up.......................................................................................................... .............. 15-22 configuration faqs............................................................................................................. ........................... 15-23 general ........................................................................................................................ ......................... 15-23 mode specific.................................................................................................................. ...................... 15-24 technical support assistance................................................................................................... ..................... 15-24 revision history ............................................................................................................... .............................. 15-25 appendix a. lattice diamond usage overview ..................................................................................... ........ 15-26 converting an isplever project to lattice diamond ................ ................ ................ ................ ........... 15- 26 importing an isplever design project ........................................................................................... ..... 15-26 adjusting pcs modules .......................................................................................................... .............. 15-26 regenerate pcs modules ......................................................................................................... ........... 15-26 using ipexpress with lattice diamond........................................................................................... ....... 15-27 creating a new simulation project using simulation wizard ............................................................... 15-28 setting global preferences in diamond .......................................................................................... ...... 15-28 setting bitstream generation options in diamond ............................................................................... 1 5-30 setting security options in diamond ............................................................................................ ........ 15-32 latticeecp2/m s-series configuration encryption usage guide introduction ................................................................................................................... ................................... 16-1 general configuration process .................................................................................................. ...................... 16-1 bitstream encryption/decryption flow ........................................................................................... .................. 16-3 encrypting the bitstream ....................................................................................................... .................. 16-3 programming the 128-bit key .................................................................................................... ............. 16-5 verifying a configuration...................................................................................................... ................... 16-6 file formats ................................................................................................................... .................................. 16-7 decryption flow ................................................................................................................ .................... 16-10 references..................................................................................................................... ................................ 16-11 technical support assistance................................................................................................... ..................... 16-11 revision history ............................................................................................................... .............................. 16-11 appendix a. lattice diamond usage overview ..................................................................................... ........ 16-12 setting global preferences in diamond .......................................................................................... ...... 16-12 setting bitstream generation options in diamond ............................................................................... 1 6-13 setting security options in diamond ............................................................................................ ........ 16-15 latticeecp2/m soft error detection (sed) usage guide introduction ................................................................................................................... ................................... 17-1 sed overview................................................................................................................... ............................... 17-1 hardware description........................................................................................................... ............................ 17-2 signal description ............................................................................................................. ............................... 17-2 sedclkin ....................................................................................................................... ....................... 17-2 sedenable...................................................................................................................... ..................... 17-3 sedclkout ...................................................................................................................... .................... 17-3 sedstart ....................................................................................................................... ...................... 17-3 sedfrcerr...................................................................................................................... .................... 17-3 table of contents lattice semiconductor latti ceecp2/m family handbook 11 sedinprog...................................................................................................................... ..................... 17-3 seddone ........................................................................................................................ ...................... 17-4 sederr ......................................................................................................................... ........................ 17-4 sed flow ....................................................................................................................... .................................. 17-5 sed run time ................................................................................................................... .............................. 17-6 sample code .................................................................................................................... ............................... 17-7 vhdl example................................................................................................................... ..................... 17-7 verilog example ................................................................................................................ ...................... 17-8 technical support assistance................................................................................................... ....................... 17-8 revision history ............................................................................................................... ................................ 17-9 latticeecp2/m hardware checklist introduction ................................................................................................................... ................................... 18-1 power supplies ................................................................................................................. ............................... 18-1 latticeecp2m serdes/pcs power supplies ....................................................................................... 18 -1 power supply sequencing ........................................................................................................ .............. 18-2 power supply ramp .............................................................................................................. ................. 18-2 power estimation ............................................................................................................... ..................... 18-2 configuration.................................................................................................................. .................................. 18-2 jtag interface ................................................................................................................. ....................... 18-3 i/o interface and critical pins ................................................................................................ .......................... 18-4 i/o pin assignments around v ccpll.......................................................................................................................... ........ 18-4 pllcap ......................................................................................................................... ......................... 18-4 ddr/ddr2 memory interface pin assignments..................................................................................... 1 8-5 true-lvds output pin assignments............................................................................................... ........ 18-5 hstl and sstl pin assignments .................................................................................................. ........ 18-5 pci clamp pin assignments ...................................................................................................... ............. 18-5 checklist...................................................................................................................... ..................................... 18-5 technical support assistance................................................................................................... ....................... 18-6 revision history ............................................................................................................... ................................ 18-6 latticeecp3 and latticeecp2m high-speed backplane measurements introduction ................................................................................................................... ................................... 19-1 eye diagram experiment ......................................................................................................... ........................ 19-1 backplane specifications ....................................................................................................... ................. 19-2 test setup parameters .......................................................................................................... ................. 19-2 eye diagram measurements....................................................................................................... ............ 19-2 results and conclusion ......................................................................................................... ................. 19-5 data rate experiment........................................................................................................... ........................... 19-5 backplane specifications ....................................................................................................... ................. 19-5 test setup parameters .......................................................................................................... ................. 19-5 data rate measurements ......................................................................................................... .............. 19-6 results and conclusions........................................................................................................ ................. 19-6 conclusions and design guidelines .............................................................................................. .................. 19-6 references..................................................................................................................... .................................. 19-7 technical support assistance................................................................................................... ....................... 19-7 revision history ............................................................................................................... ................................ 19-7 section iii. latticeecp2/m fa mily handbook revi sion history revision history ............................................................................................................... ................................ 20-1 section i. latticeecp 2/m family data sheet version 03.6, march 2010 www.latticesemi.com 1-1 ds1006 introduction_01.7 june 2008 data sheet ds1006 ? 2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. features ? high logic density for system integration ? 6k to 95k luts ? 90 to 583 i/os ? embedded serdes (latticeecp2m only) ? data rates 250 mbps to 3.125 gbps ? up to 16 channels per device ? pci express, ethernet (1gbe, sgmii), obsai, cpri and serial rapidio. ? sysdsp? block ? 3 to 42 blocks for high performance multiply and accumulate ? each block supports ? one 36x36, four 18x18 or eight 9x9 multipliers ? flexible memory resources ? 55kbits to 5308kbits sysmem? embedded block ram (ebr) ? 18kbit block ? single, pseudo dual and true dual port ? byte enable mode support ? 12k to 202kbits distributed ram ? single port and pseudo dual port ? sysclock analog plls and dlls ? two gplls and up to six splls per device ? clock multiply, divide, phase & delay adjust ? dynamic pll adjustment ? two general purpose dlls per device ? pre-engineered source synchronous i/o ? ddr registers in i/o cells ? dedicated gearing logic ? source synchronous standards support ? spi4.2, sfi4 (d dr mode), xgmii ? high speed adc/dac devices ? dedicated ddr and ddr2 memory support ? ddr1: 400 (200mhz) / ddr2: 533 (266mhz) ? dedicated dqs support ? programmable sysi/o? buffer supports wide range of interfaces ? lvttl and lvcmos 33/25/18/15/12 ? sstl 3/2/18 i, ii ? hstl15 i and hstl18 i, ii ? pci and differential hstl, sstl ? lvds, rsds, bus-lvds, mlvds, lvpecl ? flexible device configuration ? 1149.1 boundary scan compliant ? dedicated bank for configuration i/os ? spi boot flash interface ? dual boot images supported ? transfr? i/o for simple field updates ? soft error detect macro embedded ? optional bitstream encryption (latticeecp2/m ?s? versions only) ? system level support ? isptracy? internal logic analyzer capability ? on-chip oscillator for initialization & general use ?1.2v power supply table 1-1. latticeecp2 (including ?s-series?) family selection device ecp2-6 ecp2-12 ecp2-20 ecp2-35 ecp2-50 ecp2-70 luts (k) 6 12 21 32 48 68 distributed ram (kbits) 1224426496136 ebr sram (kbits) 55 221 276 332 387 1032 ebr sram blocks 3 12 15 18 21 60 sysdsp blocks 3 6 7 8 18 22 18x18 multipliers 122428327288 gpll + spll + dll 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2 maximum available i/o 190 297 402 450 500 583 packages and i/o combinations 144-pin tqfp (20 x 20 mm) 90 93 208-pin pqfp (28 x 28 mm) 131 131 256-ball fpbga (17 x 17 mm) 190 193 193 484-ball fpbga (23 x 23 mm) 297 331 331 339 672-ball fpbga (27 x 27 mm) 402 450 500 500 900-ball fpbga (31 x 31 mm) 583 latticeecp2/m family data sheet introduction 1-2 introduction lattice semiconductor latticeecp2 /m family data sheet table 1-2. latticeecp2m (including ?s-series?) family selection introduction the latticeecp2/m family of fpga devices is optimized to deliver high performance features such as advanced dsp blocks, high speed serdes (latticeecp2m family only) and high speed source synchronous interfaces in an economical fpga fabric. this combination was achieved through advances in device architecture and the use of 90nm technology. the latticeecp2/m fpga fabric is optimized with high performance and low cost in mind. the latticeecp2/m devices include lut-based logic, distributed and em bedded memory, phase locked loops (plls), delay locked loops (dlls), pre-engineered source synchronous i/o support, enhanced sysdsp blocks and advanced configu- ration support, including encryption (?s? versions only) and dual boot capabilities. the latticeecp2m device family features high speed serdes with pcs. these high jitter tolerance and low trans- mission jitter serdes with pcs blocks can be configured to support an array of popular data protocols including pci express, ethernet (1gbe and sgmii), obsai and cpri. transmit pre-emphasis and receive equalization settings make serdes suitable for chip to chip and small form factor backplane applications. the isplever ? design tool suite from lattice allows large comp lex designs to be efficiently implemented using the latticeecp2/m fpga family. synthesis library support for latticeecp2/m is available for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the latticeecp2/m device. the isplever tool extracts the timing from the routing and back-annotates it into the design for timing verification. lattice provides many pre-engineered ip (intellectual property) isplevercore? modules for the latticeecp2/m family. by using these ip cores as standardized blocks, de signers are free to concentrate on the unique aspects of their design, increasing their productivity. device ecp2m20 ecp2m35 ecp2m50 ecp2m70 ecp2m100 luts (k) 1934486795 sysmem blocks (18kb) 66 114 225 246 288 embedded memory (kbits) 1217 2101 4147 4534 5308 distributed memory (kbits) 41 71 101 145 202 sysdsp blocks 6 8 22 24 42 18x18 multipliers 24 32 88 96 168 gpll+spll+dll 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2 maximum available i/o 304 410 410 436 520 packages and serdes / i/o combinations 256-ball fpbga (17 x 17 mm) 4 / 140 4 / 140 484-ball fpbga (23 x 23 mm) 4 / 304 4 / 303 4 / 270 672-ball fpbga (27 x 27 mm) 4 / 410 8 / 372 900-ball fpbga (31 x 31 mm) 8 / 410 16 / 416 16 / 416 1152-ball fpbga (35 x 35 mm) 16 / 436 16 / 520 www.latticesemi.com 2-1 ds1006 architecture_01.9 august 2008 data sheet ds1006 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. architecture overview each latticeecp2/m device contains an array of logic bl ocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem? embedded block ram (ebr) and rows of sys- dsp? digital signal processing blocks, as shown in figu re 2-1. in addition, the latticeecp2m family contains serdes quads in one or more of the corners. figure 2-2 shows the block diagram of ecp2m20 with one quad. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram and rom functions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. logic blocks are arranged in a two- dimensional array. only one type of block is used per row. the latticeecp2/m devices contain one or more rows of sysmem ebr blocks. sysmem ebrs are large dedicated 18k fast memory blocks. each sysmem block can be configured in a variety of depths and widths of ram or rom. in addition, latticeecp2/m devices contain up to two rows of dsp blocks. each dsp block has multipliers and adder/accumulators, whic h are the building blocks for comple x signal processing capabilities. the latticeecp2m devices feature up to 16 embedded 3.125gbps serdes (serializer / deserializer) channels. each serdes channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. each group of four serdes channels along with its physical coding sub-layer (pcs) block, creates a quad. the functionality of the serdes/pcs quads can be controlled by memory cells set during device configuration or by registers that are addressable during device operation. the registers in every quad can be programmed by a soft ip interface, referred to as the serd es client interface (sci). these quads ( up to four) are located at the corners of the devices. each pic block encompasses two pios (pio pairs) with t heir respective sysi/o buffers. the sysi/o buffers of the latticeecp2/m devices are arranged in eight banks, allowing the implementation of a wide variety of i/o standards. in addition, a separate i/o bank is provided for the programming interfaces. pio pairs on the left and right edges of the device can be configured as lvds transmit/receive pairs. the pic logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as spi4.2, along with memory interfaces including ddr2. other blocks provided include plls, dlls and configurat ion functions. the latticeecp2/m architecture provides two general plls (gpll) and up to six standard plls ( spll) per device. in addition, each latticeecp2/m family member provides two dlls per device. the gplls and dlls blocks are located in pairs at the end of the bottom- most ebr row; the dll block is located towards the edge of the device. the spll blocks are located at the end of the other ebr/dsp rows. the configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual boot support is located toward the center of this ebr row. the ball grid array (bga) package devices in the latticeecp2/m family supports a sysconfig? port lo cated in the corner between banks four and five, which allows for serial or parallel device configuration. in addition, every device in the family has a jtag port. this family also provides an on -chip oscillator and soft error detect capability. the latticeecp2/m devices use 1.2v as their core voltage. latticeecp2/m family data sheet architecture 2-2 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-1. simplified block diagram, ecp2-6 device (top level) figure 2-2. simplified block diagram, ecp2m20 device (top level) programmable function units (pfus) flexible sysio buffers: lvcmos, hstl, sstl, lvds, and other standards sysdsp blocks multiply and accumulate support sysmem block ram 18kbit dual port sysclock plls and dlls frequency synthesis and clock alignment flexible routing optimized for speed, cost and routability configuration logic, including dual boot and encryption. on-chip oscillator and soft-error detection. configuration port pre-engineered source synchronous support ? ddr1/2 ? spi4.2 ? adc/dac devices flexible sysio buffers: lvcmos, hstl sstl, lvds pre-engineered source synchronous support ? ddr1/2 ? spi4.2 ? adc/dac devices serdes dsp blocks multiply & accumulate support on-chip oscillator programmable function units (pfus) channel 3 channel 2 channel 1 channel 0 sysmem block ram 18kbit dual port configuration logic, including dual boot and encryption, and soft-error detection flexible routing optimized for speed, cost & routability sysclock gplls & gdlls frequency synthesis & clock alignment configuration port sysclock splls 2-3 architecture lattice semiconductor latticeecp2 /m family data sheet pfu blocks the core of the latticeecp2/m device consists of pfu bl ocks, which are provided in two forms, the pfu and pff. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remain- der of this data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, nu mbered 0-3 as shown in figure 2-3. all the interconnec- tions to and from pfu blocks are from routing. there are 50 inputs and 23 outputs associated with each pfu block. figure 2-3. pfu diagram slice slice 0 through slice 2 contain two lut4s feeding two re gisters, whereas slice 3 contains two lut4s only. for pfus, slice 0 and slice 2 can also be configured as distributed memory, a capability not available in the pff. table 2-1 shows the capability of the slices in both pff and pfu blocks along with the operation modes they enable. in addition, each pfu contains some logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchro- nous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-4 shows an overview of the internal logic of the slice. the registers in the slice can be con? gured for positive/negative and edge triggered or level sensitive clocks. table 2-1. resources and modes available per slice slices 0, 1 and 2 have 14 input signals: 13 signals fr om routing and one from the carry-chain (from the adjacent slice or pfu). there are seven outputs: six to routing and one to carry-chain (to the adjacent pfu). slice 3 has 13 input signals from routing and four signals to routing. tabl e 2-2 lists the signals associated with slice 0 to slice 2. slice pfu block pff block resources modes resources modes slice 0 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 1 2 lut4s and 2 registers logic, ripple, rom 2 lut4s and 2 registers logic, ripple, rom slice 2 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 3 2 lut4s logic, rom 2 lut4s logic, rom slice 0 lut4 & carry lut4 & carry d d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 lut4 d d d d ff ff ff ff ff ff 2-4 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-4. slice diagram table 2-2. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fc fast carry-in 1 input inter-slice signal fxa intermediate signal to generate lut6 and lut7 input inter-slice signal fxb intermediate signal to generate lut6 and lut7 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco slice 2 of each pfu is the fast carry chain output 1 1. see figure 2-4 for connection details. 2. requires two pfus. lut4 & carry* lut4 & carry* slice a0 c0 d0 ff* ofx0 f0 q0 a1 b1 c1 d1 ci ci co co ce clk lsr ff* ofx1 f1 q1 f/sum f/sum d d m1 fci from different slice/pfu fco to different slice/pfu lut5 mux m0 from routing to routing fxb fxa b0 for slices 0 and 2, memory control signals are generated from slice 1 as follows: wck is clk wre is from lsr di[3:2] for slice 2 and di[1:0] for slice 0 data wad [a:d] is a 4bit address from slice 1 lut input * not in slice 3 2-5 architecture lattice semiconductor latticeecp2 /m family data sheet modes of operation each slice has up to four potential modes of operation: logic, ripple, ram and rom. logic mode in this mode, the luts in each slice are configured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any four input logic functions can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be cons tructed within one slice. larger look-up tables such as lut6, lut7 and lut8 can be constructed by concatenatin g other slices. note lut8 requires more than four slices. ripple mode ripple mode supports the efficient implementation of small arithmetic functions. in ripple mode, the following func- tions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ? down counter 2-bit ? up/down counter with async clear ? up/down counter with preload (sync) ? ripple mode multiplier building block ? multiplier support ? comparator functions of a and b inputs ? a greater-than-or-equal-to b ? a not-equal-to b ? a less-than-or-equal-to b ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. in this con- figuration (also referred to as ccu2 mode) two additional signals, carry generate and carry propagate, are gener- ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating slices. ram mode in this mode, a 16x4-bit distributed single port ram (spr ) can be constructed using each lut block in slice 0 and slice 2 as a 16x1-bit memory. slice 1 is used to provid e memory address and control signals. a 16x2-bit pseudo dual port ram (pdpr) memory is created by using one s lice as the read-write port and the other companion slice as the read-only port. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distribute d memory primitives that represent th e capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. for more information about using ram in latticeecp2/m devices, please see the list of additional technical documentation at the end of this data sheet. table 2-3. number of slices required to implement distributed ram spr 16x4 pdpr 16x4 number of slices 3 3 note: spr = single port ram, pdpr = pseudo dual port ram 2-6 architecture lattice semiconductor latticeecp2 /m family data sheet rom mode rom mode uses the lut logic; hence, slices 0 through 3 can be used in rom mode. preloading is accomplished through the programming interface during pfu configuration. routing there are many resources provided in the latticeecp2/m devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. the x2 and x6 resources are buffered, allowing the routing of both short and long connections between pfus. the latticeecp2/m family ha s an enhanced routing architecture that produces a compact design. the isplever design tool suite takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysclock phase locked loops (gpll/spll) the sysclock plls provide the ability to synthesize clock frequencies. all the devices in the latticeecp2/m fam- ily support two general purpose plls (gplls) which are full-featured plls. in addition, some of the larger devices have two to six standard plls (splls) that have a subset of gpll functionality. general purpose pll (gpll) the architecture of the gpll is shown in figure 2-5. a description of the gpll functionality follows. clki is the reference frequency (generated either from the pin or from routing) for the pll. clki feeds into the input clock divider block. the clkfb is the feedback signal (generated from clkop or from a user clock pin/ logic). this signal feeds into the feedback divider. the feedback divider is used to multiply the reference fre- quency. the delay adjust block adjusts either the delays of the reference or feedback signals. the delay adjust block can either be programmed during configuration or can be adjusted dynamically. the setup, hold or clock-to-out times of the device can be improved by programming a delay in the feedback or input path of the pll, which will advance or delay the output clock with reference to the input clock. following the delay adjust block, both the input path and feedback signals enter the voltage contro lled oscillator (vco) block. in this block the difference between the input path and feedback signals is used to control the fre- quency and phase of th e oscillator. a lock signal is generated by th e vco to indicate that the vco has locked onto the input clock signal. in dynamic mode, the pll may lose lock after a dynamic delay adjustment and not relock until the t lock parameter has been satisfied. latticeecp2/m devices have two dedicated pins on the left and right edges of the device for connecting optional external capacitors to the vco. this allows the plls to operate at a lower frequency. this is a shared resource that can only be used by one pll (gpll or spll) per side. the output of the vco then enters the post-scalar divider. the post-scalar divider allows the vco to operate at higher frequencies than the clock output (clkop), thereb y increasing the frequency range. a secondary divider takes the clkop signal and uses it to derive lower frequency outputs (clkok). the phase/duty select block adjusts the phase and duty cycle of the clkop signal and generates the clkos signal. the phase/duty cycle set- ting can be pre-programmed or dynamically adjusted. the primary output from the post scalar divider clkop along with the outputs from the secondary divider (clkok) and phase/duty select (clkos) are fed to the clock distribution network. 2-7 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-5. general purpose pll (gpll) diagram standard pll (spll) some of the larger devices have two to six standard plls (splls). splls have the same features as gplls but without delay adjustment capability. splls also provide different parametric s pecifications. for mo re information, please see the list of additional technical documentation at the end of this data sheet. table 2-4 provides a description of the signals in the gpll and spll blocks. table 2-4. gpll and spll blocks signal descriptions signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) rst i ?1? to reset pll counters, vco, charge pumps and m-dividers rstk i ?1? to reset k-divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ?1? indicates pll lock to clki ddamode 1 i dynamic delay enable. ?1?: pin control (dynamic), ?0?: fuse control (static) ddaizr 1 i dynamic delay zero. ?1?: delay = 0, ?0?: delay = on ddailag 1 i dynamic delay lag/lead. ?1?: lead, ?0?: lag ddaidel[2:0] 1 i dynamic delay input dpa modes i dpa (dynamic phase adjust/duty cycle select) mode dphase [3:0] i dpa phase adjust inputs ddduty [3:0] ? dpa duty cycle select inputs 1. these signals are not available in spll. input clock divider (clki) feedback divider (clkfb) delay adjust voltage controlled oscillator post scalar divider (clkop) phase/duty select secondary divider (clkok) clkos clkok clkop lock clkfb clki rst dynamic delay adjustment (from routing or external pin) from clkop (pll internal), from clock net(clkop) or from a user clock (pin or logic) dynamic adjustment pllcap external pin (optional external capacitor) rstk 2-8 architecture lattice semiconductor latticeecp2 /m family data sheet delay locked loops (dll) in addition to plls, the latticeecp2/m family of devices has two dlls per device. clki is the input frequency (generated either from the pin or routing) for the dll. clki feeds into the output muxes block to bypass the dll, directly to the delay chain block and (directly or through divider circuit) to the reference input of the phase frequency detector (pfd) input mux. the reference signal for the pfd can also be generated from the delay chain and clkfb signals. the feedback input to the pfd is generated from the clkfb pin, clki or from tapped signal from the delay chain. the pfd produces a binary number proportional to the phase and frequency difference between the reference and feedback signals. this binary output of the pfd is fed in to a arithmetic logic unit (alu). based on these inputs, the alu determines the correct digital control codes to send to the delay chain in order to better match the refer- ence and feedback signals. this digital code from the al u is also transmitted via th e digital control bus (dcntl) bus to its associated dlldela delay block. the aluhold input allows the user to suspend the alu output at its current value. the uddcntl signal allows the user to latch the current value on the dcntl bus. the dll has two independent clock outputs, clkop and clkos. these outputs can individually select one of the outputs from the tapped delay line. the clkos has optional fi ne phase shift and divider blocks to allow this output to be further modified, if required. the fine phase shift block allows the clkos output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. both the clkos and clkop outputs are available with optional duty cycle correction. divide by two and divide by four frequencies are availa ble at clkos. the lock out- put signal is asserted when the dll is locked. figure 2-6 shows the dll block diagram and table 2-5 provides a description of the dll inputs and outputs. the user can configure the dll for many common functions such as time reference delay mode and clock injection removal mode. lattice provides primitives in its design tools for these functions. for more information about the dll, please see the list of additional technica l documentation at the end of this data sheet. figure 2-6. delay locked loop diagram (dll) clkop clkos lock clkfb clki aluhold dcntl uddcntl phase frequency detector delay3 delay2 delay1 delay0 delay4 reference feedback 9 4 2 4 2 rstn (from routing or external pin) from clkop (dll internal), from clock net (clkop) or from a user clock (pin or logic) arithmetic logic unit lock detect digital control output delay chain output muxes duty cycle 50% duty cycle 50% 2-9 architecture lattice semiconductor latticeecp2 /m family data sheet table 2-5. dll signals dlldela delay block closely associated with each dll is a dlldela block. this is a delay block consisting of a delay line with taps and a selection scheme that selects one of the taps. the dcntl[8:0] bus controls the delay of the clko signal. typi- cally this is the delay setting that the dll uses to achieve phase alignment. this results in the delay providing a cal- ibrated 90 phase shift that is useful in centering a cloc k in the middle of a data cycle for source synchronous data. the clko signal feeds the edge clock network. figure 2-7 shows the connections between the dll block and the dlldela delay block. for more information, please see the list of additional technical documentation at the end of this data sheet. figure 2-7. dlldela delay block pll/dll cascading latticeecp2/m devices have been designed to allow certain combinations of pll (gpll and spll) and dll cas- cading. the allowable combinations are: ? pll to pll supported ? pll to dll supported signal i/o description clki i clock input from external pin or routing clkfb i dll feed input from dll output, clock net, routing or external pin rstn i active low synchronous reset aluhold i active high freezes the alu uddcntl i synchronous enable signal (hold high for two cycles) from routing dcntl[8:0] o encoded digital control signals for pic indel and slave delay calibration clkop o the primary clock output clkos o the secondary clock output with ? ne ph ase shift and/or division by 2 or by 4 lock o active high phase lock indicator dll block clkop clkos lock clko clki clkfb clki dlldela delay block pll_pio dll_pio routing routing clkfb_ck eclk1 clkop gdllfb_pio dcntl[8:0] * * * * software selectable 2-10 architecture lattice semiconductor latticeecp2 /m family data sheet the dlls in the latticeecp2/m are used to shift the clock in relation to the data for source synchronous inputs. plls are used for frequency synthesis and clock generation for source synchronous interfaces. cascading pll and dll blocks allows applications to utilize the unique benefits of both dlls and plls. for further information about the dll, please see the list of additional technical documentation at the end of this data sheet. gpll/spll/gdll pio inpu t pin connections (latticeecp2m family only) all latticeecp2m devices contain two gdlls, two gplls and six splls, arranged in quadrants as shown in figure 2-8. in the latticeecp2m devices gplls, splls and gdlls share their input pins. figure 2-8 shows the sharing of splls input pin connections in the upper tw o quadrants and the sharing of gdll, gpll and spll input pin connections in the lower two quadrants. figure 2-8. sharing of pio pins by gpll, spll and gdll in latticeecp2m devices clock dividers latticeecp2/m devices have two clock dividers, one on the left side and one on the right side of the device. these are intended to generate a slower-speed system clock from a high-speed edge clock. the block operates in a 2, 4 or 8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. the clock dividers can be fed from selected pll/dll outputs, dll- dela delay blocks, routing or from an external clock input. the clock divider outputs serve as primary clock sources and feed into the clock distribution network. the reset (rst) control signal resets input and synchro- nously forces all outputs to low. th e release signal releases outputs synchron ously to the input clock. for further information about clock dividers, please see the list of addi tional technical documentation at the end of this data sheet. figure 2-9 shows the clock divider connections. spll spll gpll gdll spll spll_pio spll_pio gpll_pio gdll_pio spll_pio spll spll gpll gdll spll spll_pio spll_pio gpll_pio gdll_pio spll_pio upper left quadrant lower left quadrant upper right quadrant lower right quadrant 2-11 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-9. clock divider connections clock distribution network latticeecp2/m devices have eight quadrant-based primary clocks and eight flexible region-based secondary clocks/control signals. two high performance edge clocks are available on each edge of the device to support high speed interfaces. these clock inputs are selected from external i/os, the sysc lock plls, dlls or routing. these clock inputs are fed throughout the chip via a clock distribution system. primary clock sources latticeecp2/m devices derive clocks from five primary sources: pll (gpll and spll) outputs, dll outputs, clk- div outputs, dedicated clock inputs and routing. latticeecp2/m devices have two to eight sysclock plls and two dlls, located on the left and right sides of the device. there are eight dedicated clock inputs, two on each side of the device, with the exception of the latticeecp2m 256-fpbga package devices which have six dedicated clock inputs on the device. figure 2-10 shows the primary clock sources. rst release 1 2 4 8 clko clkop (gpll) clkop (dll) routing pll pad clkos (gpll) clkos (dll) clkdiv 2-12 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-10. primary clock sources for ecp2-50 primary clock sources to eight quadrant clock selection from routing from routing spll gpll dll pll input pll input dll input note: this diagram shows sources for the ecp2-50 device. smaller latticeecp2 devices have fewer splls. all latticeecp2m device have six splls. clk div clock input clock input pll input pll input dll input clock input clock input clock input clock input clock input clock input spll gpll dll clk div 2-13 architecture lattice semiconductor latticeecp2 /m family data sheet secondary clock/control sources latticeecp2/m devices derive secondary clocks (sc0 through sc7) from eight dedicated clock input pads and the rest from routing. figure 2-11 shows the secondary clock sources. figure 2-11. secondary clock sources secondary clock sources from routing from routing from routing from routing from routing from routing from routing from routing from routing from routing clock input clock input clock input clock input clock input clock input from routing from routing from routing from routing clock input clock input from routing from routing 2-14 architecture lattice semiconductor latticeecp2 /m family data sheet edge clock sources edge clock resources can be driven from a variety of sources at the same edge. edge clock resources can be driven from adjacent edge clock pios, primary clock pios, plls/dlls and clock dividers as shown in figure 2-12. figure 2-12. edge clock sources eight edge clocks (eclk) two clocks per edge sources for bottom edge clocks sources for right edge clocks clock input clock input from routing from routing from routing from routing from routing clock input clock input clock input clock input from routing from routing clock input clock input from routing sources for left edge clocks sources for top edge clocks dll input pll input dll input pll input dlldela dll gpll dll gpll dlldela 2-15 architecture lattice semiconductor latticeecp2 /m family data sheet primary clock routing the clock routing structure in latticeecp2/m devices cons ists of a network of eight primary clock lines (clk0 through clk7) per quadrant. the primary clocks of each quadrant are generated from muxes located in the center of the device. all the clock sources are connected to these muxes. figure 2-13 shows the clock routing for one quadrant. each quadrant mux is identical. if desired, any clock can be routed globally figure 2-13. per quadrant primary clock selection dynamic clock select (dcs) the dcs is a smart multiplexer function available in the primary clock routing. it switches between two independent input clock sources without any glitches or runt pulses. this is achieved regardless of when the select signal is tog- gled. there are two dcs blocks per quadrant; in total, there are eight dcs blocks per device. the inputs to the dcs block come from the center muxes. the output of the dcs is connected to primary clocks clk6 and clk7 (see figure 2-13). figure 2-14 shows the timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information about the dcs, please see the list of additional technical documentation at the end of this data sheet. figure 2-14. dcs waveforms secondary clock/control routing secondary clocks in the latticeecp2 devices are region-based resources. the benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. ebr/dsp rows and a special vertical routing channel bound the secondary cloc k regions. this special vertical routing channel aligns with either the left edge of the center dsp block in the dsp row or the center of the dsp row. figure 2-15 shows clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 35:1 35:1 35:1 35:1 32:1 32:1 32:1 32:1 35:1 35:1 8 primary clocks (clk0 to clk7) per quadrant dcs dcs primary clock sources: plls + dlls + clkdivs + pios + routing clk0 sel dcsout clk1 2-16 architecture lattice semiconductor latticeecp2 /m family data sheet this special vertical routing channel and the eight seco ndary clock regions for the ecp2-50. latticeecp2 devices have four secondary clocks (sc0 to sc3) which are distrubed to every region. the secondary clock muxes are located in the center of the device. figure 2-16 shows the mux structure of the secondary clock routing. secondary clocks sc0 to sc3 are used for clock and control and sc4 to sc7 are used for high fan-out signals. figure 2-15. secondary clock regions ecp2-50 i/o bank 0 i/o bank 1 i/o bank 6 i/o bank 7 i/o bank 2 i/o bank 3 i/o bank 5 i/o bank 4 secondary clock region 1 secondary clock region 2 secondary clock region 3 secondary clock region 4 secondary clock region 5 secondary clock region 6 secondary clock region 7 secondary clock region 8 vertical routing channel regional boundary ebr row regional boundary dsp row regional boundary dsp row regional boundary bank 8 2-17 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-16. secondary clock selection slice clock selection figure 2-17 shows the clock selections and figure 2-18 shows the control selections for slice0 through slice2. all the primary clocks and the four secondary clocks are routed to this clock selection mux. other signals can be used as a clock input to the slices via routing. slice controls are generated from the secondary clocks or other signals connected via routing. if none of the signals are selected for both clock and control then the default value of the mux output is 1. slice 3 does not have any registers; therefore it does not have the clock or control muxes. figure 2-17. slice0 through slice2 clock selection sc0 sc1 sc2 sc3 sc4 sc5 24:1 24:1 24:1 sc6 sc7 24:1 24:1 24:1 24:1 24:1 4 secondary clocks/ce/lsr (sc0 to sc3) per region clock/control secondary clock feedlines: 8 pios + 16 routing high fan-out data 4 high fan-out data signals (sc4 to sc7) per region clock to slice primary clock secondary clock routing vcc 8 4 12 1 25:1 2-18 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-18. slice0 through slice2 control selection edge clock routing latticeecp2/m devices have a number of high-speed edge clocks that are intended for use with the pios in the implementation of high-speed interfaces. there are eight edge clocks per device: two edge clocks per edge. differ- ent pll and dll outputs are routed to the two muxes on the left and right sides of the device. in addition, the clko signal (generated from the dlldela block) is routed to all the edge clock muxes on the left and right sides of the device. figure 2-19 shows the selection muxes for these clocks. figure 2-19. edge clock mux connections slice control secondary clock routing vcc 3 12 1 16:1 left and right edge clocks eclk1 top and bottom edge clocks eclk1/ eclk2 clock input pad routing routing input pad gpll input pad dll output clkop gpll output clkop clko left and right edge clocks eclk2 routing input pad gpll input pad dll output clkos gpll output clkos clko (both mux) 2-19 architecture lattice semiconductor latticeecp2 /m family data sheet sysmem memory latticeecp2/m devices contains a number of sysmem em bedded block ram (ebr). the ebr consists of an 18- kbit ram with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. fifos can be implemented in sysmem ebr blocks by imple- menting support logic with pfus . the ebr block facilitates pa rity checking by supporting an optional parity bit for each data byte. ebr blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. table 2-6. sysmem block con? gurations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1, and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded duri ng device con? guration. by preloading the ram block during the chip con? guration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of ram can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? c design inputs. single, dual and pseudo-dual port modes in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. ebr memory supports two forms of write behavior for single port or dual port operation: 1. normal ? data on the output appears only during a read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. memory mode configurations single port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 true dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 pseudo dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 2-20 architecture lattice semiconductor latticeecp2 /m family data sheet 2. write through ? a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. memory core reset the memory array in the ebr utilizes la tches at the a and b out put ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signal s, which reset the output latches associated with port a and port b, respectively. the global reset (gsrn) signal resets both ports. the output data latches and associ- ated resets for both ports are as shown in figure 2-20. figure 2-20. memory core reset for further information about the sysmem ebr block, please see the the list of additional technical documentation at the end of this data sheet. ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-21. the gsr input to the ebr is always asynchronous. figure 2-21. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn pro g rammable disable rsta l clr reset clock clock enable 2-21 architecture lattice semiconductor latticeecp2 /m family data sheet if an ebr is pre-loaded during configuration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becomes active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restrictions if the ebr syn chronous reset is used and the ebr gsr input is disabled. sysdsp? block the latticeecp2/m family provides a sysdsp block, making it ideally suited for low cost, high performance digital signal processing (dsp) applications. typical functions us ed in these applications are finite impulse response (fir) filters, fast fourier transforms (fft) functions, correlators, reed-solomon/turbo/convolution encoders and decoders. these complex signal processing functions use si milar building blocks such as multiply-adders and mul- tiply-accumulators. sysdsp block approach compared to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with ? xed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticeecp2/m, on the other hand, has many dsp blocks that support different data- widths. this allows the designer to us e highly parallel implementations of dsp functions. the designer can opti- mize the dsp performance vs. area by choosing an appropriat e level of parallelism. figure 2-22 compares the fully serial and the mixed parallel and serial implementations. figure 2-22. comparison of general dsp and latticeecp2/m approaches sysdsp block capabilities the sysdsp block in the latticeecp2/m family supports four functional elements in three 9, 18 and 36 data path widths. the user selects a function element for a dsp block and then selects the width and type (signed/unsigned) of its operands. the operands in the latticeecp2/m family sysdsp blocks can be either signed or unsigned but not mixed within a function element. similarly, the operand widths cannot be mixed within a block. in the latticeecp2/ m family the dsp elements can be concatenated. the resources in each sysdsp block can be con? gured to support the following four elements: multiplier 0 x operand a operand b x operand a operand b x operand a operand b multiplier 1 multiplier k (k adds) output m/k loops single multiplier x operand a accumulator operand b m loops function implemented in general purpose dsp function implemented in latticeecp2/m m/k accumulate + + 2-22 architecture lattice semiconductor latticeecp2 /m family data sheet ? mult (multiply) ? mac (multiply, accumulate) ? multaddsub (multiply, addition/subtraction) ? multaddsubsum (multiply, addition/subtraction, accumulate) the number of elements available on each block depends in the width selected from the three available options x9, x18, and x36. a number of these elements are concatenat ed for highly parallel implementations of dsp functions. table 2-7 shows the capabilities of the block. table 2-7. maximum number of elements in a block some options are available in four elements. the input regist er in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. by selecting ?dynamic operation? the following opera- tions are possible: ? in the ?signed/unsigned? options the operands can be switched between signed and unsigned on every cycle. ? in the ?add/sub? option the accumulator can be switched between addition and subtraction on every cycle. ? the loading of operands can switch between parallel and serial operations. width of multiply x9 x18 x36 mult 841 mac 2 2 ? multaddsub 4 2 ? multaddsubsum 2 1 ? 2-23 architecture lattice semiconductor latticeecp2 /m family data sheet mult sysdsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, a and b, are multiplied and the result is available at the output. the user can enable the input/output and pipeline registers. figure 2-23 shows the mult sysdsp element. figure 2-23. mult sysdsp element multiplier x n m m n m n m n n m m+n m+n (default) clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) pipeline register input register multiplier multiplicand signed a shift register a in shift register b in shift register a out shift register b out output input data register a input data register b output register to multiplier input register signed b to multiplier 2-24 architecture lattice semiconductor latticeecp2 /m family data sheet mac sysdsp element in this case, the two operands, a and b, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers, but the out- put register is always enabled. the output register is used to store the accumulated value. the accumulators in the dsp blocks in the latticeecp2/m family can be initialized dynamically. a regist ered overflow signal is also avail- able. the over? ow conditions are provided later in this document. figure 2-24 shows the mac sysdsp element. figure 2-24. mac sysdsp multiplier x input data register a n m input data register b m n n n m n n m output register output register accumulator multiplier multiplicand signed a serial register b in serial register a in srob sroa output addn accumsload pipeline clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input pipeline register input register pipeline register input register pipeline register to accumulator signed b pipeline input to accumulator to accumulator to accumulator overflow signal m+n (default) m+n+16 (default) m+n+16 (default) preload register register register register 2-25 architecture lattice semiconductor latticeecp2 /m family data sheet multaddsub sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and a2. the user can enable the input, output and pipeline registers. figure 2-25 shows the multaddsub sysdsp element. figure 2-25. multaddsub multiplier multiplier add/sub pipe reg pipe reg n m m n m n m n n m m+n (default) m+n+1 (default) m+n+1 (default) m+n (default) x x n m m n m n n m multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 signed a shift register a in shift register b in shift register a out shift register b out output addn pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register pipeline register pipe reg signed b pipeline register input register input data register a input data register a input data register b input data register b output register to add/sub to add/sub to add/sub 2-26 architecture lattice semiconductor latticeecp2 /m family data sheet multaddsubsum sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. additionally the operands a2 and b2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands a3 and b3. the result of both addition/subtraction are added in a summation block. the user can enable the input, output and pipeline registers. figure 2-26 shows the multaddsubsum sysdsp element. figure 2-26. multaddsubsum clock, clock enable and reset resources global clock, clock enable and reset signals from routing are available to every dsp block. four clock, reset and clock enable signals are selected for the sysdsp block. from four clock sources (clk0, clk1, clk2, clk3) multiplier add/sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m multiplier multiplier multiplier add/sub1 x n m m n m n m n n m x n m m n m n n m sum multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 multiplier b2 multiplicand a2 multiplier b3 multiplicand a3 signed a shift register b in output addn0 pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register to add/sub0 to add/sub0, add/sub1 pipeline register signed b pipeline register input register to add/sub0, add/sub1 pipeline register input register to add/sub1 addn1 pipeline register pipeline register pipeline register shift register a in shift register b out shift register a out input data register a input data register a input data register a input data register a input data register b input data register b input data register b input data register b output register 2-27 architecture lattice semiconductor latticeecp2 /m family data sheet one clock is selected for each input register, pipeline register and output register. similarly clock enable (ce) and reset (rst) are selected from their four respective sources (ce0, ce1, ce2, ce3 and rst0, rst1, rst2, rst3) at each input register, pipeline register and output register. signed and unsigned with different widths the dsp block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. for unsigned operands, unused upper data bits should be ? lled to create a valid x9, x18 or x36 operand. for signed two?s complement operands, sign extension of the most signi? cant bit should be performed until x9, x18 or x36 width is reached. table 2-8 provides an example of this. table 2-8. sign extension example overflow flag from mac the sysdsp block provides an overflow output to indicate that the accumulator has overflowed. when two unsigned numbers are added and the result is a smaller number than the accumulator, ?roll-over? is said to have occurred and an overflow signal is indicated. when two positive numbers are added with a negative sum and when two negative numbers are added with a positive sum, then the accumulator ?roll-over? is said to have occurred and an overflow signal is indicated. note that when overflow occurs the overflow flag is present for only one cycle. by counting these overflow pulses in fpga logic, larger accumulators can be constructed. the conditions overflow signals for signed and unsigned operands are listed in figure 2-27. figure 2-27. accumulator over? ow/under? ow number unsigned unsigned 9-bit unsigned 18-bit signed two?s complement signed 9 bits two?s complement signed 18 bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 n/a n/a n/a 1010 111111010 111111111111111010 000000000 000000001 000000010 000000011 111111101 111111110 111111111 overflow signal is generated for one cycle when this boundary is crossed 0 +1 +2 +3 -3 -2 -1 unsigned operation signed operation 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 -254 -255 -256 000000000 000000001 000000010 000000011 111111101 111111110 111111111 carry signal is generated for one cycle when this boundary is crossed 0 1 2 3 509 510 511 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 258 257 256 2-28 architecture lattice semiconductor latticeecp2 /m family data sheet ipexpress? the user can access the sysdsp block via the isplever ipex press tool, which provides the option to configure each dsp module (or group of modules) or by direct hdl instantiation. in addition, lattice has partnered with the mathworks ? to support instanti ation in the simulink ? tool, a graphical simulation environment. simulink works with isplever to dramatically shorten the dsp design cycle in lattice fpgas. optimized dsp functions lattice provides a library of optimized dsp ip functions. some of the ip cores planned for the latticeecp2/m dsp include the bit correlator, fast fourier transform, fini te impulse response (fir) filter, reed-solomon encoder/ decoder, turbo encoder/decoder and convolutional encoder/decoder. please contact lattice to obtain the latest list of available dsp ip cores. resources available in t he latticeecp2/m family table 2-9 shows the maximum number of multipliers for each member of the latticeecp2/m family. table 2-10 shows the maximum available ebr ram blocks in each latticeecp2/m device. ebr blocks, together with distrib- uted ram can be used to store variables locally for fast dsp operations. table 2-9. maximum number of dsp blocks in the latticeecp2/m family table 2-10. embedded sram in the latticeecp2/m family device dsp block 9x9 multiplier 18 x18 multiplier 36x36 multiplier ecp2-6 3 24 12 3 ecp2-12 6 48 24 6 ecp2-20 7 56 28 7 ecp2-35 8 64 32 8 ecp2-50 18 144 72 18 ecp2-70 22 176 88 22 ecp2m20 6 48 24 6 ecp2m35 8 64 32 8 ecp2m50 22 176 88 22 ecp2m70 24 192 96 24 ecp2m100 42 336 168 42 device ebr sram block total ebr sram (kbits) ecp2-6 3 55 ecp2-12 12 221 ecp2-20 15 277 ecp2-35 18 332 ecp2-50 21 387 ecp2-70 60 1106 ecp2m20 66 1217 ecp2m35 114 2101 ecp2m50 225 4147 ecp2m70 246 4534 ecp2m100 288 5308 2-29 architecture lattice semiconductor latticeecp2 /m family data sheet latticeecp2/m dsp performance table 2-11 lists the maximum performance in millions of ma c operations per second (mma c) for each member of the latticeecp2/m family. table 2-11. dsp performance for further information about the sysdsp block, please see the list of additional technical information at the end of this data sheet. programmable i/o cells (pic) each pic contains two pios connected to their respective sysi/o buffers as shown in figure 2-28. the pio block supplies the output data (do) and the tri-state control signal (to) to the sysi/o buffer and receives input from the buffer. table 2-12 provides the pio signal list. device dsp block dsp performance gmac ecp2-6 3 3.9 ecp2-12 6 7.8 ecp2-20 7 9.1 ecp2-35 8 10.4 ecp2-50 18 23.4 ecp2-70 22 28.6 ecp2m20 6 7.8 ecp2m35 8 10.4 ecp2m50 22 28.6 ecp2m70 24 31.2 ecp2m100 42 54.6 2-30 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-28. pic diagram two adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?) as shown in figure 2-28. the pad labels ?t? and ?c? distinguish the two pios. approximately 50% of the pio pairs on the left and right edges of the device can be configured as true lvds outputs. all i/o pairs can operate as inputs. opos1 oneg1 td inck** indd inff ipos0 ipos1 clk ce lsr gsrn clk1 clk0 ceo cei sysio buffer pada ?t? padb ?c? lsr gsr eclk1 ddrclkpol* *signals are available on left/right/bottom edges only. ** selected blocks. iold0 di tristate register block output register block input register block control muxes piob pioa opos0 opos2* oneg0 oneg2* dqsxfer* qpos1* qneg1* qneg0* qpos0* iolt0 eclk2 2-31 architecture lattice semiconductor latticeecp2 /m family data sheet table 2-12. pio signals list pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for operating in a variety of modes along with the necessary clock and selec- tion logic. input register block the input register blocks for pios in left, right and bottom edges contain delay elements and registers that can be used to condition high-speed interface signals, such as ddr memory interfaces and source synchronous inter- faces, before they are passed to the device core. figure 2-29 shows the diagram of the input register block for left, right and bottom edges. the input register block for the top edge contains one memory element to register the input signal as shown in figure 2-30. the following description applies to the input register block for pios in the left, right and bottom edges of the device. input signals are fed from the sysi/o buffer to the input regi ster block (as signal di). if desired, the in put signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and, in selected blocks, the input to the dqs delay block. if an input delay is desired, designers can select either a fixed delay or a dynamic delay del[3:0]. the delay, if selected, reduces input register hold time requirements when using a global clock. the input block allows three modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in ddr mode, two registers are used to sample the data on the positive and negative edges of the dqs signal, creating two data streams, d0 and d1. these two data streams are synchronized with the system cl ock before entering the co re. further discussion on this topic is in the ddr memory section of this data sheet. name type description ce0, ce1 control from the core clock enab les for input and output block flip-flops clk0, clk1 control from the core system clocks for input and output blocks eclk1, eclk2 control from the core fast edge clocks lsr control from the core local set/reset gsrn control from routing global set/reset (active low) inck 2 input to the core input to primary clock network or pll reference inputs dqs input to pio dqs signal from logic (routing) to pio indd input to the core unregistered data input to core inff input to the core registered input on positive edge of the clock (clk0) ipos0, ipos1 input to the core double data rate registered inputs to the core qpos0 1 , qpos1 1 input to the core gearbox pipelined inputs to the core qneg0 1 , qneg1 1 input to the core gearbox pipelined inputs to the core opos0, oneg0, opos2, oneg2 output data from the core output signal s from the core for sdr and ddr operation opos1 oneg1 tristate control from the core signal s to tristate register block for ddr operation del[3:0] control from the core dy namic input delay control bits td tristate control from the core tristate signal from the core used in sdr operation ddrclkpol control from clock polarity bus controls the pola rity of the clock (clk0) that feed the ddr input block dqsxfer control from core controls signal to the output block 1. signals available on left/right/bottom only. 2. selected i/o. 2-32 architecture lattice semiconductor latticeecp2 /m family data sheet by combining input blocks of the complementary pios and sharing some registers from output blocks, a gearbox function can be implemented, which takes a double data rate signal applied to pioa and converts it as four data streams, ipos0a, ipos1a, ipos0b and ipos1b. figure 2- 29 shows the diagram using this gearbox function. for more information about this topic, please see information regarding additional documentation at the end of this data sheet. the signal ddrclkpol controls the pola rity of the clock used in the synchr onization registers. it ensures ade- quate timing when data is transferred from the dqs to the system clock domain. for further information about this topic, see the ddr memory section of this data sheet. figure 2-29. input register block for left, right and bottom edges clock transfer registers clock transfer registers sdr & sync registers d1 d2 d0 ddr registers d q d-type d q d-type d q d-type d q d-type /latch d q d-type 0 1 d q d q 0 1 fixed delay dynamic delay di (from sysio buffer) di (from sysio buffer) inck** indd ipos0a qpos0a ipos1a qpos1a del [3:0] clk0 (of pio a) delayed dqs 0 1 clka dq d q d q 0 1 0 1 d q d q 0 1 d q d q 0 1 fixed delay dynamic delay inck** indd ipos0b qpos0b ipos1b qpos1b del [3:0] clk0 (of pio b) delayed dqs clkb /latch true pio (a) in lvds i/o pair comp pio (b) in lvds i/o pair d-type* d-type* d-type /latch d-type /latch d-type* d-type* from routing to routing d1 d2 d0 ddr registers sdr & sync registers 0 1 ddrsrc gearbox configuration bit ddrclkpol ddrclkpol *shared with output register **selected pio. note: simplified version does not show ce and set/reset details from routing to routing to dqs delay block** to dqs delay block** d-type d-type d-type 2-33 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-30. input register block top edge output register block the output regist er block provides the ability to register signals from the core of the device before they are passed to the sysi/o buffers. the blocks on the pios on the left, right and bottom contain a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-31 shows the diagram of the output register block for pios on the left, right and the bottom edges. figure 2-32 shows the diagram of the output register block for pios on the top edge of the device. in sdr mode, oneg0 feeds one of the flip-flops that then feeds the output. the flip-flop can be configured as a d- type or latch. in ddr mode, oneg0 and opos0 are fed into registers on the positive edge of the clock. then at the next clock cycle this registered opos0 is latched. a multiplexer running off the sa me clock selects the correct register for feeding to the output (d0). by combining the output blocks of the complementary pios and sharing some registers from input blocks, a gear- box function can be implemented, that takes four data streams: oneg0a, oneg1a, oneg1b and oneg1b. figure 2-32 shows the diagram using this gearbox function. for more information about this topic, please see infor- mation regarding additional documentation at the end of this data sheet. fixed delay dynamic delay note: simplified version does not show ce and set/reset details. *on selected blocks. to routing di (from sysio buffer) clk0 (from routing) del[3:0] inck* indd d-type ipos0 /latch dq 2-34 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-31. output and tristate block for left, right and bottom edges clock transfer registers oneg1 clka to opos1 from routing td dq dq dq 0 1 0 1 0 1 dq dq dq 0 1 0 1 d q d-type * d q latch d q 0 1 0 1 0 1 0 1 oneg0 opos0 do programmable control programmable control 0 1 eclk1 eclk2 clk1 tristate logic tristate logic output logic true pio (a) in lvds i/o pair to sysio buffer oneg1 clkb to opos1 from routing td d q d q d q 0 1 0 1 0 1 d q d-type /latch d-type /latch d-type /latch d-type /latch dq dq 0 1 0 1 d q dq latch d-type d-type latch latch d-type latch d-type latch dq oneg0 opos0 do eclk1 eclk2 clk1 output logic to sysio buff er comp pio (b) in lvds i/o pair (clkb) (clka) d-type * d-type* d-type* clock transfer registers ddr output registers ddr output registers * shared with input register note: simplified version does not show ce and set/reset details 0 1 dqsxfer dqsxfer 0 1 0 1 2-35 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-32. output and tristate block, top edge tristate register block the tristate register block prov ides the ability to register tr i-state control signals from t he core of the device before they are passed to the sysi/o buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-31 shows the diagram of the tristate register block with the output block for the left, right and bottom edges and figure 2-32 shows the diagram of the tristate register block with the output block for the top edge. in sdr mode, oneg1 feeds one of the flip-flops that then feeds the output. the flip-flop can be configured a d- type or latch. in ddr mode, oneg1 and opos1 are fed into registers on the positive edge of the clock. then in the next clock the registered opos1 is latched. a multiplexer running off the same clock cycle selects the correct register for feeding to the output (d0). control logic block the control logic block allows the selection and modification of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (eclk1/ eclk2) and a dqs signal provided from the programmable dqs pin and provided to the input register block. the clock can optionally be inverted. ddr memory support certain pics have additional circuitry to allow the implementation of high speed source synchronous and ddr memory interfaces. the support varies by the edge of the device as detailed below. left and right edges pics on these edges have registered elements that supp ort ddr memory interfaces. one of every 16 pios con- tains a delay element to facilitate the generation of dqs signals. the dqs si gnal feeds the dqs bus that spans the set of 16 pios. figure 2-33 shows the assignment of dqs pins in each set of 16 pios. bottom edge pics on the bottom edge have registered elements that support ddr memory interfaces. one of every 18 pios contains a delay element to facilitate the generation of dqs sign als. the dqs signal feeds the dqs bus that spans the set of 18 pios. figure 2-34 shows the assignment of dqs pins in each set of 18 pios. to oneg1 note: simplified version does not show ce and set/reset details. from routing td d q d-type 0 1 0 1 d q d-type /latch 0 1 oneg0 do eclk1 eclk2 clk1 tristate logic output logic to sys io buffer (clka) 0 1 /latch 2-36 architecture lattice semiconductor latticeecp2 /m family data sheet top edge the pics on the top edge are different from pios on the left, right and bottom edges. pios on this edge do not have ddr registers or dqs signals. the exact dqs pins are shown in a dual function in the lo gic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table. the dqs signal from the bus is used to strobe the ddr data from the memory into input regi ster blocks. interfaces on the left and right edges are designed for ddr mem- ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits of data. figure 2-33. dqs input routing for the left and right edges of the device pio b pio a pio b pio a assigned dqs pin dqs delay sysio buffer pada "t" padb "c" lvds pair pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair 2-37 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-34. dqs input routing for the bottom edge of the device dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment. however, in ddr memories the clock (referred to as dqs) is not free-running so this approach cannot be used. the dqs delay block provides the required clock alignment fo r ddr memory interfaces. the dqs signal (selected pios only, as shown in figure 2-35) feeds from the pad through a dqs delay element to a dedicated dqs routing resource. the dqs signal also feeds polarity control logic, which controls the polarity of the clock to the sync registers in the input register blocks. figure 2-35 and figure 2-36 show how the dqs transi- tion signals are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dedicated dlls (ddr_dll) on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-35. the dll loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. pio b pio a pio b pio a assigned dqs pin dqs delay sysio buffer pada "t" padb "c" lvds pair pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio b pio a pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair 2-38 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-35. edge clock, dll calibr ation and dqs local bus distribution i/o bank 5 note: bank 8 is not shown. i/o bank 4 i/o b a n k 6 i/o b a n k 3 i/o b a n k 2 i/o bank 0 i/o bank 1 ddr_dll (right) i/o b a n k 7 ddr_dll (left) eclk1 eclk2 delayed dqs polarity control dqsxfer dqs delay control bus dqs input spans 18 pios spans 16 pios 2-39 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-36. dqs local bus polarity control logic in a typical ddr memory interface design, the phase relationship between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticeecp2/m family contains dedicated circuits to transfer data between these domains. to prevent set-up and hold violations, at the domain transfer between dqs (delayed) and the system clock, a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register block. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr me mories, dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects the first dqs rising edge after the pre- amble state. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer ddr datain pad di clk1 cei pio sysio buffer gsr dqs to sync reg. dqs to ddr reg. dqs strobe pad pio dqsdel polarity control logic dqs calibration bus from dll dqsxfer output register block input register block dqsxfer dcntl[6:0] polarit y control dqs di dqsxferdel* dqsxfer dcntl[6:0] *dqsxferdel shifts eclk1 by 90% and is not associated with a particular pio. dcntl[6:0] eclk1 clk1 eclk2 eclk1 2-40 architecture lattice semiconductor latticeecp2 /m family data sheet dqsxfer latticeecp2/m devices provide a dqsxfer signal to the output buffer to assist it in data transfer to ddr memo- ries that require dqs strobe be shifted 90 o . this shifted dqs strobe is generated by the dqsdel block. the dqsxfer signal runs the span of the data bus. sysi/o buffer each i/o is associated with a ? exible buffer referred to as a sysi/o buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysi/o buffers allow users to implement the wide variety of standards that are found in today?s systems including lvcm os, sstl, hstl, lvds and lvpecl. sysi/o buffer banks latticeecp2/m devices have nine sysi/o buffer banks: eight banks for user i/os arranged two per side. the ninth sysi/o buffer bank (bank 8) is located adjacent to bank 3 and has dedicated/shared i/os for configuration. when a shared pin is not used for configuration it is available as a user i/o. each bank is capable of supporting multiple i/o standards. each sysi/o bank has its own i/o supply voltage (v ccio ). in addition, each bank, except bank 8, has voltage references, v ref1 and v ref2 , which allow it to be completely independent from the others. bank 8 shares two voltage references, v ref1 and v ref2 , with bank 3. figure 2-37 shows the nine banks and their associated supplies. in latticeecp2/m devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos and pci) are powered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as fixed threshold inputs independent of v ccio . each bank can support up to two separate v ref voltages, v ref1 and v ref2 , that set the threshold for the refer- enced input buffers. some dedicated i/o pins in a bank c an be configured to be a reference voltage supply pin. each i/o is individually configurable based on the bank?s supply and reference voltages. 2-41 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-37. latticeecp2 banks v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd bank 6 v ccio6 v ref2(6) bank 5 bank 4 v ref1(0) gnd bank 0 v ccio0 v ref2(0) v ref1(1) gnd bank 1 v ccio1 v ref2(1) gnd bank 8 v ccio8 left rig ht top v ref1(5) gnd v ccio5 v ref2(5) v ref1(4) gnd v ccio4 v ref2(4) bottom 2-42 architecture lattice semiconductor latticeecp2 /m family data sheet figure 2-38. latticeecp2m banks latticeecp2/m devices contain two types of sysi/o buffer pairs. 1. top (bank 0 and bank 1) sysi/o buffer pairs (single-ended outputs only) ? the sysi/o buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be con - figured as a differential input. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. bottom (bank 4 and bank 5) sysi/o buffer pairs (single-ended outputs only) ? the sysi/o buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two v ref1(5) gnd v ccio5 v ref2(5) v ref1(4) gnd v ccio4 v ref2(4) v ref1(0) gnd v ccio0 v ref2(0) v ref1(1) gnd v ccio1 v ref2(1) v ref1(7) gnd v ccio7 v ref2(7) v ref1(6) gnd v ccio6 v ref2(6) v ref1(2) gnd v ccio2 v ref2(2) v ref1(3) gnd v ccio3 v ref2(3) gnd v ccio8 rig ht bank 2 bank 3 bank 7 bank 6 bank 5 bank 4 bank 0 bank 1 bank 8 bottom serdes quad serdes quad serdes quad serdes quad left top 2-43 architecture lattice semiconductor latticeecp2 /m family data sheet sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be configured as a differential input. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 3. left and right (banks 2, 3, 6 and 7) sysi/o buffer pairs (50% differential and 100% single-ended out- puts) ? the sysi/o buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. one of the ref- erenced input buffers can also be configured as a differential input. in these banks the two pads in the pair are described as ?true? and ?comp?, where the true pad is asso ciated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. ? ? lvds differential output drivers are available on 50% of the buffer pairs on the left and right banks. 4. bank 8 sysi/o buffer pairs (single-ended outputs, only on shared pins when not used by configura- tion) ? the sysi/o buffers in bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be configured as a differential input. ? ? the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. in latticeecp2 devices, only the i/os on the bottom banks have programmable pci clamps. in latticeecp2m devices, the i/os on the left and bottom banks have programmable pci clamps. typical sysi/o i/o be havior during power-up the internal power-on-reset (por ) signal is deactivated when v cc , v ccio8 and v ccaux have reached satisfactory levels. after the por signal is deactiva ted, the fpga core logic becomes active . it is the user?s responsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. for more information about cont rolling the output logic state with valid input logic levels during power-up in latticeecp2/m devices, see the list of additional technical documentation at the end of this data sheet. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buf- fers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered-up before or together with the v cc and v ccaux supplies. supported sysi/o standards the latticeecp2/m sysi/o buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2v, 1.5v, 1.8v, 2.5v and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individual configura- tion options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, mlvds, blvds, lvpecl, rsds, differential sstl and differential hstl. tables 2-13 and 2-14 show the i/ o standards (together with their supply and reference voltages) supported by latticeecp2/m devices. for further information about utilizing the sysi/o buff er to support a variety of standards please see the the list of additional technical information at the end of this data sheet. 2-44 architecture lattice semiconductor latticeecp2 /m family data sheet table 2-13. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lv t t l ? ? lv c m o s 3 3 ? ? lv c m o s 2 5 ? ? lv c m o s 1 8 ? 1 . 8 lv c m o s 1 5 ? 1 . 5 lv c m o s 1 2 ? ? pci 33 ? 3.3 hstl18 class i, ii 0.9 ? hstl15 class i 0.75 ? sstl3 class i, ii 1.5 ? sstl2 class i, ii 1.25 ? sstl18 class i, ii 0.9 ? differential interfaces differential sstl18 class i, ii ? ? differential sstl2 class i, ii ? ? differential sstl3 class i, ii ? ? differential hstl15 class i ? ? differential hstl18 class i, ii ? ? lvds, mlvds, lvpecl, blvds, rsds ? ? 1 when not specified, v ccio can be set anywhere in the valid operating range (page 3-1). 2-45 architecture lattice semiconductor latticeecp2 /m family data sheet table 2-14. supported output standards hot socketing latticeecp2/m devices have been carefully designed to ensure predictable behavior during power-up and power- down. during power-up and power-down sequences, the i/os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. in addition, leakag e into i/o pins is controlled within specified limits. this allows for easy integration with the rest of the system. these capabilities make the la tticeecp2/m ideal for many multiple power supply and hot-swap applications. output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma, 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos18, open drain 4ma, 8ma, 12ma 16ma ? lvcmos15, open drain 4ma, 8ma ? lvcmos12, open drain 2ma, 6ma ? pci33 n/a 3.3 hstl18 class i, ii n/a 1.8 hstl15 class i n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i, ii n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i, ii n/a 1.8 differential hstl18, class i, ii n/a 1.8 differential hstl15, class i n/a 1.5 lvds n/a 2.5 mlvds 1 n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 rsds 1 n/a 2.5 lvcmos33d 1 4ma, 8ma, 12ma, 16ma, 20ma 3.3 1. emulated with external resistors. for more detail, pleas e see information regarding additi onal technical documentation at the end of this data sheet. 2-46 architecture lattice semiconductor latticeecp2 /m family data sheet serdes and pcs (physi cal coding sublayer) latticeecp2m devices feature up to 16 channels of embedded serdes arranged in quads at the corners of the devices. figure 2-39 shows the position of the quad blocks in relation to the pfu array for latticeecp2m70 and latticeecp2m100 devices. table 2-15 shows the location of quads for all the devices. each quad contains four dedicated serdes (ch0 to ch3) for high-speed, full-duplex serial data transfer. each quad also has a pcs block that interfaces to the serdes channels and contains digital logic to support an array of popular data protocols. pcs also contains logic to the interface to fpga core. figure 2-39. serdes quads (latticeecp2m70/latticeecp2m100) table 2-15. available serdes quads per latticeecp2m devices serdes block a differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and de-serializes the data-stream before passing the 8- or 10-bit data to the pcs logic. the transmit channel receives the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen- tial buffers. there is a single transmit clock per quad. figure 2-40 shows a single channel serdes and its inter- face to the pcs logic. each serdes receiver channel provides a recovered clock to the pcs block and to the fpga core logic. device urc quad ulc quad lrc quad llc quad ecp2m20 available ? ? ? ecp2m35 available ? ? ? ecp2m50 available ? available ? ecp2m70 available available available available ecp2m100 available available available available ulc serdes quad urc serdes quad lrc serdes quad llc serdes quad ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0 2-47 architecture lattice semiconductor latticeecp2 /m family data sheet each transmit and receive channel has its independent power supplies. the output and input buffers of each channel also have their own independent power supplies. in addition, there are separate power supplies for pll, terminating resistor per quad. figure 2-40. simplified channel block diagram for serdes and pcs pcs as shown in figure 2-40, the pcs receives the parallel digital data from the deserializer receivers and adjusts the polarity, detects, byte boundary, decodes (8b/10b) and provides clock tolerance compensation (ctc) fifo for changing the clock domain from receiver clock to the fpga clock. for the transmit channel, the pcs block receives the parallel data from the fpga core, encodes it with 8b/10b, adjusts the polarity and passes the 8/10 bit data to the transmit serdes channel. the pcs also provides bypass modes that allow a direct 8-bit or 10-bit interface from the serdes to the fpga logic. the pcs interface to fpga can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the fpga logic. sci (serdes client interface) bus the serdes client interface (sci) is a soft ip interface that allow the ser des/pcs quad block to be controlled by registers as opposed to the configuration memory cells. it is a simple register configuration interface. the isplever design tools from lattice support all modes of the pcs. mo st modes are dedicate d to applications associated with a specific industry standard data prot ocol. other more general purpose modes allow users to define their own operation. with isplever, the user can define the mode for each quad in a design. popular standards such as 10gb ethernet and x4 pci-express and 4x serial rapidio can be implemented using ip (provided by lattice), a single quad (four serdes chann els and pcs) and some additional logic from the core. for further information about serdes, please see the list of additional technical documentation at the end of this data sheet. deserializer 1:8/1:10 polarity adjust equalizer byte boundary detect, 8b/10b decoder ctc fifo down sample fifo up sample fifo 8b/10b encoder polarity adjust serializer tx pll fpga transmit clock recovered clock rx refclk fpga receive clock to fpga core transmit receiver 8/10 bits or 16/20 bits transmit data elastic buffer read clock 16/20 bits receive data from transmit pll (in common block) serdes (analog) pcs (digital) 8:1/10:1 tx refclk 2-48 architecture lattice semiconductor latticeecp2 /m family data sheet ieee 1149.1-compliant boundary scan testability all latticeecp2/m devices have bounda ry scan cells that ar e accessed through an i eee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. in ternal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri? cation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device configuration all latticeecp2/m devices contai n two ports that can be used for device configuration. the test access port (tap), which supports bit-wide configuration, and the sysconfig port, support both byte-wide and serial configuration, including the standa rd spi flash interface. the tap supports bo th the ieee standard 11 49.1 boundary scan specification and the ieee standard 1532 in- system configuration specification. the sysconfig port is a 20-pin interface with six i/os used as dedicated pins with the remainder used as dual-use pins. see tn1108, latticeecp2/m sysconfig usage guide for more information about using the dual-use pins as general purpose i/ os. on power-up, the fpga sram is ready to be configured using the selected sysconfig port. once a configuration port is selected, it will rema in active throughout that c onfiguration cycle. the ieee 1149 .1 port can be activated any time after power-up by sending the appropriate command through the tap port. enhanced configuration option latticeecp2/m devices have enhanced configuration feat ures such as: decryption support, transfr? i/o and dual boot image support. 1. decryption support ? latticeecp2/m devices provide on-chip, one time programmable (otp) non-volatile key storage to support decryption of a 128-bit aes encrypted bitstream, securing designs and deterring design piracy. 2. transfr (transparent field reconfiguration) ? transfr i/o (tfr) is a unique lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispvm ? command. transfr i/o allows i/o states to be frozen dur- ing device configuration. this allows the device to be field updated with a mini mum of system disruption and downtime. see tn1087, minimizing system interruption during configuration using transfr technology , for details. 3. dual boot image support ? dual boot images are supported for applications requiring reliable remote updates of configuration data for the system fpga. after the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. any time after the update the latticeecp2/m can be re-booted from this new configuration file. if there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the latticeecp2/m device can revert back to the original backup configuration and try again. this all can be done without power cycling the system. for more information about device configuration, please see the list of additional technical documentation at the end of this data sheet. soft error detect (sed) support latticeecp2/m devices have dedicated logic to perform crc checks. during configuration, the configuration data bitstream can be checked with the crc lo gic block. in addition, the latticee cp2 device can also be programmed 2-49 architecture lattice semiconductor latticeecp2 /m family data sheet for checking soft errors (sed) in sram. this sed operati on can be run in the background during user mode. if a soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a known good boot image or generate an error signal. for further information about soft error detect (sed) support, please see the list of additional technical documen- tation at the end of this data sheet. external resistor latticeecp2/m devices require a single external, 10k ohm 1% value between the xres pin and ground. device con? guration will not be completed if th is resistor is missing. there is no boundary scan register on the external resistor pad. on-chip oscillator every latticeecp2/m device has an internal cmos oscillato r which is used to derive a master clock for configura- tion. the oscillator and the mast er clock run continuously and are available to user logic after configuration is com- pleted. the software default value of the master clock is 2.5mhz. table 2-16 lists all the available master configuration clock frequencies for normal non-encrypted mode and encrypted mode. when a different master clock is selected during the design proc ess, the following sequence takes place: 1. device powers up with a master clock frequency of 3.1mhz. 2. during configuration, users select a different master clock frequency. 3. the master clock frequency changes to the selected frequency once the clock configuration bits are received. 4. if the user does not select a master clock frequency, then the configuration bitstream defaults to the master clock frequency of 2.5mhz. this internal cmos oscillator is availabl e to the user by routing it as an in put clock to the clock tree. for further information about the use of this oscilla tor for configuration or user mode, plea se see the list of additional technical documentation at the end of this data sheet. table 2-16. selectable master clock (cclk) frequencies during configuration density shifting the latticeecp2/m family is designed to ensure that differ ent density devices in the same family and in the same package have the same pinout. furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. in many cases, it is also possible to shift a lower uti- lization design targeted for a high-density device to a lowe r density device. however, the exact details of the final resource utilization will impact the like lihood of success in each case. design migration between latticeecp2 and latticeecp2m families is not possible. for specific requirements relating to sysconfig pins of the ecp2m50, m70 and m100, see the logic signal connections tables. non-encrypted mode cclk (mhz ) encrypted mode cclk (mhz) 2.5 1 13.0 45.0 2.5 1 4.3 15.0 55.0 5.4 5.4 20.0 60.0 10.0 6.9 26.0 ? 34.0 8.1 30.0 ? 41.0 9.2 34.0 ? 45.0 10.0 41.0 130.0 ? 1. software default frequency. www.latticesemi.com 3-1 ds1006 dc and switching_02.0 march 2010 data sheet ds1006 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. recommended operating conditions 7 absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?absol ute maximum ratings? may cause permanent dam age to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. supply voltage v cc . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . -0.5 to 3.75v input or i/o tristate voltage applied 4 . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . -65 to 150c junction temperature (tj) . . . . . . . . . . . . . . . . . . +125c 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc 1, 4, 5 core supply voltage 1.14 1.26 v v ccaux 1, 3, 4, 5 auxiliary supply voltage 3.135 3.465 v v ccpll pll supply voltage 1.14 1.26 v v ccio 1, 2, 4 i/o driver supply voltage 1.14 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.14 3.465 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 c serdes external power supply (for latticeecp2m family only) v ccib input buffer power supply (1.2v) 1.14 1.26 v input buffer power supply (1.5v) 1.425 1.575 v v ccob output buffer power supply (1.2v) 1.14 1.26 v output buffer power supply (1.5v) 1.425 1.575 v v ccaux33 termination resistor switching power supply 3.135 3.465 v v ccrx 6 receive power supply 1.14 1.26 v v cctx 6 transmit power supply 1.14 1.26 v latticeecp2/m family data sheet dc and switching characteristics 3-2 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet v ccp 6 pll and reference clock buffer power 1.14 1.26 v 1. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . v ccpll must be connected to the same power supply as v cc through careful filtering and decoupling. 2. see recommended voltages by i/o standard in subsequent table. 3. v ccaux ramp rate must not exceed 30mv/s during power-up when transitioning between 0v and 3.3v. 4. for proper power-up configuration, users mu st ensure that the configuration control signals such as the cfgx, initn, programn and done pins are driven to the proper logic levels when the device powers up. the device power-up is triggered by the last of v cc , v ccaux or v ccio8 supplies that reaches its minimum vali d levels. alternatively, if the confi guration control signals are pulled up by v ccio8 , the v ccio8 (configuration i/o bank) voltage must be powered up prior to or at th e same time as the last of v cc or vccaux reaches its minim um lev- els. 5. for power-up, v cc must reach its valid minimum value before powering up v ccaux (latticeecp2/m ?s? version devices only). 6. v ccrx ,v cctx and v ccp must be tied together in each quad and all quads need to be powered up. 7. for more power supply design recommendations, refer to tn1114 electrical recommendations for lattice serdes . hot socketing specifications 1, 2, 3, 4 symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 ? v in ? v ih (max.) ? ? +/-1000 a i hdin 5 serdes average input current when device is powered down and inputs are driven ?? 4ma 1. v cc , v ccaux and v ccio should rise/fall monotonically. v cc and v ccpll must be connected to the same power supply (applies to ecp2-6, ecp2-12 and ecp2-20 only). 2. 0 ? v cc ? v cc (max), 0 ? v ccio ? v ccio (max) or 0 ? v ccaux ? v ccaux (max). 3. i dk is additive to i pu , i pw or i bh . 4. lvcmos and lvttl only. 5. assumes that the device is powered down with all supplies grounded, both p and n inputs driven by a cml driver with maximum a llowed v ccib of 1.575v, 8b10b data and internal ac coupling. symbol parameter min. max. units 3-3 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i il , i ih 1 input or i/o low leakage 0 ? v in ? (v ccio - 0.2v) ? ? 10 a i ih 1 input or i/o high leakage (v ccio - 0.2v) < v in ? 3.6v ? ? 150 a i pu i/o active pull-up current 0 ? v in ? 0.7 v ccio -30 ? -210 a i pd i/o active pull-down current v il (max) ? v in ? v ih (max) 30 ? 210 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7 v ccio -30 ? ? a i bhlo bus hold low overdrive current 0 ? v in ? v ccio ??210a i bhho bus hold high overdrive current 0 ? v in ? v ccio ??-210a v bht bus hold trip points 0 ? v in ? v ih (max) v il (max) ? v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?8?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?6?pf 1. input or i/o leakage current is measured wi th the pin con? gured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25 o c, f = 1.0mhz. 3-4 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2 supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply current ecp2-6 10 ma ecp2-12 20 ma ecp2-20 30 ma ecp2-35 50 ma ecp2-50 70 ma ecp2-70 100 ma i ccaux auxiliary power supply current ecp2-6 24 ma ecp2-12 24 ma ecp2-20 24 ma ecp2-35 24 ma ecp2-50 24 ma ecp2-70 24 ma i ccgpll gpll power supply current (per gp ll) ecp2-35, -50, -70 only 0.5 ma i ccspll gpll power supply current (per spl l) ecp2-35, -50, -70 only 0.5 ma i ccio bank power supply current (per bank) ecp2-6 2 ma ecp2-12 2 ma ecp2-20 2 ma ecp2-35 2 ma ecp2-50 2 ma ecp2-70 2 ma i ccj vccj power supply current all devices 3 ma 1. for further information about supply current, please see the list of additional technical docum entation at the end of this d ata sheet. 2. assumes all outputs are tristated, all input s are configured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. 4. pattern represents a ?blank? configuration data file. 5. t j = 25c, power supplies at normal voltage. 3-5 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2m supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply current ecp2m20 25 ma ecp2m35 50 ma ecp2m50 85 ma ecp2m70 100 ma ecp2m100 100 ma i ccaux auxiliary power supply current ecp2m20 24 ma ecp2m35 24 ma ecp2m50 24 ma ecp2m70 24 ma ecp2m100 24 ma i ccgpll gpll power supply current (per gpll) all devices 0.5 ma i ccspll gpll power supply current (per spll) all devices 0.5 ma i ccio bank power supply current (per bank) ecp2m20 2 ma ecp2m35 2 ma ecp2m50 2 ma ecp2m70 2 ma ecp2m100 2 ma i ccj v ccj power supply current all devices 3 ma 1. for further information about supply current, please see the list of additional technical docum entation at the end of this d ata sheet. 2. assumes all outputs are tristated, all input s are configured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. 4. pattern represents a ?blank? configuration data file. 5. t j = 25c, power supplies at normal voltage. 3-6 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2 initializa tion supply current 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5, 6, 7 units i cc core power supply current ecp2-6 34 ma ecp2-12 54 ma ecp2-20 82 ma ecp2-35 135 ma ecp2-50 187 ma ecp2-70 267 ma i ccaux auxiliary power supply current ecp2-6 30 ma ecp2-12 30 ma ecp2-20 30 ma ecp2-35 30 ma ecp2-50 30 ma ecp2-70 30 ma i ccgpll gpll power supply current (per gpll) ecp2-35, -50, -70 only 0.5 ma i ccspll spll power supply current (per sp ll) ecp2-35, -50, -70 only 0.5 ma i ccio bank power supply current (per bank) all devices 3 ma i ccj vccj power supply current all devices 4 ma 1. until done signal is active. 2. for further information about supply current, please see the list of additional technical documentation at the end of this da ta sheet. 3. assumes all outputs are tristated, all input s are con? gured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. t j = 25 o c, power supplies at nominal voltage. 6. a specific configuration pattern is used that scales with the size of the devi ce; consists of 75% pfu utilization, 50% ebr, a nd 25% i/o con- figuration. 7. values shown in this column are the typical average dc current during configuration. use the po wer calculator tool in ispleve r to find the peak startup current. 3-7 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2m initialization supply current 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5, 6, 7 units i cc core power supply current ecp2m20 41 ma ecp2m35 107 ma ecp2m50 169 ma ecp2m70 254 ma ecp2m100 378 ma i ccaux auxiliary power supply current ecp2m20 30 ma ecp2m35 30 ma ecp2m50 30 ma ecp2m70 30 ma ecp2m100 30 ma i ccgpll gpll power supply current (per gpll) all devices 0.5 ma i ccspll spll power supply current (per spll) all devices 0.5 ma i ccio bank power supply current (per bank) all devices 3 ma i ccj vccj power supply current all devices 4 ma 1. until done signal is active. 2. for further information about supply current, please see the list of additional technical documentation at the end of this da ta sheet. 3. assumes all outputs are tristated, all input s are con? gured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. t j = 25 o c, power supplies at nominal voltage. 6. a specific configuration pattern is used t hat scales with the size of the device; consists of 75% pfu utilization, 50% ebr, a nd 25% i/o con- figuration. 7. values shown in this column are the typical average dc current during configuration. use the po wer calculator tool in ispleve r to find the peak startup current. 3-8 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet serdes power supply requiremen ts (latticeecp2m family only) 1 over recommended operating conditions serdes power (latticeecp2m family only) table 3-1 presents the serdes power for one channel. table 3-1. serdes power 1 symbol description typ. 2 units standby (power down) i cctx-sb v cctx current (per channel) 10 a i ccrx-sb v ccrx current (per channel) 75 a i ccib-sb input buffer current (per channel) 0 a i ccob-sb output buffer current (per channel) 0 a i ccp-sb serdes pll current (per quad) 30 a i ccax33-sb serdes termination current (per quad) 10 a operating (data rate = 3.125 gbps) i cctx-op v cctx current (per channel) 19 ma i ccrx-op v ccrx current (per channel) 34 ma i ccib-op input buffer current (per channel) 4 ma i ccob-op output buffer current (per channel) 13 ma i ccp-op serdes pll current (per quad) 26 ma i ccax33-op serdes termination current (per quad) 0.01 ma 1. equalization enabled, pre-emphasis disabled. 2. t j = 25c, power supplies at nominal voltage. symbol description typ. 2 units p s-1ch-31 serdes power (one channel @ 3.125 gbps) 90 mw p s-1ch-25 serdes power (one channel @ 2.5 gbps) 87 mw p s-1ch-12 serdes power (one channel @ 1.25 gbps) 86 mw p s-1ch-02 serdes power (one channel @ 250 mbps) 76 mw 1. one quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating, pre-emph asis dis- abled, equalization enabled). 2. typical values measured at 25 o c and 1.2v. 3-9 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet sysi/o recommended operating conditions standard v ccio v ref (v) min. typ. max. min. typ. max. lv c m o s 3 . 3 2 3.135 3.3 3.465 ? ? ? lv c m o s 2 . 5 2 2.375 2.5 2.625 ? ? ? lvcmos 1.8 1.71 1.8 1.89 ? ? ? lvcmos 1.5 1.425 1.5 1.575 ? ? ? lv c m o s 1 . 2 2 1.14 1.2 1.26 ? ? ? lv t t l 2 3.135 3.3 3.465 ? ? ? pci 3.135 3.3 3.465 ? ? ? sstl18 2 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 sstl2 2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 2 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl 2 15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl 2 18 class i, ii 1.71 1.8 1.89 0.816 0.9 1.08 lv d s 2 2.375 2.5 2.625 ? ? ? mlvds25 1 2.375 2.5 2.625 ? ? ? lvpecl33 1, 2 3.135 3.3 3.465 ? ? ? blvds25 1, 2 2.375 2.5 2.625 ? ? ? rsds 1, 2 2.375 2.5 2.625 ? ? ? sstl18d_i 2 , ii 2 1.71 1.8 1.89 ? ? ? sstl25d_ i 2 , ii 2 2.375 2.5 2.625 ? ? ? sstl33d_ i 2 , ii 2 3.135 3.3 3.465 ? ? ? hstl15d_ i 2 1.425 1.5 1.575 ? ? ? hstl18d_ i 2 , ii 2 1.71 1.8 1.89 ? ? ? 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. input on this standard does not depend on the value of v ccio . 3-10 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet sysi/o single-ended dc el ectrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) lvcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 -0.3 0.35 v cc 0.65 v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3 v ccio 0.5 v ccio 3.6 0.1 v ccio 0.9 v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 12 -12 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 20 -20 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 sstl18 class ii -0.3 v ref - 0.125 v ref + 0.125 3.6 0.28 v ccio - 0.28 8-8 11 -11 hstl class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 4-4 8-8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8-8 12 -12 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma, where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank. 3-11 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet sysi/o differential electrical characteristics lv d s over recommended operating conditions differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output cl asses (class i and class ii) are supported in this mode. for further information about lvpecl, rsds, mlvds, blvds and other differential interfaces please see the list of additional technical information at the end of this data sheet. parameter description test conditions min. typ. max. units v inp , v inm input voltage 0 ? 2.4 v v cm input common mode voltage half the sum of the two inputs 0.05 ? 2.35 v v thd differential input threshold differ ence between the two inputs +/-100 ? ? mv i in input current power on or power off ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ohm ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv yv od change in v od between high and low ??50mv v os output voltage offset (v op + v om )/2, r t = 100 ohm 1.125 1.20 1.375 v yv os change in v os between h and l ? ? 50 mv i sa output short circuit current v od = 0v driver outputs shorted to ground ??24ma i sab output short circuit current v od = 0v driver outputs shorted to each other ??12ma 3-12 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet lvds25e the top and bottom sides of latticeecp2/m devices sup port lvds outputs via emulated complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possible solution for point-to-point signals. figure 3-1. lvds25e output termination example table 3-2. lvds25e dc conditions lvcmos33d all i/o banks support emulated differential i/o using the lvcmos33d i/o type. this option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an i/o bank with 3.3v vccio. the default drive current for lvcmos33d output is 12ma with the option to change the device strength to 4ma, 8ma, 16ma or 20ma. follow the lvcmos33 specifications for the dc characteristics of the lvcmos33d. parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 158 ? r p driver parallel resistor (+/-1%) 140 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100.5 ? i dc dc output current 6.03 ma + - rs=158 ohms (1%) rs=158 ohms (1%) rp = 140 ohms (1%) rt = 100 ohms (1%) off-chip transmission line, zo = 100 ohm differential vccio = 2.5v (5%) 8 ma vccio = 2.5v (5%) on-chip off-chip on-chip 8 ma 3-13 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet blvds the latticeecp2/m devices support the blvds standard. this standard is emulated using complementary lvc- mos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds multi-point output example table 3-3. blvds dc conditions 1 over recommended operating conditions parameter description typical units zo = 45? zo = 90? v ccio output driver supply (+/- 5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/- 1%) 90.00 90.00 ? r tl driver parallel resistor (+/- 1%) 45.00 90.00 ? r tr receiver termination (+/- 1%) 45.00 90.00 ? v oh output high voltage 1.38 1.48 v v ol output low voltage 1.12 1.02 v v od output differentia l voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.24 10.20 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v r tl r tr r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms 45-90 ohms 45-90 ohms 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma 3-14 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet lvpecl the latticeecp2/m devices support the differential lvpecl standard. this standard is emulated using comple- mentary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the lvpecl input stan- dard is supported by the lvds differential input buffer. th e scheme shown in figure 3-3 is one possible solution for point-to-point signals. figure 3-3. diff erential lvpecl table 3-4. lvpecl dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 3.30 v z out driver impedance 10 ? r s driver series resistor (+/-1%) 93 ? r p driver parallel resistor (+/-1%) 196 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 2.05 v v ol output low voltage 1.25 v v od output differential voltage 0.80 v v cm output common mode voltage 1.65 v z back back impedance 100.5 ? i dc dc output current 12.11 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential off-chip on-chip v ccio = 3.3v (+/-5%) v ccio = 3.3v (+/-5%) r p = 196 ohms (+/-1%) r t = 100 ohms (+/-1%) r s = 93.1 ohms (+/-1%) r s = 93.1 ohms (+/-1%) 16ma 16ma + - off-chip on-chip 3-15 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet rsds the latticeecp2/m devices support differential rsds stan dard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input standard is sup- ported by the lvds differential input buffer. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. resistor values in figure 3-4 are industry standard values for 1% resistors. figure 3-4. rsds (reduced swing differential signaling) table 3-5. rsds dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 294 ? r p driver parallel resistor (+/-1%) 121 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ? i dc dc output current 3.66 ma 1. for input buffer, see lvds table. r s = 294 ohms (+/-1%) r s = 294 ohms (+/-1%) r p = 121 ohms (+/-1%) r t = 100 ohms (+/-1%) on-chip on-chip 8ma 8ma v ccio = 2.5v (+/-5%) v ccio = 2.5v (+/-5%) transmission line, zo = 100 ohm differential + - off-chip off-chip 3-16 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet mlvds the latticeecp2/m devices support the differential mlvds standard. this standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the mlvds input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-5 is one possible solution for mlvds standard implementation. resistor values in figure 3-5 are industry standard values for 1% resistors. figure 3-5. mlvds (multipoint lo w voltage differential signaling) table 3-6. mlvds dc conditions 1 for further information about lvpecl, rsds, mlvds, blvds and other differential interfaces please see the list of additional technical information at the end of this data sheet. parameter description typical units zo=50? zo=70? v ccio output driver supply (+/-5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/-1%) 35.00 35.00 ? r tl driver parallel resistor (+/-1%) 50.00 70.00 ? r tr receiver termination (+/-1%) 50.00 70.00 ? v oh output high voltage 1.52 1.60 v v ol output low voltage 0.98 0.90 v v od output differential voltage 0.54 0.70 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 21.74 20.00 ma 1. for input buffer, see lvds table. 16ma 2.5v + - 2.5v 2.5v + - 2.5v 2.5v + - a m 6 1 heavily loaded backplace, effective zo~50 to 70 ohms differential 50 to 70 ohms +/-1% r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r tr r tl 16ma 2.5v a m 6 1 2.5v + - a m 6 1 2.5v 2.5v r s = 50 to 70 ohms +/-1% 35ohms a m 6 1 16ma + - 16ma oe oe oe oe oe oe oe oe 3-17 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12ma drive) function -7 timing units basic functions 16-bit decoder 3.8 ns 32-bit decoder 4.5 ns 64-bit decoder 5.0 ns 4:1 mux 3.2 ns 8:1 mux 3.4 ns 16:1 mux 3.5 ns 32:1 mux 4.0 ns 1. these timing numbers were generated using the isplever design tool. exact performance may vary with device and tool version. the tool uses internal parameters that have been char acterized but are not tested on every device. register-to-register performance function -7 timing units basic functions 16-bit decoder 599 mhz 32-bit decoder 542 mhz 64-bit decoder 417 mhz 4:1 mux 847 mhz 8:1 mux 803 mhz 16:1 mux 660 mhz 32:1 mux 577 mhz 8-bit adder 591 mhz 16-bit adder 500 mhz 64-bit adder 306 mhz 16-bit counter 488 mhz 32-bit counter 378 mhz 64-bit counter 260 mhz 64-bit accumulator 253 mhz embedded memory functions 512x36 single port ram, ebr output registers 370 mhz 1024x18 true-dual port ram (write through or normal, ebr output regis- ters) 370 mhz 1024x18 true-dual port ram (write through or normal, plc output ? registers) 280 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) 819 mhz 32x4 pseudo-dual port ram 521 mhz 64x8 pseudo-dual port ram 435 mhz dsp functions 18x18 multiplier (all registers) 420 mhz 9x9 multiplier (all registers) 420 mhz 3-18 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet derating timing tables logic timing provided in the following sections of this data sheet and the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. the isplever design tool can provide logic timing numbers at a particular temperature and voltage. 36x36 multiplier (all registers) 372 mhz 18x18 multiplier/accumulate (input and output registers) 295 mhz 18x18 multiplier-add/sub-sum (all reg- isters) 420 mhz dsp ip functions 16-tap fully-parallel fir filter 304 mhz 1024-pt, radix 4, decimation in ? frequency fft 227 mhz 8x8 matrix multiplier 223 mhz register-to-register performance (continued) function -7 timing units 3-19 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2/m external sw itching characteristics 9 over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output ? register lfe2-6 ? 3.50 ? 3.90 ? 4.20 ns lfe2-12 ? 3.50 ? 3.90 ? 4.20 ns lfe2-20 ? 3.50 ? 3.90 ? 4.20 ns lfe2-35 ? 3.50 ? 3.90 ? 4.20 ns lfe2-50 ? 3.50 ? 3.90 ? 4.20 ns lfe2-70 ? 3.70 ? 4.10 ? 4.40 ns lfe2m20 ? 3.90 ? 4.30 ? 4.70 ns lfe2m35 ? 3.90 ? 4.30 ? 4.70 ns lfe2m50 ? 4.50 ? 5.00 ? 5.40 ns lfe2m70 ? 4.50 ? 5.00 ? 5.40 ns lfe2m100 ? 4.50 ? 5.00 ? 5.40 ns t su clock to data setup - pio input register lfe2-6 0.00 ? 0.00 ? 0.00 ? ns lfe2-12 0.00 ? 0.00 ? 0.00 ? ns lfe2-20 0.00 ? 0.00 ? 0.00 ? ns lfe2-35 0.00 ? 0.00 ? 0.00 ? ns lfe2-50 0.00 ? 0.00 ? 0.00 ? ns lfe2-70 0.00 ? 0.00 ? 0.00 ? ns lfe2m20 0.00 ? 0.00 ? 0.00 ? ns lfe2m35 0.00 ? 0.00 ? 0.00 ? ns lfe2m50 0.00 ? 0.00 ? 0.00 ? ns lfe2m70 0.00 ? 0.00 ? 0.00 ? ns lfe2m100 0.00 ? 0.00 ? 0.00 ? ns t h clock to data hold - pio input ? register lfe2-6 1.40 ? 1.70 ? 1.90 ? ns lfe2-12 1.40 ? 1.70 ? 1.90 ? ns lfe2-20 1.40 ? 1.70 ? 1.90 ? ns lfe2-35 1.40 ? 1.70 ? 1.90 ? ns lfe2-50 1.40 ? 1.70 ? 1.90 ? ns lfe2-70 1.40 ? 1.70 ? 1.90 ? ns lfe2m20 1.40 ? 1.70 ? 1.90 ? ns lfe2m35 1.40 ? 1.70 ? 1.90 ? ns lfe2m50 1.80 ? 2.10 ? 2.30 ? ns lfe2m70 1.80 ? 2.10 ? 2.30 ? ns lfe2m100 1.80 ? 2.10 ? 2.30 ? ns 3-20 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t su_del clock to data setup - pio input register with data input delay lfe2-6 1.40 ? 1.70 ? 1.90 ? ns lfe2-12 1.40 ? 1.70 ? 1.90 ? ns lfe2-20 1.40 ? 1.70 ? 1.90 ? ns lfe2-35 1.40 ? 1.70 ? 1.90 ? ns lfe2-50 1.40 ? 1.70 ? 1.90 ? ns lfe2-70 1.40 ? 1.70 ? 1.90 ? ns lfe2m20 1.40 ? 1.70 ? 1.90 ? ns lfe2m35 1.40 ? 1.70 ? 1.90 ? ns lfe2m50 1.40 ? 1.70 ? 1.90 ? ns lfe2m70 1.40 ? 1.70 ? 1.90 ? ns lfe2m100 1.40 ? 1.70 ? 1.90 ? ns t h_del clock to data hold - pio input reg- ister with input data delay lfe2-6 0.00 ? 0.00 ? 0.00 ? ns lfe2-12 0.00 ? 0.00 ? 0.00 ? ns lfe2-20 0.00 ? 0.00 ? 0.00 ? ns lfe2-35 0.00 ? 0.00 ? 0.00 ? ns lfe2-50 0.00 ? 0.00 ? 0.00 ? ns lfe2-70 0.00 ? 0.00 ? 0.00 ? ns lfe2m20 0.00 ? 0.00 ? 0.00 ? ns lfe2m35 0.00 ? 0.00 ? 0.00 ? ns lfe2m50 0.00 ? 0.00 ? 0.00 ? ns lfe2m70 0.00 ? 0.00 ? 0.00 ? ns lfe2m100 0.00 ? 0.00 ? 0.00 ? ns f max_io clock frequency of i/o register and pfu register ecp2/m ?420?357?311mhz general i/o pin parameters (using edge clock without pll) 1 t coe clock to output - pio output register lfe2-6 ? 2.60 ? 2.90 ? 3.20 ns lfe2-12 ? 2.60 ? 2.90 ? 3.20 ns lfe2-20 ? 2.60 ? 2.90 ? 3.20 ns lfe2-35 ? 2.60 ? 2.90 ? 3.20 ns lfe2-50 ? 2.60 ? 2.90 ? 3.20 ns lfe2-70 ? 2.60 ? 2.90 ? 3.20 ns lfe2m20 ? 2.60 ? 2.90 ? 3.20 ns lfe2m35 ? 2.60 ? 2.90 ? 3.20 ns lfe2m50 ? 3.10 ? 3.40 ? 3.70 ns lfe2m70 ? 3.10 ? 3.40 ? 3.70 ns lfe2m100 ? 3.10 ? 3.40 ? 3.70 ns latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-21 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t sue clock to data setup - pio input register lfe2-6 0.00 ? 0.00 ? 0.00 ? ns lfe2-12 0.00 ? 0.00 ? 0.00 ? ns lfe2-20 0.00 ? 0.00 ? 0.00 ? ns lfe2-35 0.00 ? 0.00 ? 0.00 ? ns lfe2-50 0.00 ? 0.00 ? 0.00 ? ns lfe2-70 0.00 ? 0.00 ? 0.00 ? ns lfe2m20 0.00 ? 0.00 ? 0.00 ? ns lfe2m35 0.00 ? 0.00 ? 0.00 ? ns lfe2m50 0.00 ? 0.00 ? 0.00 ? ns lfe2m70 0.00 ? 0.00 ? 0.00 ? ns lfe2m100 0.00 ? 0.00 ? 0.00 ? ns t he clock to data hold - pio input register lfe2-6 0.90 ? 1.10 ? 1.30 ? ns lfe2-12 0.90 ? 1.10 ? 1.30 ? ns lfe2-20 0.90 ? 1.10 ? 1.30 ? ns lfe2-35 0.90 ? 1.10 ? 1.30 ? ns lfe2-50 0.90 ? 1.10 ? 1.30 ? ns lfe2-70 0.90 ? 1.10 ? 1.30 ? ns lfe2m20 0.90 ? 1.10 ? 1.30 ? ns lfe2m35 0.90 ? 1.10 ? 1.30 ? ns lfe2m50 1.20 ? 1.40 ? 1.60 ? ns lfe2m70 1.20 ? 1.40 ? 1.60 ? ns lfe2m100 1.20 ? 1.40 ? 1.60 ? ns t su_dele clock to data setup - pio input register with data input delay lfe2-6 1.00 ? 1.30 ? 1.60 ? ns lfe2-12 1.00 ? 1.30 ? 1.60 ? ns lfe2-20 1.00 ? 1.30 ? 1.60 ? ns lfe2-35 1.00 ? 1.30 ? 1.60 ? ns lfe2-50 1.00 ? 1.30 ? 1.60 ? ns lfe2-70 1.00 ? 1.30 ? 1.60 ? ns lfe2m20 1.20 ? 1.60 ? 1.90 ? ns lfe2m35 1.20 ? 1.60 ? 1.90 ? ns lfe2m50 1.20 ? 1.60 ? 1.90 ? ns lfe2m70 1.20 ? 1.60 ? 1.90 ? ns lfe2m100 1.20 ? 1.60 ? 1.90 ? ns latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-22 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t h_dele clock to data hold - pio input register with input data delay lfe2-6 0.00 ? 0.00 ? 0.00 ? ns lfe2-12 0.00 ? 0.00 ? 0.00 ? ns lfe2-20 0.00 ? 0.00 ? 0.00 ? ns lfe2-35 0.00 ? 0.00 ? 0.00 ? ns lfe2-50 0.00 ? 0.00 ? 0.00 ? ns lfe2-70 0.00 ? 0.00 ? 0.00 ? ns lfe2m20 0.00 ? 0.00 ? 0.00 ? ns lfe2m35 0.00 ? 0.00 ? 0.00 ? ns lfe2m50 0.00 ? 0.00 ? 0.00 ? ns lfe2m70 0.00 ? 0.00 ? 0.00 ? ns lfe2m100 0.00 ? 0.00 ? 0.00 ? ns f max_ioe clock frequency of i/o and pfu register ecp2/m ?420?357?311mhz general i/o pin parameters (using primary clock with pll) 1 t copll 10 clock to output - pio output register lfe2-6 ? 2.30 ? 2.60 ? 2.80 ns lfe2-12 ? 2.30 ? 2.60 ? 2.80 ns lfe2-20 ? 2.30 ? 2.60 ? 2.80 ns lfe2-35 ? 2.30 ? 2.60 ? 2.80 ns lfe2-50 ? 2.30 ? 2.60 ? 2.80 ns lfe2-70 ? 2.30 ? 2.60 ? 2.80 ns lfe2m20 ? 2.30 ? 2.60 ? 2.80 ns lfe2m35 ? 2.30 ? 2.60 ? 2.80 ns lfe2m50 ? 2.60 ? 2.90 ? 3.10 ns lfe2m70 ? 2.60 ? 2.90 ? 3.10 ns lfe2m100 ? 2.70 ? 3.00 ? 3.20 ns t supll clock to data setup - pio input register lfe2-6 0.70 ? 0.80 ? 0.90 ? ns lfe2-12 0.70 ? 0.80 ? 0.90 ? ns lfe2-20 0.70 ? 0.80 ? 0.90 ? ns lfe2-35 0.70 ? 0.80 ? 0.90 ? ns lfe2-50 0.70 ? 0.80 ? 0.90 ? ns lfe2-70 0.70 ? 0.80 ? 0.90 ? ns lfe2m20 0.70 ? 0.80 ? 0.90 ? ns lfe2m35 0.70 ? 0.80 ? 0.90 ? ns lfe2m50 0.70 ? 0.80 ? 0.90 ? ns lfe2m70 0.70 ? 0.80 ? 0.90 ? ns lfe2m100 0.80 ? 0.90 ? 1.00 ? ns latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-23 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t hpll clock to data hold - pio input register lfe2-6 1.00 ? 1.20 ? 1.40 ? ns lfe2-12 1.00 ? 1.20 ? 1.40 ? ns lfe2-20 1.00 ? 1.20 ? 1.40 ? ns lfe2-35 1.00 ? 1.20 ? 1.40 ? ns lfe2-50 1.00 ? 1.20 ? 1.40 ? ns lfe2-70 1.00 ? 1.20 ? 1.40 ? ns lfe2m20 1.00 ? 1.20 ? 1.40 ? ns lfe2m35 1.00 ? 1.20 ? 1.40 ? ns lfe2m50 1.00 ? 1.20 ? 1.40 ? ns lfe2m70 1.00 ? 1.20 ? 1.40 ? ns lfe2m100 1.00 ? 1.20 ? 1.40 ? ns t su_delpll clock to data setup - pio input register with data input delay lfe2-6 1.80 ? 2.00 ? 2.20 ? ns lfe2-12 1.80 ? 2.00 ? 2.20 ? ns lfe2-20 1.80 ? 2.00 ? 2.20 ? ns lfe2-35 1.80 ? 2.00 ? 2.20 ? ns lfe2-50 1.80 ? 2.00 ? 2.20 ? ns lfe2-70 1.80 ? 2.00 ? 2.20 ? ns lfe2m20 1.80 ? 2.00 ? 2.20 ? ns lfe2m35 1.80 ? 2.00 ? 2.20 ? ns lfe2m50 1.90 ? 2.10 ? 2.30 ? ns lfe2m70 1.90 ? 2.10 ? 2.30 ? ns lfe2m100 2.00 ? 2.20 ? 2.40 ? ns t h_delpll clock to data hold - pio input ? register with input data delay lfe2-6 0.00 ? 0.00 ? 0.00 ? ns lfe2-12 0.00 ? 0.00 ? 0.00 ? ns lfe2-20 0.00 ? 0.00 ? 0.00 ? ns lfe2-35 0.00 ? 0.00 ? 0.00 ? ns lfe2-50 0.00 ? 0.00 ? 0.00 ? ns lfe2-70 0.00 ? 0.00 ? 0.00 ? ns lfe2m20 0.00 ? 0.00 ? 0.00 ? ns lfe2m35 0.00 ? 0.00 ? 0.00 ? ns lfe2m50 0.00 ? 0.00 ? 0.00 ? ns lfe2m70 0.00 ? 0.00 ? 0.00 ? ns lfe2m100 0.00 ? 0.00 ? 0.00 ? ns ddr i/o pin parameters 2 t dvadq data valid after dqs (ddr read) ecp2/m ? 0.225 ? 0.225 ? 0.225 ui t dvedq data hold after dqs (ddr read) ecp2/m 0.640 ? 0.640 ? 0.640 ? ui t dqvbs data valid before dqs (ddr write) ecp2/m 0.250 ? 0.250 ? 0.250 ? ui t dqvas data valid after dqs (ddr write) ecp2/m 0.250 ? 0.250 ? 0.250 ? ui f max_ddr ddr clock frequency 6 ecp2/m 95 200 95 166 95 133 mhz ddr2 i/o pin parameters 3 t dvadq data valid after dqs (ddr read) ecp2/m ? 0.225 ? 0.225 ? 0.225 ui t dvedq data hold after dqs (ddr read) ecp2/m 0.640 ? 0.640 ? 0.640 ? ui latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-24 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t dqvbs data valid before dqs (ddr write) ecp2/m 0.250 ? 0.250 ? 0.250 ? ui t dqvas data valid after dqs (ddr write) ecp2/m 0.250 ? 0.250 ? 0.250 ? ui f max_ddr2 ddr clock frequency ecp2/m 133 266 133 200 133 166 mhz spi4.2 i/o pin pa rameters static alignment 4, 8, 11 maximum data rate ecp2-20 ? 750 ? 622 ? 622 mbps ecp2-35 ? 750 ? 622 ? 622 mbps ecp2-50 ? 750 ? 622 ? 622 mbps ecp2-70 ? 750 ? 622 ? 622 mbps ecp2m20 ? 622 ? 622 ? 622 mbps ecp2m35 ? 622 ? 622 ? 622 mbps ecp2m50 ? 622 ? 622 ? 622 mbps ecp2m70 ? 622 ? 622 ? 622 mbps ecp2m100 ? 622 ? 622 ? 622 mbps t dvaclkspi data valid after clk (receive) ecp2-20 ? 0.25 ? 0.25 ? 0.25 ui ecp2-35 ? 0.25 ? 0.25 ? 0.25 ui ecp2-50 ? 0.25 ? 0.25 ? 0.25 ui ecp2-70 ? 0.25 ? 0.25 ? 0.25 ui ecp2m20 ? 0.21 ? 0.21 ? 0.21 ui ecp2m35 ? 0.21 ? 0.21 ? 0.21 ui ecp2m50 ? 0.21 ? 0.21 ? 0.21 ui ecp2m70 ? 0.21 ? 0.21 ? 0.21 ui ecp2m100 ? 0.21 ? 0.21 ? 0.21 ui t dveclkspi data hold after clk (receive) ecp2-20 0.75 ? 0.75 ? 0.75 ? ui ecp2-35 0.75 ? 0.75 ? 0.75 ? ui ecp2-50 0.75 ? 0.75 ? 0.75 ? ui ecp2-70 0.75 ? 0.75 ? 0.75 ? ui ecp2m20 0.79 ? 0.79 ? 0.79 ? ui ecp2m35 0.79 ? 0.79 ? 0.79 ? ui ecp2m50 0.79 ? 0.79 ? 0.79 ? ui ecp2m70 0.79 ? 0.79 ? 0.79 ? ui ecp2m100 0.79 ? 0.79 ? 0.79 ? ui t diaspi data invalid after clock (transmit) ecp2-20 ? 280 ? 280 ? 280 ps ecp2-35 ? 280 ? 280 ? 280 ps ecp2-50 ? 280 ? 280 ? 280 ps ecp2-70 ? 280 ? 280 ? 280 ps ecp2m20 ? 230 ? 230 ? 230 ps ecp2m35 ? 230 ? 230 ? 230 ps ecp2m50 ? 230 ? 230 ? 230 ps ecp2m70 ? 230 ? 230 ? 230 ps ecp2m100 ? 230 ? 230 ? 230 ps latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-25 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t dibspi data invalid before clock (transmit) ecp2-20 ? 280 ? 280 ? 280 ps ecp2-35 ? 280 ? 280 ? 280 ps ecp2-50 ? 280 ? 280 ? 280 ps ecp2-70 ? 280 ? 280 ? 280 ps ecp2m20 ? 230 ? 230 ? 230 ps ecp2m35 ? 230 ? 230 ? 230 ps ecp2m50 ? 230 ? 230 ? 230 ps ecp2m70 ? 230 ? 230 ? 230 ps ecp2m100 ? 230 ? 230 ? 230 ps xgmii i/o pin parameters (312 mbps) 5 t suxgmii data setup before read clock ecp2/m 480 ? 480 ? 480 ? ps t hxgmii data hold after read clock ecp2/m 480 ? 480 ? 480 ? ps t dvbckxgmii data valid before clock ecp2/m 960 ? 960 ? 960 ? ps t dvackxgmii data valid after clock ecp2/m 960 ? 960 ? 960 ? ps primary f max_pri 7 frequency for primary clock tree ecp2/m ? 420 ? 357 ? 311 mhz t w_pri clock pulse width for primary clock ecp2/m 0.95 ? 1.19 ? 2.00 ? ns t skew_pri primary clock skew within a bank ecp2/m ? 300 ? 360 ? 420 ps edge clock f max_edge 7 frequency for edge clock ecp2/m ? 420 ? 357 ? 311 mhz t w_edge clock pulse width for edge clock ecp2/m 0.95 ? 1.19 ? 2.00 ? ns t skew_edge edge clock skew within an edge of the device ecp2/m ?300?360?420ps 1. general timing numbers based on lvcmos 2.5, 12ma, 0pf load. 2. ddr timing numbers based on sstl25 for bga packages only. 3. ddr2 timing numbers based on sstl18 for bga packages only. 4. spi4.2 and sfi4 timing numbers based on lvds25 for bga packages only. 5. xgmii timing numbers based on hstl class i. a corresponding left/ri ght dedicated clock buffer is used when using the spi4.2 i nterface to the left or right edge of the device. for spi4.2 mode, the softwa re tool will help in selecting the appropriate clock buffer. 6. ip will be used to support ddr and ddr2 memory data rates do wn to 95mhz. this approach uses a free-running clock and pfu regi ster to sample the data instead of the hardwired ddr memory interface. 7. using the lvds i/o standard. 8. ecp2-6 and ecp2-12 do not support spi4.2 9. the ac numbers do not apply to pclk6 and pclk7. 10. applies to clkop only. 11. please refer to tn1159, latticeecp2/m pin assignment recommendations for best performance. latticeecp2/m external sw itching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. 3-26 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-6. spi4.2 parameters transmit parameters receiver parameters t dvaclkspi t dveclkspi t diaspi t dibspi t diaspi t dibspi data (rdat,rctl) rdtclk t dveclkspi t dvaclkspi clk data (tdat, tctl) 3-27 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-7. ddr and ddr2 parameters figure 3-8. xgmii parameters transmit parameters receiver parameters t dqvbs t dqvas t dqvbs t dqvas dqs dq dqs dq t dvadq t dvedq t dvedq t dvadq transmit parameters receiver parameters t t t t clock data clock data t suxgmii t hxgmii t suxgmii t hxgmii dvbckxgmii dvackxgmii dvackxgmii dvbckxgmii 3-28 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2/m internal sw itching characteristics 1 over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) ? 0.180 ? 0.198 ? 0.216 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) ? 0.304 ? 0.331 ? 0.358 ns t lsr_pfu set/reset to output of pfu (asynchro- nous) ? 0.600 ? 0.655 ? 0.711 ns t sum_pfu clock to mux (m0,m1) input setup time 0.128 ? 0.129 ? 0.129 ? ns t hm_pfu clock to mux (m0,m1) input hold time -0.051 ? -0.049 ? -0.046 ? ns t sud_pfu clock to d input setup time 0.061 ? 0.071 ? 0.081 ? ns t hd_pfu clock to d input hold time 0.002 ? 0.003 ? 0.003 ? ns t ck2q_pfu clock to q delay, (d-type register configu- ration) ? 0.285 ? 0.309 ? 0.333 ns pfu dual port memory mode timing t coram_pfu clock to output (f port) ? 0.902 ? 1.083 ? 1.263 ns t sudata_pfu data setup time -0.172 ? -0.205 ? -0.238 ? ns t hdata_pfu data hold time 0.199 ? 0.235 ? 0.271 ? ns t suaddr_pfu address setup time -0.245 ? -0.284 ? -0.323 ? ns t haddr_pfu address hold time 0.246 ? 0.285 ? 0.324 ? ns t suwren_pfu write/read enable setup time -0.122 ? -0.145 ? -0.168 ? ns t hwren_pfu write/read enable hold time 0.132 ? 0.156 ? 0.180 ? ns pic timing pio input/output buffer timing t in_pio input buffer delay (lvcmos25) ? 0.613 ? 0.681 ? 0.749 ns t out_pio output buffer delay (lvcmos25) ? 1.115 ? 1.115 ? 1.343 ns iologic input/output timing t sui_pio input register setup time (data before clock) 0.596 ? 0.645 ? 0.694 ? ns t hi_pio input register hold time (data after clock) -0.570 ? -0.614 ? -0.658 ? ns t coo_pio output register clock to output delay ? 0.61 ? 0.66 ? 0.72 ns t suce_pio input register clock enable setup time 0.032 ? 0.037 ? 0.041 ? ns t hce_pio input register clock enable hold time -0.022 ? -0.025 ? -0.028 ? ns t sulsr_pio set/reset setup time 0.184 ? 0.201 ? 0.217 ? ns t hlsr_pio set/reset hold time -0.080 ? -0.086 ? -0.093 ? ns ebr timing t co_ebr clock (read) to output from address or data ? 2.51 ? 2.75 ? 2.99 ns t coo_ebr clock (write) to output from ebr output register ? 0.33 ? 0.36 ? 0.39 ns t sudata_ebr setup data to ebr memory -0.157 ? -0.181 ? -0.205 ? ns t hdata_ebr hold data to ebr memory 0.173 ? 0.195 ? 0.217 ? ns t suaddr_ebr setup address to ebr memory -0.115 ? -0.130 ? -0.145 ? ns t haddr_ebr hold address to ebr memory 0.138 ? 0.155 ? 0.172 ? ns t suwren_ebr setup write/read enable to pfu memory -0.128 ? -0.149 ? -0.170 ? ns 3-29 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet t hwren_ebr hold write/read enable to pfu memory 0.139 ? 0.156 ? 0.173 ? ns t suce_ebr clock enable setup time to ebr output register 0.123 ? 0.134 ? 0.145 ? ns t hce_ebr clock enable hold time to ebr output register -0.081 ? -0.090 ? -0.100 ? ns t rsto_ebr reset to output delay time from ebr output register ? 1.03 ? 1.15 ? 1.26 ns t sube_ebr byte enable set-up time to ebr output register -0.115 ? -0.130 ? -0.145 ? ns t hbe_ebr byte enable hold time to ebr output register 0.138 ? 0.155 ? 0.172 ? ns gpll parameters t rstrec_gpll reset recovery to rising clock 1.00 ? 1.00 ? 1.00 ? ns spll parameters t rstrec_spll reset recovery to rising clock 1.00 ? 1.00 ? 1.00 ? ns dsp block timing 2,3 t sui_dsp input register setup time 0.12 ? 0.13 ? 0.14 ? ns t hi_dsp input register hold time 0.02 ? -0.01 ? -0.03 ? ns t sup_dsp pipeline register setup time 2.18 ? 2.42 ? 2.66 ? ns t thp_dsp pipeline register hold time -0.68 ? -0.77 ? -0.86 ? ns t suo_dsp output register setup time 4.26 ? 4.71 ? 5.16 ? ns t ho_dsp output register hold time -1.25 ? -1.40 ? -1.54 ? ns t coi_dsp input register clock to output time ? 3.92 ? 4.30 ? 4.68 ns t cop_dsp pipeline register clock to output time ? 1.87 ? 1.98 ? 2.08 ns t coo_dsp output register clock to output time ? 0.50 ? 0.52 ? 0.55 ns t suaddsub addsub input register setup time -0.24 ? -0.26 ? -0.28 ? ns t haddsub addsub input register hold time 0.27 ? 0.29 ? 0.32 ? ns 1. internal parameters are characterized but not tested on every device. 2. these parameters apply to latticeecp devices only. 3. dsp block is configured in multiply add/sub 18x18 mode. latticeecp2/m internal sw itching characteristics 1 (continued) over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max. 3-30 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet timing diagrams figure 3-9. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-10. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t co_ebr t co_ebr t co_ebr t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 output is only updated during a read cycle a1 d0 d1 mem(n) data from previous read dia ada wea csa clka doa (regs) t su t h t coo_ebr t coo_ebr 3-31 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-11. write through (sp read/wri te on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access 3-32 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2/m family timing adders 1, 2, 3 over recommended operating conditions buffer type description -7-6-5units input adjusters lvds25 lvds -0.04 -0.02 0.00 ns blvds25 blvds -0.04 -0.09 -0.15 ns mlvds lvds -0.15 -0.15 -0.15 ns rsds rsds -0.15 -0.15 -0.15 ns lvpecl33 lvpecl 0.16 0.15 0.13 ns hstl18_i hstl_18 class i 0.01 -0.01 -0.04 ns hstl18_ii hstl_18 class ii 0.01 -0.01 -0.04 ns hstl18d_i differential hstl 18 class i 0.01 -0.01 -0.04 ns hstl18d_ii differential hstl 18 class ii 0.01 -0.01 -0.04 ns hstl15_i hstl_15 class i 0.01 -0.01 -0.04 ns hstl15d_i differential hstl 15 class i 0.01 -0.01 -0.04 ns sstl33_i sstl_3 class i -0.03 -0.07 -0.10 ns sstl33_ii sstl_3 class ii -0.03 -0.07 -0.10 ns sstl33d_i differential sstl_3 class i -0.03 -0.07 -0.10 ns sstl33d_ii differential sstl_3 class ii -0.03 -0.07 -0.10 ns sstl25_i sstl_2 class i -0.04 -0.07 -0.10 ns sstl25_ii sstl_2 class ii -0.04 -0.07 -0.10 ns sstl25d_i differential sstl_2 class i -0.04 -0.07 -0.10 ns sstl25d_ii differential sstl_2 class ii -0.04 -0.07 -0.10 ns sstl18_i sstl_18 class i -0.01 -0.04 -0.07 ns sstl18_ii sstl_18 class ii -0.01 -0.04 -0.07 ns sstl18d_i differential sstl_18 class i -0.01 -0.04 -0.07 ns sstl18d_ii differential sstl_18 class ii -0.01 -0.04 -0.07 ns lvttl33 lvttl -0.16 -0.16 -0.16 ns lvcmos33 lvcmos 3.3 -0.08 -0.12 -0.16 ns lvcmos25 lvcmos 2.5 0.00 0.00 0.00 ns lvcmos18 lvcmos 1.8 -0.16 -0.17 -0.17 ns lvcmos15 lvcmos 1.5 -0.14 -0.14 -0.14 ns lvcmos12 lvcmos 1.2 -0.04 -0.01 0.01 ns pci33 pci -0.08 -0.12 -0.16 ns output adjusters lvds25e lvds 2.5 e 4 0.25 0.19 0.13 ns lvds25 lvds 2.5 0.10 0.13 0.17 ns blvds25 blvds 2.5 0.00 -0.01 -0.03 ns mlvds mlvds 2.5 4 0.00 -0.01 -0.03 ns rsds rsds 2.5 4 0.25 0.19 0.13 ns lvpecl33 lvpecl 3.3 4 -0.02 -0.04 -0.06 ns hstl18_i hstl_18 class i 8ma drive -0.19 -0.22 -0.25 ns hstl18_ii hstl_18 class ii -0.30 -0.34 -0.37 ns hstl18d_i differential hstl 18 class i 8ma drive -0.19 -0.22 -0.25 ns hstl18d_ii differential hstl 18 class ii -0.30 -0.34 -0.37 ns 3-33 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet hstl15_i hstl_15 class i 4ma drive -0.22 -0.25 -0.27 ns hstl15d_i differential hstl 15 class i 4ma drive -0.22 -0.25 -0.27 ns sstl33_i sstl_3 class i -0.12 -0.15 -0.18 ns sstl33_ii sstl_3 class ii -0.20 -0.23 -0.27 ns sstl33d_i differential sstl_3 class i -0.12 -0.15 -0.18 ns sstl33d_ii differential sstl_3 class ii -0.20 -0.23 -0.27 ns sstl25_i sstl_2 class i 8ma drive -0.16 -0.19 -0.22 ns sstl25_ii sstl_2 class ii 16ma drive -0.19 -0.22 -0.25 ns sstl25d_i differential sstl_2 class i 8ma drive -0.16 -0.19 -0.22 ns sstl25d_ii differential sstl_2 class ii 16ma drive -0.19 -0.22 -0.25 ns sstl18_i sstl_1.8 class i -0.14 -0.17 -0.20 ns sstl18_ii sstl_1.8 class ii 8ma drive -0.20 -0.23 -0.25 ns sstl18d_i differential sstl_1.8 class i -0.14 -0.17 -0.20 ns sstl18d_ii differential sstl_1.8 class ii 8ma drive -0.20 -0.23 -0.25 ns lvttl33_4ma lvttl 4ma drive 0.52 0.60 0.68 ns lvttl33_8ma lvttl 8ma drive 0.06 0.08 0.09 ns lvttl33_12ma lvttl 12ma drive 0.04 0.04 0.05 ns lvttl33_16ma lvttl 16ma drive 0.03 0.02 0.02 ns lvttl33_20ma lvttl 20ma drive -0.09 -0.09 -0.10 ns lvcmos33_4ma lvcmos 3.3 4ma drive, fast slew rate 0.52 0.60 0.68 ns lvcmos33_8ma lvcmos 3.3 8ma drive, fast slew rate 0.06 0.08 0.09 ns lvcmos33_12ma lvcmos 3.3 12ma drive, fast slew rate 0.04 0.04 0.05 ns lvcmos33_16ma lvcmos 3.3 16ma drive, fast slew rate 0.03 0.02 0.02 ns lvcmos33_20ma lvcmos 3.3 20ma drive, fast slew rate -0.09 -0.09 -0.10 ns lvcmos25_4ma lvcmos 2.5 4ma drive, fast slew rate 0.41 0.47 0.53 ns lvcmos25_8ma lvcmos 2.5 8ma drive, fast slew rate 0.01 0.01 0.00 ns lvcmos25_12ma lvcmos 2.5 12ma drive, fast slew rate 0.00 0.00 0.00 ns lvcmos25_16ma lvcmos 2.5 16ma drive, fast slew rate 0.04 0.04 0.04 ns lvcmos25_20ma lvcmos 2.5 20ma drive, fast slew rate -0.09 -0.10 -0.11 ns lvcmos18_4ma lvcmos 1.8 4ma drive, fast slew rate 0.37 0.40 0.43 ns lvcmos18_8ma lvcmos 1.8 8ma drive, fast slew rate 0.10 0.12 0.13 ns lvcmos18_12ma lvcmos 1.8 12ma drive, fast slew rate -0.02 -0.02 -0.02 ns lvcmos18_16ma lvcmos 1.8 16ma drive, fast slew rate -0.02 -0.03 -0.03 ns lvcmos15_4ma lvcmos 1.5 4ma drive, fast slew rate 0.29 0.31 0.32 ns lvcmos15_8ma lvcmos 1.5 8ma drive, fast slew rate 0.05 0.05 0.06 ns lvcmos12_2ma lvcmos 1.2 2ma drive, fast slew rate 0.58 0.69 0.79 ns lvcmos12_6ma lvcmos 1.2 6ma drive, fast slew rate 0.13 0.19 0.26 ns lvcmos33_4ma lvcmos 3.3 4ma drive, slow slew rate 2.17 2.44 2.71 ns lvcmos33_8ma lvcmos 3.3 8ma drive, slow slew rate 2.50 2.67 2.83 ns lvcmos33_12ma lvcmos 3.3 12ma drive, slow slew rate 1.72 1.88 2.05 ns lvcmos33_16ma lvcmos 3.3 16ma drive, slow slew rate 1.64 1.63 1.62 ns lvcmos33_20ma lvcmos 3.3 20ma drive, slow slew rate 1.33 1.36 1.39 ns latticeecp2/m family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7-6-5units 3-34 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet lvcmos25_4ma lvcmos 2.5 4ma drive, slow slew rate 2.18 2.26 2.33 ns lvcmos25_8ma lvcmos 2.5 8ma drive, slow slew rate 2.19 2.35 2.51 ns lvcmos25_12ma lvcmos 2.5 12ma drive, slow slew rate 1.50 1.66 1.82 ns lvcmos25_16ma lvcmos 2.5 16ma drive, slow slew rate 1.60 1.59 1.58 ns lvcmos25_20ma lvcmos 2.5 20ma drive, slow slew rate 1.43 1.39 1.34 ns lvcmos18_4ma lvcmos 1.8 4ma drive, slow slew rate 2.22 2.27 2.32 ns lvcmos18_8ma lvcmos 1.8 8ma drive, slow slew rate 1.93 2.08 2.23 ns lvcmos18_12ma lvcmos 1.8 12ma drive, slow slew rate 1.43 1.51 1.58 ns lvcmos18_16ma lvcmos 1.8 16ma drive, slow slew rate 1.47 1.46 1.45 ns lvcmos15_4ma lvcmos 1.5 4ma drive, slow slew rate 2.32 2.38 2.43 ns lvcmos15_8ma lvcmos 1.5 8ma drive, slow slew rate 1.84 1.98 2.12 ns lvcmos12_2ma lvcmos 1.2 2ma drive, slow slew rate 2.52 2.63 2.74 ns lvcmos12_6ma lvcmos 1.2 6ma drive, slow slew rate 1.69 1.83 1.96 ns pci33 pci33 0.04 0.04 0.04 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing measured with the load s pecified in switching test condition table. 3. all other standards tested accordi ng to the appropriate specifications. 4. these timing adders are measured wi th the recommended resistor values. timing v.a 0.11 latticeecp2/m family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7-6-5units 3-35 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet sysclock gpll timing over recommended operating conditions parameter description conditions min. typ. max. units f in input clock frequency (clki, clkfb) without external capacitor 20 ? 420 mhz with external capacitor 5, 6 2?420mhz f out output clock frequency (clkop, clkos) without external capacitor 20 ? 420 mhz with external capacitor 5 5?50mhz f out2 k-divider output frequency (clkok) without external capacitor 0.156 ? 210 mhz with external capacitor 5 0.039 ? 25 mhz f vco pll vco frequency 640 ? 1280 mhz f pfd phase detector input frequency without external capacitor 20 ? 420 mhz with external capacitor 5, 6 2?50mhz ac characteristics t dt output clock duty cycle d efault duty cycle selected 3 45 50 55 % t ph 4 output phase accuracy ? ? 0.05 ui t opjit 1 output clock period jitter f out ? 100 mhz ? ? 125 ps 50 ? f out < 100 mhz ? 0.025 uipp f out < 50 mhz ? ? 0.04 uipp t sk input clock to output clock skew n/m = integer ? ? 250 ps t w output clock pulse width at 90% or 10% 1 ? ? ns t lock 2 pll lock-in time without external capacitor ? ? 150 s with external capacitor 5 ??500s t pa programmable delay unit 85 130 360 ps t ipjit input clock period jitter ? ? 200 ps t fbkdly external feedback delay ? ? 10 ns t hi input clock high time 90% to 90% 0.5 ? ? ns t lo input clock low time 10% to 10% 0.5 ? ? ns t rst rst pulse width (resetm/resetk) 15 ? ? ns reset signal pulse width (cntrst) without external capacitor 500 ? ? ns with external capacitor 5 20 ? ? s 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference cloc k and no additional i/o pins to ggling. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. relative to clkop. 5. value of external capacitor: 5.6 nf 20%, npo dielectric, ce ramic chip capacitor, 1206 or sm aller package, connected to pllca p pin. 6. f out (max) = f in * 10 for f in < 5mhz. 3-36 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet sysclock spll timing over recommended operating conditions parameter description conditions min. typ. max. units f in input clock frequency (clki, clkfb) without external capacitor 33 ? 420 mhz with external capacitor 5, 6 2 ? 420 mhz f out output clock frequency (clkop, clkos) without external capacitor 33 ? 420 mhz with external capacitor 5 5?50mhz f out2 k-divider output frequency (clkok) without external capacitor 0.258 ? 210 mhz with external capacitor 5 0.039 ? 25 mhz f vco pll vco frequency 640 ? 1280 mhz f pfd phase detector input frequency without external capacitor 33 ? 420 mhz with external capacitor 6 2?50mhz ac characteristics t dt output clock duty cycle default duty cycle selected 3 45 50 55 % t ph 4 output phase accuracy ? ? 0.05 ui t opjit 1 output clock period jitter f out ? 100 mhz ? ? 125 ps 50 ? f out < 100 mhz ? ? 0.025 uipp f out < 50 mhz ? ? 0.04 uipp t sk input clock to output clock skew divider ratio = integer ? ? 250 ps t w output clock pulse width at 90% or 10% 1 ? ? ns t lock 2 pll lock-in time without external capacitor ? ? 150 s with external capacitor 5 ? ? 500 s t ipjit input clock period jitter ? ? 200 ps t fbkdly external feedback delay ? ? 10 ns t hi input clock high time 90% to 90% 0.5 ? ? ns t lo input clock low time 10% to 10% 0.5 ? ? ns t rst rst pulse width (resetm/resetk) 15 ? ? ns reset signal pulse width (cntrst) without external capacitor 500 ? ? ns with external capacitor 5 20 ? ? s 1. jitter sample is taken over 10,000 samples of the primary p ll output with clean reference cl ock and no additional i/o pins to ggling. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. phase accuracy of clkos compared to clkop. 5. value of external capacitor: 5.6 nf 20%, npo dielectric, ce ramic chip capacitor, 1206 or smaller package, connected to pllca p pin. 6. f out (max) = f in * 10 for f in < 5mhz. 3-37 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet dll timing over recommended operating conditions parameter description min. typ. max. units f ref input reference clock frequency (on-chip or off-chip) 100 ? 500 mhz f fb feedback clock frequency (on-chip or off-chip) 100 ? 500 mhz f clkop 1 output clock frequency, clkop 100 ? 500 mhz f clkos 2 output clock frequency, clkos 25 ? 500 mhz t pjit output clock period jitter (clean input) ? 250 ps p-p t cyjit output clock cycle to cycle jitter (clean input) 250 ps p-p t duty output clock duty cycle (at 50% levels, 50% duty cycle input clock, 50% duty cycle circuit turned off, time reference delay mode) 35 65 % t dutytrd output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit ena bled, time reference delay mode) 40 60 % t dutycir output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit ena bled, clock injection removal mode) 40 60 % t skew 3 output clock to clock skew between two outputs with the same phase setting ??100ps t pwh input clock minimum pulse width high (at 80% level) 750 ? ? ps t pwl input clock minimum pulse width low (at 20% level) 750 ? ? ps t r , t f input clock rise and fall time (20% to 80% levels) ? ? 1 ns t instb input clock period jitter ? ? +/-250 ps t lock dll lock time 18,500 ? ? cycles t rswd digital reset minimum pulse width (at 80% level) 3 ? ? ns t pa delay step size 16.5 42 59.4 ps t range1 max. delay setting for single delay block (144 taps) 2.376 6 8.553 ns t range4 max. delay setting for four chained delay blocks 9.504 24 34.214 ns 1. clkop runs at the same frequency as the input clock. 2. clkos minimum frequency is obtained with divide by 4. 3. this is intended to be a ?path-matching? desi gn guideline and is not a m easurable specification. 3-38 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet serdes high-speed data transmitter (latticeecp2m family only) 1, 2 table 3-7. serial output timing and levels table 3-8. channel output jitter - x10 mode symbol description frequency min. typ. max. units v tx-diff-p-p-1 differential swing (1v setting) 1, 2 0.25 to 3.125 gbps 0.79 0.99 1.19 v, p-p v tx-diff-p-p-1.25 differential swing (1.25v setting) 1, 2 0.25 to 3.125 gbps 1.00 1.25 1.50 v, p-p v tx-diff-p-p-1.3 differential swing (1.3v setting) 1, 2 0.25 to 3.125 gbps 1.04 1.30 1.56 v, p-p v tx-diff-p-p-1.35 differential swing (1.35v setting) 1, 2 0.25 to 3.125 gbps 1.08 1.35 1.62 v, p-p v ocm output common mode voltage ? v ccob - 0.75 v ccob - 0.60 v ccob - 0.45 v t tx-r rise time (20% to 80%) ? ? 70 ? ps t tx-f fall time (80% to 20%) ? ? 70 ? ps z tx-oi-se output impedance 50/75/hiz ? k ohms (single-ended) ?? 50/70 hiz ?ohms r tx-rl return loss (with package) ? ? 9 ? db 1. all measurements are with 50 ohm impedance. 2. see tn1124, latticeecp2m serdes/pcs usage guide for actual binary settings. description frequency min. typ. max. units deterministic 3.125 gbps ? 0.08 0.12 ui, p-p random 3.125 gbps ? 0.22 0.38 ui, p-p total 3.125 gbps ? 0.33 0.43 ui, p-p deterministic 2.5 gbps ? 0.08 0.17 ui, p-p random 2.5 gbps ? 0.20 0.25 ui, p-p total 2.5 gbps ? 0.25 0.35 ui, p-p deterministic 1.25 gbps ? 0.03 0.10 ui, p-p random 1.25 gbps ? 0.14 0.19 ui, p-p total 1.25 gbps ? 0.17 0.24 ui, p-p deterministic 250 mbps ? 0.04 0.17 ui, p-p random 250 mbps ? 0.12 0.13 ui, p-p total 250 mbps ? 0.15 0.29 ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, reference clock at x10 mode. 3-39 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet table 3-9. channel output jitter - x20 mode table 3-10. serdes/pcs latency breakdown (parallel clock cycle) description frequency min. typ. max. units deterministic 3.125 gbps ? 0.08 0.12 ui, p-p random 3.125 gbps ? 0.27 0.51 ui, p-p total 3.125 gbps ? 0.35 0.59 ui, p-p deterministic 2.5 gbps ? 0.09 0.19 ui, p-p random 2.5 gbps ? 0.23 0.34 ui, p-p total 2.5 gbps ? 0.29 0.45 ui, p-p deterministic 1.25 gbps ? 0.05 0.11 ui, p-p random 1.25 gbps ? 0.16 0.22 ui, p-p total 1.25 gbps ? 0.20 0.28 ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, reference clock at x20 mode. item description min. average max. fixed bypass units transmit data latency t1 fpga bridge transmit 2 135 1word clk t2 8b10b encoder ? ? ? 2 1 word clk t3 serdes bridge transmit ? ? ? 2 1 word clk t4 3 serializer: 8-bit mode ? ? ? 15 + ? 1?ui + ps serializer: 10-bit mode ? ? ? 18 + ? 1?ui + ps receive data latency r1 3 deserializer: 8-bit mode ? ? ? 10 + ? 2?ui + ps deserializer: 10-bit mode ? ? ? 12 + ? 2?ui + ps r2 serdes bridge receive ? ? ? 2 1 word clk r3 word alignment 3.1 ? 4 ? 0 word clk r4 8b10b decoder ? ? ? 1 1 word clk r5 clock tolerance compensation 7 15 23 1 word clk r6 fpga bridge receive 2 135 1word clk 1. pcs internal parallel clock. this clock rate is the same as rxfullclk. 2. fpga bridge latency varies by the upsample/downsample fifo read/write. the numbers given are for the 8b10b interface. the depth of the downsample/upsample fifo is 4. the earliest read can be done after the write clock cycle (one clock) in downsample fifo. the latest read will be done after the fifo is full (4 + 1 = 5). for the 16b20b interface, the numbers are doubled: min. = 2, max. = 10. this latency depends on the internal fifo flag operation. 3. ? 1 = -245ps, ? 2 = 700ps 3-40 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-12. transmitter and receiver block diagram hdoutpi hdoutni deserializer 1:8/1:10 polarity adjust elastic buffer fifo encoder serdes pcs bypass transmitter receiver recovered clock fpga receive clock fpga receive data transmit data cdr refclk hdinpi hdinni eq polarity adjust up sample fifo serdes bridge fpga bridge serializer 8:1/10:1 wa dec fpga ebrd clock transmit clock tx pll refclk fpga core down sample fifo bypass bypass bypass bypass bypass bypass r1 r2 r3 r4 r5 r6 t1 t2 t3 t4 transmit clock 3-41 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet serdes high speed data receiv er (latticeecp2m family only) table 3-11. serial input data specifications input data jitter tolerance a receiver?s ability to tolerate incoming signal jitter is very dependent on jitte r type. high speed serial interface stan- dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler- ance levels for different jitter types as they relate to specif ic protocols (e.g. fc, etc.). sinusoidal jitter is considered to be a worst case jitter type. table 3-12. receiver total jitter tolerance specification 1 symbol description min. typ. max. units rx-cid s stream of nontransitions 1 ? (cid = consecutive identical digits) @ 10 -12 ber 7 @ 3.125 gbps 20 @ 1.25 gbps bits v rx-diff-s differential input sens itivity 100 ? ? mv, p-p v rx-in input levels 0 ? v ccrx + 0.8 v v rx-cm-dc input common mode range (dc coupled) 0.5 ? 1.2 v v rx-cm-ac input common mode range (ac coupled) 3 0?1.5v t rx-relock cdr re-lock time 2 ? ? 3000 bits z rx-term input termination 50/75 ohm/high z ? 50 ohms rl rx-rl return loss (without package) ? 9 ? db 1. this is the number of bits allowed without a trans ition on the incoming data stream when using dc coupling. 2. this is the typical number of bit times to re-lock to a new phase of frequency within +/- 300 ppm, assuming 8b10b encoded dat a and the cdr is in lock state. when cdr is in un-lock state, or rese t is applied, the total re-lock se ttling time will be approximately 4ms including ana- log settle time, calibration time, and acquisition time. 3. ac coupling is used to interface to lvpecl and lvds. description frequency condition min. typ. max. units deterministic 3.125 gbps 600 mv differential eye ? ? 0.54 ui, p-p random 600 mv differential eye ? ? 0.26 ui, p-p total 600 mv differential eye ? ? 0.80 ui, p-p deterministic 2.5 gbps 600 mv differential eye ? ? 0.61 ui, p-p random 600 mv differential eye ? ? 0.22 ui, p-p total 600 mv differential eye ? ? 0.81 ui, p-p deterministic 1.25 gbps 600 mv differential eye ? ? 0.53 ui, p-p random 600 mv differential eye ? ? 0.22 ui, p-p total 600 mv differential eye ? ? 0.80 ui, p-p deterministic 250 mbps 2 600 mv differential eye ? ? 0.42 ui, p-p random 600 mv differential eye ? ? 0.10 ui, p-p total 600 mv differential eye ? ? 0.60 ui, p-p 1. values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/o s around serdes pins quiet, voltages are nominal, room temperature. 2. jitter specification is limited by measurem ent equipment capability. 3-42 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet table 3-13. periodic receiver jitter tolerance specification 1 description frequency condition min. typ. max. units periodic 3.125 gbps 600 mv differential eye ? ? 0.20 ui, p-p 2.5 gbps 600 mv differential eye ? ? 0.22 ui, p-p 1.25 gbps 600 mv differential eye ? ? 0.20 ui, p-p 250 mbps 2 600 mv differential eye ? ? 0.08 ui, p-p 1. values are measured with prbs 2 7 -1, all channels operating. 2. jitter specification is limited by measurem ent equipment capability. 3-43 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet serdes external reference clock (latticeecp2m family only) the external reference clock selection and its interface are a critical part of system applications for this product. table 3-14 specifies reference clock requirements, over the full range of operating conditions. figure 3-13. jitter transfer serdes power-down/power-up specification table 3-15. power-down and power-up specification table 3-14. external reference clock specification (refclkp/refclkn) symbol description min. typ. max. units f ref frequency range 25 ? 320 mhz f ref-ppm frequency tolerance -300 ? 300 ppm v ref-in-se input swing, single-ended clock 1 100 ? 1200 mv, p-p v ref-in input levels 0 ? v ccp + 0.8 v v ref-cm-dc input common mode range (dc coupled) 0.5 ? 1.2 v v ref-cm-ac input common mode range (ac coupled) 2 0? 1.5 v d ref duty cycle 3 40 ? 60 % t ref-r rise time (20% to 80%) 500 1000 ps t ref-f fall time (80% to 20%) 500 1000 ps z ref-in-term input termination 50/2k ohms c ref-in-cap input capacitance 4 ?? 1.5 pf 1. the signal swing for a single-ended input clock must be as lar ge as the p-p differential swing of a differential input clock to get the same gain at the input receiver. lower swings for the cl ock may be possible, but will tend to increase jitter. 2. when ac coupled, the input common mode range is determined by: ? (min input level) + (peak-to-peak input swing)/2 ? (input common mode voltage) ? (max input level) - (p eak-to-peak input swing)/2 3. measured at 50% amplitude. 4. input capacitance of 1.5pf is total capa citance, including both device and package. symbol description max. units t pwrdn power-down time after all power down register bits set to ?0? 10 ? s t pwrup power-up time after all power down register bits set to ?1? 100 ? s frequency (mhz) db note: this graph is for a nominal device. -25.00 -20.00 -15.00 -10.00 -5.00 0.00 5.00 0.1 1 10 100 jitter t. gain@25?,1.20v, pj=100ps 3-44 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet pci express electrical an d timing characteristics ac and dc characteristics table 3-16. transmit 1, 2 table 3-17. receive symbol description test conditions min typ max units ui unit interval 399.88 400 400.12 ps v tx-diff_p-p differential peak-to-peak output voltage 0.8 1.0 1.2 v v tx-de-ratio de-emphasis differential output voltage ratio 0 -3.5 -7.96 db v tx-cm-ac_p rms ac peak common-mode out- put voltage ?20?mv v tx-cm-dc-line-delta maximum common mode voltage delta between n and p channels ??25mv v tx-dc-cm tx dc common mode voltage 0 ? v ccob + 5% v i tx-short output short circuit current v tx-d+ =0.0v v tx-d- =0.0v ??90ma z tx-diff-dc differential output impedance 80 100 120 ohms t tx-rise tx output rise time 20 to 80% 0.125 ? ? ui t tx-fall tx output fall time 20 to 80% 0.125 ? ? ui l tx-skew lane-to-lane static output skew for all lanes in port/link ??1.3ns t tx-eye transmitter eye width 0.75 ? ? ui t tx-eye-median-to-max-jitter 3 ? ? 0.125 ui c tx ac coupling capacitor 75 ? 200 nf 1. values are measured at 2.5 gbps. 2. compliant to pci express v1.1. 3. measured at 60ps with plug-in board and jitter due to socket removed. symbol description test conditions min. typ. max. units ui unit interval 399.88 400 400.12 ps v rx-diff_p-p differential peak-to-peak input voltage 0.175 ? ? v v rx-idle-det-diff_p-p idle detect threshold voltage 65 ? 175 mv z rx-diff-dc dc differential input impedance 80 100 120 ohms z rx-dc dc input impedance 40 50 60 ohms z rx-high-imp-dc 1 power-down dc input impedance 200k ? ? ohms t rx-eye receiver eye width 0.4 ? ? ui t rx-eye-median-to-max-jitter ??0.3ui notes: 1. measured with external ac-coupling on the receiver 2. values are measured at 2.5 gbps 3-45 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet table 3-18. reference clock symbol description test conditions min. typ. max. units f refclk reference clock frequency ? 100 ? mhz v cm input common mode voltage ? 0.65 ? v t r /t f clock input rise/fall time ? ? 1.0 ns v sw differential input voltage swing 0.6 ? 1.6 v dc refclk input clock duty cycle 40 50 60 % ppm reference clock tolerance -300 ? +300 ppm 3-46 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet latticeecp2/m sysconfig port timing specifications over recommended operating conditions parameter description min. max. units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 7 ? ns t hcbdi byte d[0:7] hold time to cclk 1 ? ns t codo cclk to dout in flowthrough mode ? 12 ns t sucs csn[0:1] setup time to cclk 7 ? ns t hcs csn[0:1] hold time to cclk 1 ? ns t suwd write signal setup time to cclk 7 ? ns t hwd write signal hold time to cclk 1 ? ns t dcb cclk to busy delay time ? 12 ns t cord cclk to out for read data ? 12 ns sysconfig byte slave clocking t bsch byte slave cclk minimum high pulse 6 ? ns t bscl byte slave cclk minimum low pulse 9 ? ns t bscyc byte slave cclk cycle time 15 ? ns sysconfig serial (bit) data flow t suscdi di setup time to cclk slave mode 7 ? ns t hscdi di hold time to cclk slave mode 1 ? ns t codo cclk to dout in flowthrough mode ? 12 ns sysconfig serial slave clocking t ssch serial slave cclk minimum high pulse 6 ? ns t sscl serial slave cclk minimum low pulse 6 ? ns sysconfig por, initialization and wake-up t icfg minimum vcc to initn high ? 28 ms t vmc time from t icfg to valid master cclk ? 2 us t prgmrj programn pin pulse rejection ? 8 ns t prgm programn low time to start con? guration 25 ? ns t dinit programn high to initn high delay ? 1.5 ms t dppinit delay time from programn low to initn low ? 37 ns t dppdone delay time from programn low to done low ? 37 ns t iodiss user i/o disable from programn low ? 35 ns t ioenss user i/o enabled time from cclk edge during wake-up sequence ? 25 ns t mwc additional wake master clock signals after done pin high 120 ? cycles sysconfig spi port 1 t cfgx initn high to cclk low ? 1 s t csspi initn high to csspin low ? 2 us t cscclk cclk low before csspin low 0 ? ns t socdo cclk low to output valid ? 15 ns t soe csspin[0:1] active setup time 300 ? ns t cspid csspin[0:1] low to first cclk edge setup time 300+3cyc 600+6cyc ns f maxspi max. cclk frequency - spi flash read opcode (0x03) ? (spifastn = 1) ? 20mhz max. cclk frequency - spi flash fast read opcode (0x0b) ? (spifastn = 0) ?50mhz 3-47 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-14. sysconfig parallel port read cycle t suspi sospi data setup time before cclk 7 ? ns t hspi sospi data hold time after cclk 2 ? ns 1. for sed (soft error detect), the sedclkin operating frequency mu st be at least 20mhz. sedclkin is derived from master clock f re- quency that has a +/-30% variation.. parameter min. max. units master clock frequency selected value - 30% selected value + 30% mhz duty cycle 40 60 % latticeecp2/m sysconfig port timi ng specifications (continued) over recommended operating conditions parameter description min. max. units cclk cs1n csn writen busy d[0:7] t sucs t hcs t suwd t cord t dcb t hwd t bscyc t bsch t bscl byte 0 byte 1 byte 2 byte n* *n = last byte of read cycle. 3-48 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-15. sysconfig parallel port write cycle figure 3-16. sysconfig slave serial port timing figure 3-17. power-on-reset (por) timing cclk 1 cs1n csn writen busy d[0:7] t sucs t hcs t suwd t hcbdi t dcb t hwd t bscyc t bsch t bscl t sucbdi byte 0 byte 1 byte 2 byte n 1. in master parallel mode the fpga provides cclk. in slave parallel mode the external device provides cclk. cclk (input) din dout t suscdi t hscdi t codo t sscl t ssch cclk 2 done v cc /v ccaux 1 cfg[2:0] 3 t icfg valid initn t vmc t sucfg t hcfg 1. time taken from v cc or v ccaux , whichever is the last to reach its v min . 2. device is in a master mode. 3. the cfg pins are normally static (hard wired). 3-49 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-18. configuration from programn timing figure 3-19. wake-up timing cclk done programn cfg[2:0] t prgmrj valid initn t sucfg t hcfg 1. the cfg pins are normally static (hard wired) t dppinit t dinitd t dinit t iodiss user i/o cclk done programn user i/o initn t ioenss wake-up t mwc 3-50 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet figure 3-20. spi/spim configuration waveforms vcc t icfg t cscclk t soe t socdo t cspid t csspi t cfgx t dinit t dppinit programn done initn csspi[0:1]n cclk sispi/busy d7/spid0 d7 d5 d4 d3 d2 d1 d0 d6 xxx valid bitstream clock 127 clock 128 0 1 2 3 4 5 6 7 0 t prgm capture cfgx capture opcode dppdone 3-51 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet jtag port timing specifications over recommended operating conditions figure 3-21. jtag port timing waveforms symbol parameter min max units f max tck clock frequency ? 25 mhz t btcp tck [bscan] clock pulse width 40 ? ns t btcph tck [bscan] clock pulse width high 20 ? ns t btcpl tck [bscan] clock pulse width low 20 ? ns t bts tck [bscan] setup time 8 ? ns t bth tck [bscan] hold time 10 ? ns t btrf tck [bscan] rise/fall time 50 ? mv/ns t btco tap controller falling edge of clock to valid output ? 10 ns t btcodis tap controller falling edge of clock to valid disable ? 10 ns t btcoen tap controller falling edge of clock to valid enable ? 10 ns t btcrs bscan test capture register setup time 8 ? ns t btcrh bscan test capture register hold time 25 ? ns t butco bscan test update register, falling edge of clock to valid output ? 25 ns t btuodis bscan test update register, falling edge of clock to valid disable ? 25 ns t btupoen bscan test update register, falling edge of clock to valid enable ? 25 ns timing v.a 0.11 tms tdi tck tdo data to be captured from i/o data to be driven out to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data captured t btcph t btcpl t btcoen t btcrs t btupoen t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp 3-52 dc and switching characteristics lattice semiconductor latticeecp2 /m family data sheet switching test conditions figure 3-22 shows the output test load that is used for ac testing. the speci? c values for resistance, capacitance, voltage, and other test conditions are shown in table 3-19. figure 3-22. output test load, lvttl and lvcmos standards table 3-19. test fixture required components, non-terminated interfaces test condition r 1 r 2 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) ?? 0pf lvcmos 3.3 = 1.5v ? lvcmos 2.5 = v ccio /2 ? lvcmos 1.8 = v ccio /2 ? lvcmos 1.5 = v ccio /2 ? lvcmos 1.2 = v ccio /2 ? lvcmos 2.5 i/o (z -> h) ? 1m? v ccio /2 ? lvcmos 2.5 i/o (z -> l) 1m? ? v ccio /2 v ccio lvcmos 2.5 i/o (h -> z) ? 100 v oh - 0.10 ? lvcmos 2.5 i/o (l -> z) 100 ? v ol + 0.10 v ccio note: output test conditions for all other inte rfaces are determined by the respective standards. dut v t r1 r2 cl* test poi nt *cl includes test fixture and probe capacitance www.latticesemi.com 4-1 ds1006 pinout information_02.1 march 2010 data sheet ds1006 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. signal descriptions signal name i/o description general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or b (bottom), only need to spec- ify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pins, when not used as special purpose pins, can be programmed as i/os for user logic. during configuration the user-programmable i/os are tri-stated with an internal pull-up resistor enabl ed. if any pin is not used (or not bonded to a package pin), it is also tri-stat ed with an internal pull-up resistor enabled after configuration. gsrn i global reset signal (activ e low). any i/o pin can be gsrn. nc ? no connect. gnd ? ground. dedicated pins. v cc ? power supply pins for core logic. dedicated pins. v ccaux ? auxiliary power supply pin. this dedicated pin powers all the differential and referenced input buffers. v cciox ? dedicated power supply pins for i/o bank x. v ccpll ? pll supply pins. should be tied to v cc even when the corresponding pll is unused. v ref1_x , v ref2_x ? reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. when not used, they may be used as i/o pins. xres 4 ? 10k ohm +/-1% resistor must be connected between this pad and ground. pllcap 4 ? external capacitor connection for pll. pll, dll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_v ccpll ? power supply pin for pll: lum, llm, rum, rlm, num = row from center. [loc][num]_gpll[t, c]_in_a i general purpose pll (gpll) input pads : lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_gpll[t, c]_fb_a i optional feedback gpll input pads: lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_spll[t, c]_in_a 5 i secondary pll (spll) input pads: lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_spll[t, c]_fb_a 5 i optional feedback (spll) input pads: lu m, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_dll[t, c]_in_a i dll input pads: lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_dll[t, c]_fb_a i optional feedback (dll) input pads: lum, llm, rum, rlm, num = row from center, t = true and c = complement, index a,b,c...at each side. pclk[t, c]_[n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1,2,3 within bank. latticeecp2/m family data sheet pinout information 4-2 pinout information lattice semiconductor latticeecp2 /m family data sheet [loc]dqs[num] i/o dq input/output pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. [loc]dq[num] i/o dq input/output pads: t (top), r (right ), b (bottom), l (left), dq, associated dqs number. test and programmin g (dedicated pins) tms i test mode select input, used to control the 1149.1 state machine. pull-up is enabled during configuration. tck i test clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. tdi i test data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for configuration by sending appropriate command. (note: once a co nfiguration port is selected it is locked. another configuration port cannot be selected until the power-up sequence). pull-up is enabled during configuration. tdo o output pin. test data out pin used to shift data out of a device using 1149.1. vccj ? power supply pin for jtag test access port. configuration pads (used during sysconfig) cfg[2:0] i mode pins used to specify configuratio n mode values latched on rising edge of initn. during configuration, a pu ll-up is enabled. these are dedicated pins. initn i/o open drain pin. indicates the fpga is re ady to be configured. during config- uration, a pull-up is enabled. it is a dedicated pin. programn i initiates configuration sequence when asserted low. this pin always has an active pull-up. this is a dedicated pin. done i/o open drain pin. indicates that the c onfiguration sequence is complete, and the startup sequence is in progress. this is a dedicated pin. cclk i/o configuration clock for configuring an fpga in sysconfig mode. busy/sispi i/o read control command in spi or spim mode. csn i sysconfig chip sele ct (active low). during conf iguration, a pull-up is enabled. cs1n i sysconfig chip sele ct (active low). during conf iguration, a pull-up is enabled. writen i write data on parallel port (active low). d[0]/spifastn i/o sysconfig port data i/o for parallel mode. sysconfig port data i/o for spi or spim. when using the spi or spim mode, this pin should either be tied high or low, must not be left floating. d[1:6] i/o sysconfig port data i/o for parallel d[7]/spid0 i/o sysconfi g port data i/o for parallel, spi, spim dout/cson o output for serial config uration data (ris ing edge of cclk) when using sys- config port. di/csspi0n i/o input for serial configuration data (clocked with cclk) when using syscon- fig port. during configuration, a pull-up is enabled. output when used in spi/ spim modes. dedicated serdes signals 1, 2, 3 [loc]_sq_vccaux33 ? termination resistor switching power (3.3v). this pin must be tied to 3.3v even if the quad is unused. [loc]_sq_refclkn i negative reference clock input [loc]_sq_refclkp i positive reference clock input [loc]_sq_vccp ? pll and reference clock buffer power (1.2v). this pin must be tied to 1.2v even if the quad is unused. signal descriptions (cont.) signal name i/o description 4-3 pinout information lattice semiconductor latticeecp2 /m family data sheet [loc]_sq_vccibm ? input buffer power supply, channel m (1.2v/1.5v). this pin should be left float- ing if the channel is unused. [loc]_sq_vccobm ? output buffer power supply, channel m (1.2v/1.5v). this pin should be left floating if the channel is unused. [loc]_sq_hdoutnm o high-speed output, negative channel m [loc]_sq_hdoutpm o high-speed output, positive channel m [loc]_sq_hdinnm i high-speed input, negative channel m [loc]_sq_hdinpm i high-speed input, positive channel m [loc]_sq_vcctxm 4 ? transmitter power supply, channel m (1.2v). this pin must be tied to 1.2v even if the channel is unused. [loc]_sq_vccrxm 4 ? receiver power supply, channel m (1.2v). this pin must be tied to 1.2v even if the channel is unused. 1. these signals are relevant for latticeecp2m family. 2. m defines the associ ated channel in the quad. 3. these signals are defined in quads [loc] indicates the corner serdes quad is located: ulc (upper left), urc (upper right), ll c (lower left), lrc (lower right). 4. when placing switching i/os around these cr itical pins that are designed to supply t he device with the proper reference or su pply voltage, care must be given. for more information, refer to tn1159, latticeecp2/m pin assignment recommendations . 5. there may be splls that do not have dedicated i/os. signal descriptions (cont.) signal name i/o description 4-4 pinout information lattice semiconductor latticeecp2 /m family data sheet pics and ddr data (dq) pins associ ated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic ddr strobe (dqs) and data (dq) pins for left and right edges of the device p[edge] [n-4] adq bdq p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a[edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq p[edge] [n+3] adq bdq for bottom edge of the device p[edge] [n-4] adq bdq p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a [edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq p[edge] [n+3] adq bdq p[edge] [n+4] adq bdq notes: 1. ?n? is a row pic number. 2. the ddr interface is designed for memori es that support one dqs strobe up to 15 bits of data for the left and right edges and up to 17 bits of data for the bottom edge. in some packages, all the potential ddr data (dq) pins may not be available. pic numbering definitions are provided in the ?signal names? column of the signal descriptions table. 4-5 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 pin information su mmary, lfe2-6 and lfe2-12 pin type lfe2-6 lfe2-12 144 tqfp 256 fpbga 144 tqfp 208 pqfp 256 fpbga 484 fpbga single ended user i/o 90 190 93 131 193 297 differential pair user i/o 43 95 45 62 96 148 configuration tap pins 555555 muxed pins 14 14 14 14 14 14 dedicated pins (non tap)777777 non configuration muxed pins 34 54 33 40 54 57 dedicated pins 333333 vcc 10 7 10 14 7 16 vccaux 4448416 vccpll 000000 vccio bank0 121224 bank1 121224 bank2 121224 bank3 121224 bank4 121224 bank5 121224 bank6 121224 bank7 121224 bank8 111212 gnd, gnd0 to gnd7 12 20 12 22 20 60 nc 4310044 single ended/ differential i/o pairs per bank (including ? emulated with resistors) bank0 8/4 18/6 8/4 18/9 18/9 50/25 bank1 17/8 34/17 18/9 18/9 34/17 46/23 bank2 4/2 20/10 4/2 11/5 20/10 24/12 bank3 8/4 12/6 8/4 11/5 12/6 16/8 bank4 18/9 32/16 18/9 19/9 32/16 46/23 bank5 8/4 14/7 10/5 18/9 17/8 46/23 bank6 9/4 26/13 9/4 18/8 26/13 32/16 bank7 12/6 20/10 12/6 12/6 20/10 23/11 bank8 6/2 14/7 6/2 6/2 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 000000 bank1 (top edge) 000000 bank2 (right edge) 151456 bank3 (right edge) 333334 bank4 (bottom edge) 0 00000 bank5 (bottom edge) 0 00000 bank6 (left edge) 272678 bank7 (left edge) 555555 bank8 (right edge) 000000 4-6 pinout information lattice semiconductor latticeecp2 /m family data sheet available ddr-interfaces per i/o bank 1 bank0 000000 bank1 000000 bank2 010011 bank3 000000 bank4 020023 bank5 010013 bank6 010011 bank7 010011 bank8 000000 pci capable i/os per bank bank0 000000 bank1 000000 bank2 000000 bank3 000000 bank4 183218193246 bank5 8 14 10 18 17 46 bank6 000000 bank7 000000 bank8 000000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available dd r interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin inform ation summary, lfe2-6 and lfe2-12 (cont.) pin type lfe2-6 lfe2-12 144 tqfp 256 fpbga 144 tqfp 208 pqfp 256 fpbga 484 fpbga 4-7 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 pin information su mmary, lfe2-20 and lfe2-35 pin type lfe2-20 lfe2-35 208 pqfp 256 fpbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga single ended user i/o 131 193 331 402 331 450 differential pair user i/o 62 96 165 200 165 224 configuration tap pins 555555 muxed pins 14 14 14 14 14 14 dedicated pins (non tap)777777 non configuration muxed pins 42 54 60 64 60 68 dedicated pins 333333 vcc 14 7 18 24 16 22 vccaux 8 4 16 16 16 16 vccpll 000022 vccio bank0 224545 bank1 224545 bank2 224545 bank3 224545 bank4 224545 bank5 224545 bank6 224545 bank7 224545 bank8 212222 gnd, gnd0 to gnd7 22 20 60 72 60 72 nc 0 1 81018102 single ended/ differential i/o pairs per bank (including ? emulated with resistors) bank0 18/9 18/9 50/ 25 67/33 50/25 67/33 bank1 18/9 34/17 46/ 23 52/26 46/23 52/26 bank2 11/5 20/10 34/ 17 36/18 34/17 48/24 bank3 11/5 12/6 22/ 11 32/16 22/11 42/21 bank4 19/9 32/16 46/ 23 50/25 46/23 54/27 bank5 18/9 17/8 46/ 23 68/34 46/23 68/34 bank6 18/8 26/13 40/ 20 48/24 40/20 58/29 bank7 12/6 20/10 33/ 16 35/17 33/16 47/23 bank8 6/2 14/7 14 /7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 000000 bank1 (top edge) 000000 bank2 (right edge) 4599912 bank3 (right edge) 335859 bank4 (bottom edge) 0 00000 bank5 (bottom edge) 0 00000 bank6 (left edge) 6 7 10 12 10 13 bank7 (left edge) 5588811 bank8 (right edge) 000000 4-8 pinout information lattice semiconductor latticeecp2 /m family data sheet available ddr-interfaces per i/o bank 1 bank0 000000 bank1 000000 bank2 012223 bank3 000202 bank4 023333 bank5 013434 bank6 012313 bank7 012223 bank8 000000 pci capable i/os per bank bank0 000000 bank1 000000 bank2 000000 bank3 000000 bank4 193246504654 bank5 181746684668 bank6 000000 bank7 000000 bank8 000000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available dd r interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin inform ation summary, lfe2-20 and lfe2-35 (cont.) pin type lfe2-20 lfe2-35 208 pqfp 256 fpbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga 4-9 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 pin information su mmary, lfe2-50 and lfe2-70 pin type lfe2-50 lfe2-70 484 fpbga 672 fpbga 672 fpbga 900 fpbga single ended user i/o 339 500 500 583 differential pair user i/o 169 249 249 290 configuration tap pins 5 5 5 5 muxed pins 14 14 14 14 dedicated pins (non tap) 7 7 7 7 non configuration muxed pins 68 79 79 89 dedicated pins 3 3 3 3 vcc 16202026 vccaux 16 16 16 17 vccpll 4 4 2 4 vccio bank0 4556 bank1 4556 bank2 4556 bank3 4556 bank4 4556 bank5 4556 bank6 4556 bank7 4556 bank8 2222 gnd, gnd0 to gnd7 60 72 72 104 nc 0 3 5 101 single ended/ differential i/o pairs per bank (including ? emulated with resistors) bank0 50/25 67/33 67/33 84/42 bank1 46/23 66/33 66/33 76/38 bank2 38/19 56/28 56/28 74/37 bank3 22/11 48/24 48/24 48/24 bank4 46/23 62/31 62/31 72/35 bank5 46/23 68/34 68/34 80/40 bank6 40/20 64/32 64/32 64/32 bank7 37/18 55/27 55/27 71/35 bank8 14/7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 0 0 0 0 bank1 (top edge) 0 0 0 0 bank2 (right edge) 9 13 13 18 bank3 (right edge) 5 12 12 12 bank4 (bottom edge) 0 0 0 0 bank5 (bottom edge) 0 0 0 0 bank6 (left edge) 10 16 16 16 bank7 (left edge) 8 12 12 16 bank8 (right edge) 0 0 0 0 4-10 pinout information lattice semiconductor latticeecp2 /m family data sheet available ddr-interfaces per i/o bank 1 bank0 0000 bank1 0000 bank2 2334 bank3 0333 bank4 3444 bank5 3445 bank6 1444 bank7 2334 bank8 0000 pci capable i/os per bank bank0 0000 bank1 0000 bank2 0000 bank3 0000 bank4 46626272 bank5 46686880 bank6 0000 bank7 0000 bank8 0000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available dd r interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin inform ation summary, lfe2-50 and lfe2-70 (cont.) pin type lfe2-50 lfe2-70 484 fpbga 672 fpbga 672 fpbga 900 fpbga 4-11 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m pin information summary, lfe2m20 and lfe2m35 pin type lfe2m20 lfe2m35 256 fpbga 484 fpbga 256 fp bga 484 fpbga 672 fpbga single ended user i/o 140 304 140 303 410 differential pair user i/o 70 152 70 151 199 configuration tap pins 55555 muxed pins 14 14 14 14 14 dedicated pins (non tap)77777 non configuration muxed pins 64 84 60 84 89 dedicated pins 33333 vcc 6 16 6 16 29 vccaux 484817 vccpll 14148 vccio bank0 14145 bank1 13134 bank2 24245 bank3 24245 bank4 24244 bank5 24245 bank6 24245 bank7 24245 bank8 12122 gnd, gnd0 to gnd7 22 57 22 57 80 nc 17 11 17 12 37 single ended/ differential i/o pairs per bank (including emulated with resistors) bank0 0/0 36/18 0/0 36/18 63/31 bank1 0/0 18/9 0/0 18/9 18/9 bank2 14/7 30/15 14/7 30/15 50/25 bank3 16/8 36/18 16/8 36/18 43/21 bank4 32/16 62/31 32/16 62/31 50/21 bank5 20/10 28/14 20/10 28/14 60/30 bank6 16/8 40/20 16/8 39/19 52/25 bank7 28/14 40/20 28/14 40/20 60/30 bank8 14/7 14/7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 00000 bank1 (top edge) 00000 bank2 (right edge) 373712 bank3 (right edge) 494911 bank4 (bottom edge) 00000 bank5 (bottom edge) 00000 bank6 (left edge) 4 10 4 10 14 bank7 (left edge) 7 10 7 10 15 bank8 (right edge) 00000 4-12 pinout information lattice semiconductor latticeecp2 /m family data sheet available ddr-interfaces per i/o bank 1 bank0 00000 bank1 00000 bank2 01013 bank3 01012 bank4 24243 bank5 12123 bank6 03012 bank7 12123 bank8 00000 pci capable i/os per bank bank0 00000 bank1 00000 bank2 00000 bank3 00000 bank4 3262326250 bank5 2028202860 bank6 1640163952 bank7 2840284060 bank8 00000 1. minimum requirement to implement a full y functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2m pin information summa ry, lfe2m20 and lfe2m35 (cont.) pin type lfe2m20 lfe2m35 256 fpbga 484 fpbga 256 fp bga 484 fpbga 672 fpbga 4-13 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m pin information su mmary, lfe2m50, lfe2m70 and lfe2m100 pin type lfe2m50 lfe2m70 lfe2m100 484 fpbga 672 fpbga 900 fpbga 900 fpbga 1152 fpbga 900 fpbga 1152 fpbga single ended user i/o 270 372 410 416 436 416 520 differential pair user i/o 135 185 205 208 218 207 260 configuration tap pins 5555 5 5 5 muxed pins 14 14 14 14 14 14 14 dedicated pins (non tap) 7777 7 7 7 non configuration muxed pins 69 72 72 75 76 74 78 dedicated pins 3333 3 3 3 vcc 16206244 44 44 44 vccaux 8 26 18 16 12 16 12 vccpll 4844 4 4 4 vccio bank0 4566 7 6 7 bank1 3466 7 6 7 bank2 4599 9 9 9 bank3 4599 9 9 9 bank4 4466 7 6 7 bank5 4566 7 6 7 bank6 4599 9 9 9 bank7 4599 9 9 9 bank8 2222 2 2 2 gnd, gnd0 to gnd7 57 80 122 122 134 122 134 nc 31 35 121 63 283 63 199 single ended/ differential i/o pairs per bank (includ- ing emulated with resis- tors) bank0 36/18 63/31 56/28 34/17 46/23 34/17 54/27 bank1 18/9 18/9 36/18 42/21 34/17 42/21 44/22 bank2 30/15 50/25 54/27 70/35 72/36 70/35 80/40 bank3 36/18 43/21 44/22 60/30 64/32 60/30 80/40 bank4 42/21 24/12 38/19 38/19 40/20 38/19 44/22 bank5 28/14 60/30 58/29 40/20 40/20 40/20 46/23 bank6 40/20 54/27 60/30 62/31 66/33 62/31 82/41 bank7 40/20 60/30 64/32 70/35 74/37 70/35 90/45 bank8 0/0 0/0 0/0 0/0 0/0 0/0 0/0 true lvds i/o pairs per bank bank0 (top edge) 0000 0 0 0 bank1 (top edge) 0000 0 0 0 bank2 (right edge) 7 12 13 17 18 17 20 bank3 (right edge) 9 11 11 15 16 15 20 bank4 (bottom edge) 0000 0 0 0 bank5 (bottom edge) 0000 0 0 0 bank6 (left edge) 10 14 15 15 16 15 20 bank7 (left edge) 10 15 17 17 18 17 22 bank8 (right edge) 0000 0 0 0 4-14 pinout information lattice semiconductor latticeecp2 /m family data sheet available ddr-interfaces per i/o bank 1 bank0 0000 0 0 0 bank1 0000 0 0 0 bank2 2224 4 4 4 bank3 2113 4 3 5 bank4 3133 3 3 3 bank5 2332 3 2 3 bank6 1223 4 3 5 bank7 3334 4 4 5 bank8 0000 0 0 0 pci capable i/os per bank bank0 0000 0 0 0 bank1 0000 0 0 0 bank2 000072080 bank3 000064080 bank4 50244848 40 48 44 bank5 60605040 40 40 46 bank6 52546062 66 62 82 bank7 60606870 74 70 90 bank8 0000 0 0 0 1. minimum requirement to implement a full y functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2m pin information summary, lfe2m50, lfe2m70 and lfe2m100 (cont.) pin type lfe2m50 lfe2m70 lfe2m100 484 fpbga 672 fpbga 900 fpbga 900 fpbga 1152 fpbga 900 fpbga 1152 fpbga 4-15 pinout information lattice semiconductor latticeecp2 /m family data sheet available device resources by package, latticeecp2 available device resources by package, latticeecp2m resource device 256 fpbga 484 fpbga 672 fpbga 900 fpbga pll/dll ecp2-6 4 ? ? ? ecp2-12 4 4 ? ? ecp2-20 4 4 4 ? ecp2-35 ? 4 4 ? ecp2-50 ? 6 6 ? ecp2-70 ? ? 8 8 resource device 256 fpbga 484 fpbg a 672 fpbga 900 fpbga 1152 fpbga pll/dll ecp2m201010??? ecp2m35101010? ? ecp2m50 ? 10 10 10 ? ecp2m70 ? ? ? 10 10 ecp2m100 ? ? ? 10 10 4-16 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 power supply and nc signals 144 tqfp 3 208 pqfp 3 256 fpbga 4 484 fpbga 4 vcc 16, 22, 29, 48, 54, 83, 94, 102, 128, 135 12, 19, 28, 40, 74, 80, 97, 116, 129, 140, 146, 171, 188, 198 lfe2-6: g7, g9, g10, h7, j10, k10, k8 lfe2-12/lfe2-20: g7, g9, g10, h7, j10, k10, k8 lfe2-12/lfe2-20: n6, n18, j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 lfe2-35/lfe2-50: j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 vccio0 139 195, 206 c5, e7 g10, g9, h8, h9 vccio1 117 162, 170 c12, e10 g11, g12, g13, g14 vccio2 106 143, 148 e14, g12 h14, h15, j15, k16 vccio3 89 123, 135 k12, m14 l16, m16, n16, p16 vccio4 64 93, 100 m10, p12 r14, t12, t13, t14 vccio5 42 55, 63 m7, p5 r9, t10, t11, t9 vccio6 31 38, 44 k5, m3 n7, p7, p8, r8 vccio7 9 10, 14 e3, g5 j8, k7, l7, m7 vccio8 85 113, 118 t15 p15, r15 vccj 35 51 k7 t8 vccaux 6, 39, 90, 142 7, 30, 70, 86, 125, 151, 174, 190 g8, h10, j7, k9 g5, k5, r5, v7, v11, v8, v13, v15, m17, p17, e17, g18, d11, f13, c5, e6 vccpll none none none lfe2-12/lfe2-20: none lfe2-35: n6, n18 lfe2-50: n6, n18, k6, j16 gnd 1 11, 21, 30, 47, 51, 61, 81, 95, 105, 120, 133, 138 5, 13, 17, 25, 32, 42, 60, 68, 77, 81, 89, 102, 115, 122, 139, 145, 159, 169, 175, 184, 192, 201 a1, a16, b12, b5, c8, e15, e2, h14, h8, h9, j3, j8, j9, m15, m2, p9, r12, r5, t1, t16 a22, aa19, aa4, ab1, ab22, b19, b4, c14, c9, d2, d21, f17, f6, h10, h11, h12, h13, j14, j20, j3, j9, k10, k11, k12, k13, k15, k8, l10, l11, l12, l 13, l15, l8, m10, m11, m12, m13, m15, m8, n10, n11, n12, n13, n15, n8, p14, p20, p3, p9, r10, r11, r12, r13, u17, u6, w2, w21, y14, y9, a1 nc 2 lfe2-6: 45, 46, 124, 127 lfe2-12: 127 none lfe2-6: k6, r3, p4 lfe2-12/lfe2-20: none lfe2-12: e3, f3, f1, h4, f2, h5, g1, g3, g2, g4, k6, n1, m2, n2, m1, n3, n5, n4, p5, n19, m19, j22, l22, h22, k22, j16, d22, f21, e21, e22, h19, g20, g19, f20, c21, c22, h6, j6, h3, h2, h17, h16, h20, h18 lfe2-20/lfe2-35: k6, j16, h6, j6, h3, h2, h17, h16, h20, h18 lfe2-50: none 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less tha n the actual number of gnd logic connec tions from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. pin orientation follows the conventi onal order from the pin 1 marking of the top side view and counter-clockwise. 4. pin orientation a1 starts from the upper left corner of t he top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4-17 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 power supp ly and nc (cont.) signals 672 fpbga 3 900 fpbga 3 vcc lfe2-20: r8, p18, m8, l20, l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2-35/lfe2-50: l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2-70: l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 aa11, aa20, k11, k21, k22, l11, l12, l13, l18, l19, l20, m11, m20, n11, n20, v11, v20, w11, w20, y10, y11, y12, y13, y18, y19, y20 vccio0 d11, d6, g9, j12, k12 j13, j14, k12, k13, k14, k15 vccio1 d16, d21, g18, j15, k15 j17, j18, j20, k17, k18, k20 vccio2 f23, j20, l23, m17, m18 l21, m21, m22, n21, n22, r21 vccio3 aa23, r17, r18, t23, v20 u 21, u22, v21, v22, w21, y22 vccio4 ac16, ac21, u15, v15, y18 a a16, aa17, aa18, aa19, ab17, ab18 vccio5 ac11, ac6, u12, v12, y9 aa12, aa13, aa14, ab12, ab13, ab14 vccio6 aa4, r10, r9, t4, v7 u10, u9, v10, w10, w9, y9 vccio7 f4, j7, l4, m10, m9 l10, l9, m10, n10, p10, r10 vccio8 ae25, v18 aa21, y21 vccj ab5 ad3 vccaux j10, j11, j16, j17, k18, l18, t18, u18, v16, v17, v10, v11, t9, u9, k9, l9 aa15, ab11, ab19, ab20, j11, j12, j19, k19, l22, m9, n9, p21, p9, t10, t21, v9, w22 vccpll lfe2-20: none lfe2-35/lfe2-70: r8, p18 lfe2-50: r8, p18, m8, l20 p22, p8, t22, y7 gnd 1 a2, a25, aa18, aa24, aa3, aa9, ad11, ad16, ad21, ad6, ae1, ae26, af 2, af25, b1, b26, c11, c16, c21, c6, f18, f24, f3, f9, j13, j14, j21, j6, k10, k11, k13, k14, k16, k17, l10, l11, l16, l17, l24, l3, m13, m14, n10, n12, n13, n14, n15, n17, p10, p12, p13, p14, p15, p17, r13, r14, t10, t11, t16, t17, t24, t3, u10, u11, u13, u14, u16, u17, v13, v14, v21, v6 a1, a30, ac28, ac3, ah13, ah18, ah23, ah28, ah3, ah8, ak1, ak30, c13, c18, c23, c28, c3, c8, h28, h3, l14, l15, l16, l17, m12, m13, m14, m15, m16, m17, m18, m19, n12, n13, n14, n15, n16, n17, n18, n19, n28, n3, p11, p12, p13, p14, p15, p16, p17, p18, p19, p20, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, u11, u12, u13, u14, u15, u16, u17, u18, u19, u20, v12, v13, v14, v15, v16, v17, v18, v19, v28, v3, w12, w13, w14, w15, w16, w17, w18, w19, y14, y15, y16, y17 nc 2 lfe2-20: e4, e3, e2, e1, h6, h5, f2, f1, h8, j9, g4, g3, k3, k2, k1, l2, l1, m2, m1, n2, t1, t2, p8, p6, p5, p4, u1, v1, p3, r3, r4, u2, v2, w2, t6, r5, aa19, w17, y19, y17, af20, ae20, aa20, w18, ad20, ae21, af21, af22, r22, t21, p26, p25, r24, r23, p20, r19, p21, p19, p23, p22, n22, r21, n26, n25, j26, j25, j23, k23, h26, h25, h24, h23, f22, e24, d25, c25, d24, b25, h21, g22, b24, c24, d23, c23, e19, c19, b21, b20, d19, b19, g17, e18, g19, f17, a20, a19, e17, d18, m3, n6, p24 lfe2-35: k3, k2, k1, l2, l1, m2, m1, n2, m8, p3, r3, r4, u2, v2, w2, af20, ae20, aa20, w18, ad20, ae21, af21, af22, p26, p25, r24, r23, p20, r19, l20, j26, j25, j23, k23, h26, h25, h24, h23, e19, c19, b21, b20, d19, b19, g17, e18, g19, f17, a20, a19, e17, d18, m3, n6, p24 lfe2-50: n6, p24, m3 lfe2-70: m8, l20, m3, p24, n6 a2, a3, a4, a5, ab28, ac4, ad23, ae1, ae2, ae29, ae3, ae30, ae4, ae5, ae6, af1, af2, af23, af26, af27, af28, af29, af3, af30, af4, af5, ag1, ag13, ag16, ag18, ag2, ag26, ag27, ag28, ag29, ag3, ag30, ag4, ag8, ah1, ah16, ah2, ah26, ah27, ah29, ah30, ah4, aj1, aj2, aj27, aj28, aj29, aj3, aj30, ak2, ak27, ak28, ak29, ak3, b1, b2, b3, b30, b4, b5, c1, c2, c29, c30, c4, d13, d18, d23, d28, d29, d3, d30, d4, e25, e26, e27, e28, e29, e3, e30, e4, e5, e6, f25, f5, f6, g6, g7, k10, k9, n27, n4, r1, r2, v27, v4 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less tha n the actual number of gnd logic connec tions from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. pin orientation a1 starts from the upper left corner of t he top side view with alphabetical order ascending vertically and nu merical order ascending horizontally. 4-18 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m power supply and nc signal 256 fpbga 484 fpbga v cc g7, g9, h7, j10, k10, k8 j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 v ccio0 e7 b5, b9, e7, h9 v ccio1 e10 d13, e16, h14 v ccio2 e14, g12 e21, g18, j15, k19 v ccio3 k12, m14 n19, p15, t18, v21 v ccio4 m10, p12 aa18, r14, v16, w13 v ccio5 m7, p5 aa5, r9, v7, w10 v ccio6 k5, m3 n4, p8, t5, v2 v ccio7 e3, g5 e2, g5, j8, k4 v ccio8 t15 aa22, u19 v ccj k7 w4 v ccaux g8, h10, j7, k9 h11, h12, l 15, l8, m15, m8, r11, r12 v ccpll g10 r8, h15, h8, r15 serdes power 3 c15, b15, c12, a12, c11, c10, c14, c13, b9, c9, c5, c4, c8, c7, a6, c6, b3, c3 c22, b22, c19, a19, c18, c17, c21, c20, b16, c16, c12, c11, c15, c14, a13, c13, b10, c10 gnd 1 a1, a15, a16, a3, a9, b1 2, b6, e15, e2, h14, h8, h9, j3, j8, j9, m15, m2, p9, r12, r5, t1, t16 a1, a10, a16, a22, aa 19, aa4, ab1, ab22, b13, b19, b4, d16, d2, d21, d7, g19, g4, h10, h13, j14, j9, k10, k11, k12, k13, k 15, k20, k3, k8, l10, l11, l12, l13, m10, m11, m12, m13, n10, n11, n12, n13, n15, n20, n3, n8, p14, p9, r10, r13, t19, t4, w16, w2, w21, w7, y10, y13 nc 2 d10, d11, d12, d13, d14, d4, d5, d6, d7, e11, e6, e8, e9, f10, f7, f8, f9 lfe2m20: d14, d15, e14, e15, f13, f14, f15, g12, g13, g14, g15 lfe2m35: d14, d15, e14, e15, f13, f14, f15, g12, g13, g14, g15, u6 lfe2m50: y15, w15, ab20, ab21, aa20, ab19, ab18, y22, y21, y17, y18, y16, w17, y19, y20, w19, w18, v17, v18, d15, g14, g15, d14, e15, e14, f15, f14, f13, g12, g13 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less than the actual number of gnd logic connections from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. for package migration across device densities, the designer must comprehend the package pin requirements for the serdes bloc ks. spe- cifically, the serdes power pins of the largest density device mu st be accounted to accommodate migration to other smaller devi ces using the same package. please refer to tn1160, latticeecp2/m density migration for more details. 4-19 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m power su pply and nc (cont.) signal 672 fpbga 900 fpbga v cc lfe2m35: ad13, ad14, ad16, ad17, ad19, ad21, ad22, ad24, ad25, l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2m50: l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2m50: ah1, ah4, ah5, ah2, ah7, ah12, ah9, ah10, ah13, c13, c10, c9, c12, c7, c2, c5, c4, c1, l12, l13, l18, l19, m1 1, m12, m13, m14, m15, m16, m17, m18, m19, m20, n11, n12, n19, n20, p12, p19, r12, r19, t12, t19, u12, u19, v11, v12, v19, v20, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, y12, y13, y18, y19 lfe2m70/lfe2m100: l12, l13, l18, l19, m11, m12, m13, m14, m15, m16, m17, m18, m19, m20, n11, n12, n19, n20, p12, p19, r12, r19, t12, t19, u12, u19, v11, v12, v19, v20, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, y12, y13, y18, y19 v ccio0 b12, b7, f11, j13, k12 d14, e6, e9, f12, k12, k13 v ccio1 d18, f16, j14, k15 d17, e22, e25, f19, k18, k19 v ccio2 g25, l21, m17, m25, n1 8 f28, j25, k28, m21, m 24, n21, n28, p21, r25 v ccio3 p18, r17, r25, t21, y25 aa28, ab25, ae28, t25, u 21, v21, v28, w21, w24 v ccio4 aa16, ac18, u15, v14 aa18, aa19, ae19, af22, ag17, ag25 v ccio5 aa11, ae12, ae7, u12, v13 aa12, aa13, ae12, af9, ag14, ag6 v ccio6 p9, r10, r2, t6, y2 aa3, ab6, ae3 , t6, u10, v10, v3, w10, w7 v ccio7 g2, l6, m10, m2, n9 f3, j6, k3, m10, m7, n10, n3, p10, r6 v ccio8 ac24, u17 aa25, ad28 v ccj aa7 ag1 v ccaux lfe2m35: ae19, j11, j12, j15, j16, l18, l9, m18, m9, r18, r9, t18, t9, v11, v12, v15, v16 lfe2m50: j11, j12, j15, j16, l18, l9, m18, m9, r18, r9, t18, t9, v1 1, v12, v15, v16 lfe2m50: aj7, b7, aa10, aa11, aa20, aa21, k10, k11, k20, k21, l10, l11, l20 , l21, y10, y11, y20, y21 lfe2m70/lfe2m100: aa10, aa11, aa20, aa21, k10, k11, k20, k21, l10, l11, l20, l21, y10, y11, y20, y21 v ccpll h7, k6, p7, r8, v18, p20, j1 7, g19 n13, n18, v13, v18 serdes power 3 lfe2m35: c25, b25, c22, a22, c21, c20, c24, c23, b19, c19, c15, c14, c18, c17, a16, c16, b13, c13 lfe2m50: ad13, ae13, ad16, af16, ad17, ad18, ad14, ad15, ad19, ae19, ad23, ad24, ad20, ad21, af22, ad22, ae25, ad25, c25, b25, c22, a22, c21, c20, c24, c23, b19, c19, c15, c14, c18, c17, a16, c16, b13, c13 lfe2m50: ah18, aj18, ah21, ak21, ah22, ah23, ah19, ah20, ah24, aj24, ah28, ah29, ah25, ah26, ak27, ah27, aj30, ah30, c30, b30, c27, a27, c26, c25, c29, c28, b24, c24, c20, c19, c23, c22, a21, c21, b18, c18 lfe2m70/lfe2m100: c13, b13, c10, a10, c9, c8, c12, c11, b7, c7, c3, c2, c6, c5, a4, c4, b1, c1, c30, b30, c27, a27, c26, c25, c29, c28, b24, c24, c20, c19, c23, c22, a21, c21, b18, c18, ah18, aj18, ah21, ak21, ah22, ah23, ah19, ah20, ah24, aj24, ah28, ah29, ah25, ah26, ak27, ah27, aj30, ah30, ah1, aj 1, ah4, ak4, ah5, ah6, ah2, ah3, ah7, aj7, ah11, ah12, ah8, ah9, ak10, ah10, aj13, ah13 4-20 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd 1 a13, a19, a2, a25, aa2 , aa25, ab18, ab22, ab5, ab9, ae1, ae11, ae16, ae2 2, ae26, ae6, af13, af19, af2, af25, b1, b11, b16, b22, b26, b6, e18, e22, e5, e9, f2, f25, g11, g16, j22, j5, k11, k13, k14, k16, l10, l11, l16, l1 7, l2, l20, l25, l7, m13, m14, n10, n12, n13, n14, n15, n17, p10, p12, p13, p14, p15, p17, r13, r14, t10, t11, t16, t17, t2, t20, t25, t7, u11, u13, u14, u16, v22, v5, y11, y16 lfe2m50: a1, a13, a18, a24, a30, a7, aa14, aa15, aa16, aa17, aa24, aa27, aa4, ab24, ab7, ad12, ad19, ad27, ae22, ae27, ae4, ae9, af14, af17, af25, af6, aj10, aj21, aj27, aj4, ak1, ak13, ak18, ak24, ak30, ak7, b10, b21, b27, b4, d25, d6, e14, e17, f22, f27, f4 , f9, g12, g19, j24, j7, k14, k15, k16, k17, k2 7, k4, l14, l15, l16, l17, m23, m8, n14, n15, n16, n17, n27, n4, p11, p13, p14, p15, p16, p17, p18, p20, r10, r11, r13, r14, r15, r16, r17, r18, r20, r21, r24, r7, t10, t11, t13, t14, t15, t16, t17, t18, t20, t21, t24, t7, u11, u13, u14, u15, u16, u17, u18, u20, v14, v15, v16, v17, v27, v4, w23, w8, y14, y15, y16, y17 lfe2m70/lfe2m100: a1, a13, a18, a24, a30, a7, aa14, aa15, aa16, aa17, aa24, aa27, aa4, ab24, ab7, ad12, ad19, ad27, ae22, ae27, ae4, ae9, af14, af17, af25, af6, aj10, aj21, aj27, aj4, ak1, ak13, ak18, ak24, ak30 , ak7, b10, b21, b27, b4, d25, d6, e14, e17, f22, f27, f4, f9, g12, g19, j24, j7, k14, k15, k16, k1 7, k27, k4, l14, l15, l16, l17, m23, m8, n14, n15, n16, n17, n27, n4, p11, p13, p14, p15, p16, p17, p18, p20, r10, r11, r13, r14, r15, r16, r17, r18, r20, r21, r24, r7, t10, t11, t13, t14, t15, t16, t17, t18, t20, t21, t24, t7, u11, u13, u14, u15, u 16, u17, u18, u20, v14, v15, v16, v17, v27, v4, w23, w8, y14, y15, y16, y17 nc 2 lfe2m35: ab3, ab4, ac1, ac2, ad15, ad18, ad20, ad23, ae13, ae25, af16, af 22, b4, b5, c26, d20, d21, d22, d23, d24, d25, d26, e20, e21, e25, e26, f20, g20, k10, k17, r4, u1 0, u23, v10, w7, n7, v7 lfe2m50: ab3, ab4, ac1, ac2, b4, b5, c26, d20, d21, d22, d23, d24, d25, d26, e20, e21, e25, e26, f20, g20, k10, k17, r4, u10, u23, v10, w7, ab21, ac20, ac21, ac22, ac23, ac25, ad26, w20 lfe2m50: g5, g4, k7, k8, e1, f2, f1, g3, g2, g1, l9, l7, k6, k5, l8, l6, aa 1, aa2, y3, ab1, y9, y8, y7, aa7, ab2, ab3, aa5, aa6, ab4, ab5, aa8, aa9, aj1, ak4, ah6, ah3, ah11, ah8, ak10, aj13, ab26, ab27, y24, y25, aa29, y28, y30, y29, w22, v22, y27, y26, w30, w29, w25, w26, l24, l23, d30, d29, k24, k25, j27, k26, j26, h26, h27, g26, h23, h24, d28, e28, j18, j19, h17, j17, f18, f17, b13, a10, c8, c11, c3, c6, a4, b1, aa26, ab11, ab12, ab13, ab14, ab15, ab16, ab17, ab19, ab20, ab21, ac11, ac21, ac22, ad21, ad22, ae23, af20, af23, ag23, ag26, f20, f23, g10, g20, g21, h19, h20, h21, h22, j2 0, j21, r9, u22, w9 lfe2m70/lfe2m100: aa26, ab10, ab11, ab12, ab13, ab14, ab15, ab16, ab17, ab19, ab20, ab21, ab9, ac10, ac11, ac21, ac22, ac8, ac9, ad21, ad22, ad4, ad5, ad6, ad 7, ad8, ae23, ae5, ae6, ae7, af20, af23, af5, ag23, ag26, d10, e10, e11, f10, f20, f23, f8, g10, g2 0, g21, g7, g8, g9, h19, h20, h21, h22, h6, h8, h9, j10, j20, j21, j9, k9, r9, u22, w9 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less than the actual number of gnd logic connec tions from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. for package migration across device densities, the designer must comprehend the package pin requirements for the serdes bloc ks. spe- cifically, the serdes power pins of the largest density device must be accounted to accommodate migration to other smaller devi ces using the same package. please refer to tn1160, latticeecp2/m density migration for more details. latticeecp2m power su pply and nc (cont.) signal 672 fpbga 900 fpbga 4-21 pinout information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m power su pply and nc (cont.) signal 1152 fpbga v cc aa13, aa14, aa15, aa16, aa17, aa18, aa19, aa20, aa21, aa22, ab14, ab15, ab20, ab21, n14, n15, n20, n21, p13, p14, p15, p16, p17, p18, p19, p20, p21, p22, r13, r14, r21, r22, t14, t21, u14, u21, v14, v21, w14, w21, y13, y14, y21, y22 v ccio0 c12, c16, e14, h12, h16, m14, m15 v ccio1 c19, c23, e21, h19, h23, m20, m21 v ccio2 g32, k28, k32, n27, n32, p23, r23, t27, t32 v ccio3 aa23, ab27, ab32, ae28, ae32, ah32, w27, w32, y23 v ccio4 ac20, ac21, ag19, ag23, ak21, am19, am23 v ccio5 ac14, ac15, ag12, ag16, ak14, am12, am16 v ccio6 aa12, ab3, ab8, ae3, ae7, ah3, w3, w8, y12 v ccio7 g3, k3, k7, n3, n8, p12, r12, t3, t8 v ccio8 ad28, ag32 v ccj ak3 v ccaux ab12, ab13, ab22, ab23, ac13, ac22, m13, m22, n12, n13, n22, n23 v ccpll r15, r20, y15, y20 serdes power 3 d7, b9, b8, d9, b7, e7, b6, d8, e6, d6, d4, b5, d3, b4, c1, b3, b1, b2, b33, b34, b32, c34, b31, d32, b30, d31, e29, d29, d27, b29, e28, b28, d26, b27, b26, d28, al28, an26, an27, al26, an28, ak28, an29, al27, al29, ak29, al31, an30, al32, an31, am34, an32, an34, an33, an2, an1, an3, am1, an4, al3, an5, al4, al6, ak6, al8, an6, ak7, an7, al9, an8, an9, al7 gnd 1 a1, a10, a13, a22, a25, a34, ab16, ab17, ab18, ab19, ab26, ab31, ab4, ab9, ac16, ac17, ac18, ac19, ad27, ae27, ae31, ae4, ae8, af12, af16, af19, af23, ag31, ah31, ah4, aj14, aj21, ak27, ak8, al10, al16, al19, al2, al25, al33, ap1, ap10, ap13, ap22, ap25, ap34, d10, d16, d19, d2, d25, d33, e27, e8, f14, f21, g31, g4, j12, j16, j19, j23, k27, k31, k4, k8, m16, m17, m18, m19, n16, n17, n18, n19, n26, n31, n4, n9, r16, r17, r18, r19, t12, t13, t15, t16, t17, t18, t19, t20, t22, t23, t26, t31, t4, t9, u12, u13, u15, u16, u17, u18, u19, u20, u22, u23, v12, v13, v15, v16, v17, v18, v19, v20, v22, v23, w12, w13, w15, w16, w17, w18, w19, w20, w22, w23, w26, w31, w4, w9, y16, y17, y18, y19 nc 2 lfe2m70: h2, h1, g5, g6, m9, m10, h3, h4, p3, p4, p9, m7, p1, p2, n7, p7, ac7, ac5, ac6, ad5, ad4, ad3, ad10, ad8, ad2, ad1, ad9, ac11, ad6, ad7, ae1, ae2, aj12, ah12, al13, ak13, ae14, ag13, ah22, ah21, ag22, ag21, af33, af34, ac27, ac28, ad29, ad30, ae33, ae34, ad32, ad31, ab25, ac25, ab28, aa26, ad33, ad34, p30, p29, p31, p32, r25, t24, n34, n33, f24, g23, j22, g22, h21, k21, l19, l20, l18, k19, j14, l15, h14, k14, f12, d11, f11, e11, a11, a12, a23, a24, aa11, ab11, ac26, ac30, ad11, ad12, ad13, ad14, ad15, ad19, ad21, ad22, ad23, ae10, ae11, ae12, ae13, ae19, ae21, ae22, ae23, af11, af21, af22, af24, af8, af9, ag10, ag11, ag24, ag25, ag26, ag3, ag7, ag8, ag9, ah10, ah11, ah13, ah24, ah25, ah26, ah27, ah5, ah6, ah7, ah8, ah9, aj10, aj11, aj13, aj24, aj25, aj26, aj27, aj3, aj4, aj5, aj6, aj7, aj8, aj9, ak10, ak11, ak12, ak24, ak25, ak26, ak4, ak9, al11, al12, al34, am10, am11, am13, am25, an10, an11, an12, an13, an24, an25, ap11, ap12, ap24, b10, b11, b12, b13, b22, b23, b24, b25, c10, c11, c13, c22, c24, c 25, d1, d15, d24, d34, e10, e24, e25, e26, e3, e31, e32, e33, e34, e4, e9, f10, f25, f26, f27, f28, f29, f30, f31, f32, f33, f34, f5, f6, f7, f8, f9, g10, g11, g24, g25, g26, g27, g28, g29, g30, g33, g34, g7, g8, g9, h10, h11, h24, h25, h26, h27, h28, h29, h8, h9, j10, j11, j24, j25, j26, j9, k10, k11, k12, k13, k23, k24, k25, k26, l11, l12, l13, l14, l21, l22, l23, l24, l25, l26, m11, m24, m25, m6, m8, n10, n11, p10, p25, p26, r9, t11, u11, w11, y10, y11 lfe2m100: a11, a12, a23, a24, aa11, ab11, ac26, ac30, ad11, ad12, ad13, ad14, ad15, ad19, ad21, ad22, ad23, ae10, ae11, ae12, ae13, ae19, ae21, ae22, ae23, af11, af21, af22, af24, af8, af9, ag10, ag11, ag24, ag25, ag26, ag3, ag7, ag8, ag9, ah10, ah11, ah13, ah24, ah25, ah26, ah27, ah5, ah6, ah7, ah8, ah9, aj10, aj11, aj13, aj24, aj25, aj26, aj27, aj3, aj4, aj5, aj6, aj7, aj8, aj9, ak10, ak11, ak12, ak24, ak25, ak26, ak4, ak9, al11, al12, al34, am10, am11, am13, am25, an10, an11, an12, an13, an24, an25, ap11, ap12, ap24, b10, b11, b12, b13, b22, b23, b24, b25, c10, c11, c13, c22, c2 4, c25, d1, d15, d24, d34, e10, e24, e25, e26, e3, e31, e32, e33, e34, e4, e9, f10, f25, f26, f27, f28, f29, f30, f31, f32, f33, f34, f5, f6, f7, f8, f9, g10, g11,g24, g25, g26, g27, g28, g29, g30, g33, g34, g7, g8, g9, h10, h11, h24, h25, h26, h27, h28, h29, h8, h9, j10, j11, j24, j25, j26, j9, k10, k11, k12, k13, k23, k24, k25, k26, l11, l12, l13, l14, l21, l22, l23, l24, l25, l26, m11, m24, m25, m6, m8, n10, n11, p10, p25, p26, r9, t11, u11, w11, y10, y11 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less than the actual number of gnd logic connections from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. for package migration across device densities, the designer must comprehend the package pin requirements for the serdes bloc ks. spe- cifically, the serdes power pins of the la rgest density device must be accounted to accommodate migration to other smaller devi ces using the same package. please refer to tn1160, latticeecp2/m density migration for more details. 4-22 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-6e/se and lfe2-12e/se logic signal connections: 144 tqfp lfe2-6e/se lfe2-12e/12se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 1 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7 t (lvds)* 2 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7 c (lvds)* 3 pl4a 7 t (lvds)* pl4a 7 t (lvds)* 4 pl4b 7 c (lvds)* pl4b 7 c (lvds)* 5 pl6a 7 ldq10 t (lvds)* pl6a 7 ldq10 t (lvds)* 6 vccaux - vccaux - 7 pl6b 7 ldq10 c (lvds)* pl6b 7 ldq10 c (lvds)* 8 pl8a 7 ldq10 t (lvds)* pl8a 7 ldq10 t (lvds)* 9vccio77 vccio77 10 pl8b 7 ldq10 c (lvds)* pl8b 7 ldq10 c (lvds)* 11 gnd - gnd - 12 pl12a 7 ldq10 t (lvds)* pl12a 7 ldq10 t (lvds)* 13 pl12b 7 ldq10 c (lvds)* pl12b 7 ldq10 c (lvds)* 14 pl13a 7 pclkt7_0/ldq10 t pl13a 7 pclkt7_0/ldq10 t 15 pl13b 7 pclkc7_0/ldq10 c pl13b 7 pclkc7_0/ldq10 c 16 vcc - vcc - 17 pl15a 6 pclkt6_0 t (lvds)* pl15a 6 pclkt6_0 t (lvds)* 18 pl15b 6 pclkc6_0 c (lvds)* pl15b 6 pclkc6_0 c (lvds)* 19 pl16a 6 vref2_6 t pl16a 6 vref2_6 t 20 pl16b 6 vref1_6 c pl16b 6 vref1_6 c 21 gnd - gnd - 22 vcc - vcc - 23 pl18a 6 llm0_gdllt_fb_a t pl18a 6 llm0_gdllt_fb_a t 24 pl18b 6 llm0_gdllc_fb_a c pl18b 6 llm0_gdllc_fb_a c 25 llm0_pllcap 6 llm0_pllcap 6 26 pl20a 6 llm0_gpllt_in_a** t (lvds)* pl20a 6 llm0_gpllt_in_a** t (lvds)* 27 pl20b 6 llm0_gpllc_in_a** c (lvds)* pl20b 6 llm0_gpllc_in_a** c (lvds)* 28 pl22a 6 pl22a 6 29 vcc - vcc - 30 gnd - gnd - 31 vccio6 6 vccio6 6 32 tck - tck - 33 tdi - tdi - 34 tdo - tdo - 35 vccj - vccj - 36 tms - tms - 37 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t 38 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c 39 vccaux - vccaux - 40 pb4a 5 bdq6 t pb6a 5 bdqs6 t 41 pb4b 5 bdq6 c pb6b 5 bdq6 c 42 vccio5 5 vccio5 5 43 pb6a 5 bdqs6 t pb12a 5 bdq15 t 44 pb6b 5 bdq6 c pb12b 5 bdq15 c 45 nc 5 pb16a 5 bdq15 t 4-23 pinout information lattice semiconductor latticeecp2 /m family data sheet 46 nc 5 pb16b 5 bdq15 c 47 gnd - gnd - 48 vcc vcc - 49 pb8a 5 pclkt5_0/bdq6 t pb26a 5 pclkt5_0/bdq24 t 50 pb8b 5 pclkc5_0/bdq6 c pb26b 5 pclkc5_0/bdq24 c 51 gnd - gnd - 52 pb13a 4 pclkt4_0/bdq15 t pb31a 4 pclkt4_0/bdq33 t 53 pb13b 4 pclkc4_0/bdq15 c pb31b 4 pclkc4_0/bdq33 c 54 vcc - vcc - 55 pb14a 4 bdq15 t pb34a 4 bdq33 t 56 pb14b 4 bdq15 c pb34b 4 bdq33 c 57 pb16a 4 bdq15 t pb40a 4 bdq42 t 58 pb16b 4 bdq15 c pb40b 4 bdq42 c 59 pb18a 4 bdq15 t pb44a 4 bdq42 t 60 pb18b 4 bdq15 c pb44b 4 bdq42 c 61 gnd - gnd - 62 pb20a 4 bdq24 t pb48a 4 bdq51 t 63 pb20b 4 bdq24 c pb48b 4 bdq51 c 64 vccio4 4 vccio4 4 65 pb22a 4 bdq24 t pb50a 4 bdq51 t 66 pb22b 4 bdq24 c pb50b 4 bdq51 c 67 pb24a 4 bdqs24 t pb52a 4 bdq51 t 68 pb24b 4 bdq24 c pb52b 4 bdq51 c 69 pb26a 4 bdq24 t pb54a 4 bdq51 t 70 pb26b 4 bdq24 c pb54b 4 bdq51 c 71 pb28a 4 vref2_4/bdq24 t pb55a 4 vref2_4/bdq51 t 72 pb28b 4 vref1_4/bdq24 c pb55b 4 vref1_4/bdq51 c 73 cfg1 8 cfg1 8 74 cfg2 8 cfg2 8 75 programn 8 programn 8 76 initn 8 initn 8 77 cfg0 8 cfg0 8 78 cclk 8 cclk 8 79 done 8 done 8 80 pr29a 8 d0/spifastn pr29a 8 d0/spifastn 81 gnd - gnd - 82 pr26a 8 d6 pr26a 8 d6 83 vcc - vcc - 84 pr25b 8 d7/spid0 c pr25b 8 d7/spid0 c 85 vccio8 8 vccio8 8 86 pr25a 8 di/csspi0n t pr25a 8 di/csspi0n t 87 pr24b 8 dout/cson c pr24b 8 dout/cson c 88 pr24a 8 busy/sispi t pr24a 8 busy/sispi t 89 vccio3 3 vccio3 3 90 vccaux - vccaux - lfe2-6e/se and lfe2-12e/se logic sign al connections: 144 tqfp (cont.) lfe2-6e/se lfe2-12e/12se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-24 pinout information lattice semiconductor latticeecp2 /m family data sheet 91 pr20b 3 rlm0_gpllc_in_a** c (lvds)* pr20b 3 rlm0_gpllc_in_a** c (lvds)* 92 pr20a 3 rlm0_gpllt_in_a** t (lvds)* pr20a 3 rlm0_gpllt_in_a** t (lvds)* 93 rlm0_pllcap 3 rlm0_pllcap 3 94 vcc - vcc - 95 gnd - gnd - 96 pr17b 3 rlm0_gdllc_in_a** c (lvds)* pr17b 3 rlm0_gdllc_in_a** c (lvds)* 97 pr17a 3 rlm0_gdllt_in_a** t (lvds)* pr17a 3 rlm0_gdllt_in_a** t (lvds)* 98 pr16b 3 vref2_3 c pr16b 3 vref2_3 c 99 pr16a 3 vref1_3 t pr16a 3 vref1_3 t 100 pr15b 3 pclkc3_0 c (lvds)* pr15b 3 pclkc3_0 c (lvds)* 101 pr15a 3 pclkt3_0 t (lvds)* pr15a 3 pclkt3_0 t (lvds)* 102 vcc - vcc - 103 pr13b 2 pclkc2_0/rdq10 c pr13b 2 pclkc2_0/rdq10 c 104 pr13a 2 pclkt2_0/rdq10 t pr13a 2 pclkt2_0/rdq10 t 105 gnd - gnd - 106 vccio2 2 vccio2 2 107 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2 c (lvds)* 108 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2 t (lvds)* 109 pt28b 1 vref2_1 c pt55b 1 vref2_1 c 110 pt28a 1 vref1_1 t pt55a 1 vref1_1 t 111 pt26b 1 c pt54b 1 c 112 pt26a 1 t pt54a 1 t 113 pt24b 1 c pt52b 1 c 114 pt24a 1 t pt52a 1 t 115 pt22b 1 c pt50b 1 c 116 pt22a 1 t pt50a 1 t 117 vccio1 1 vccio1 1 118 pt20b 1 c pt48b 1 c 119 pt20a 1 t pt48a 1 t 120 gnd - gnd - 121 pt18b 1 c pt44b 1 c 122 pt18a 1 t pt44a 1 t 123 pt16a 1 pt40b 1 c 124 nc 1 pt40a 1 t 125 pt14b 1 c pt34b 1 c 126 pt14a 1 t pt34a 1 t 127 nc 1 nc 1 128 vcc - vcc - 129 pt12b 1 pclkc1_0 c pt30b 1 pclkc1_0 c 130 pt12a 1 pclkt1_0 t pt30a 1 pclkt1_0 t 131 pt10b 0 pclkc0_0 c pt28b 0 pclkc0_0 c 132 xres 0 xres 0 133 gnd - gnd - 134 pt10a 0 pclkt0_0 t pt28a 0 pclkt0_0 t 135 vcc - vcc - lfe2-6e/se and lfe2-12e/se logic sign al connections: 144 tqfp (cont.) lfe2-6e/se lfe2-12e/12se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-25 pinout information lattice semiconductor latticeecp2 /m family data sheet 136 pt6b 0 c pt16b 0 c 137 pt6a 0 t pt16a 0 t 138 gnd - gnd - 139 vccio0 0 vccio0 0 140 pt4b 0 c pt6b 0 c 141 pt4a 0 t pt6a 0 t 142 vccaux - vccaux - 143 pt2b 0 vref2_0 c pt2b 0 vref2_0 c 144 pt2a 0 vref1_0 t pt2a 0 vref1_0 t * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between g nd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one-to-one connection with a package ball or pin. lfe2-6e/se and lfe2-12e/se logic sign al connections: 144 tqfp (cont.) lfe2-6e/se lfe2-12e/12se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-26 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-12e/se and lfe2-20e/se logic signal connections: 208 pqfp lfe2-12e/se lfe2-20e/se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 1 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7 t (lvds)* 2 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7 c (lvds)* 3 pl4a 7 t (lvds)* pl6a 7 ldq8 t (lvds)* 4 pl4b 7 c (lvds)* pl6b 7 ldq8 c (lvds)* 5gnd- gnd- 6 pl6a 7 ldq10 t (lvds)* pl12a 7 ldq16 t (lvds)* 7 vccaux - vccaux - 8 pl6b 7 ldq10 c (lvds)* pl12b 7 ldq16 c (lvds)* 9 pl8a 7 ldq10 t (lvds)* pl14a 7 ldq16 t (lvds)* 10 vccio7 7 vccio7 7 11 pl8b 7 ldq10 c (lvds)* pl14b 7 ldq16 c (lvds)* 12 vcc - vcc - 13 gnd- gnd- 14 vccio7 7 vccio7 7 15 pl12a 7 ldq10 t (lvds)* pl18a 7 ldq16 t (lvds)* 16 pl12b 7 ldq10 c (lvds)* pl18b 7 ldq16 c (lvds)* 17 gnd- gnd- 18 pl13a 7 pclkt7_0/ldq10 t pl19a 7 pclkt7_0/ldq16 t 19 vcc - vcc - 20 pl13b 7 pclkc7_0/ldq10 c pl19b 7 pclkc7_0/ldq16 c 21 pl15a 6 pclkt6_0 t (lvds)* pl21a 6 pclkt6_0/ldq25 t (lvds)* 22 pl15b 6 pclkc6_0 c (lvds)* pl21b 6 pclkc6_0/ldq25 c (lvds)* 23 pl16a 6 vref2_6 t pl22a 6 vref2_6/ldq25 t 24 pl16b 6 vref1_6 c pl22b 6 vref1_6/ldq25 c 25 gnd- gnd- 26 pl17a 6 llm0_gdllt_in_a** t (lvds)* pl27a 6 llm0_gdllt_in_a**/ldq25 t (lvds)* 27 pl17b 6 llm0_gdllc_in_a** c (lvds)* pl27b 6 llm0_gdllc_in_a**/ldq25 c (lvds)* 28 vcc - vcc - 29 llm0_pllcap 6 llm0_pllcap 6 30 vccaux - vccaux - 31 pl20a 6 llm0_gpllt_in_a** t (lvds)* pl3 0a 6 llm0_gpllt_in_a**/ldq34 t (lvds)* 32 gnd- gnd- 33 pl21a 6 llm0_gpllt_fb_a t pl31a 6 llm0_gpllt_fb_a/ldq34 t 34 pl20b 6 llm0_gpllc_in_a** c (lvds)* pl3 0b 6 llm0_gpllc_in_a**/ldq34 c (lvds)* 35 pl21b 6 llm0_gpllc_fb_a c pl31b 6 llm0_gpllc_fb_a/ldq34 c 36 pl23a 6 pl33a 6 ldq34 37 pl24a 6 ldq28 t (lvds)* pl38a 6 ldq42 t (lvds)* 38 vccio6 6 vccio6 6 39 pl24b 6 ldq28 c (lvds)* pl38b 6 ldq42 c (lvds)* 40 vcc - vcc - 41 pl26a 6 ldq28 t (lvds)* pl40a 6 ldq42 t (lvds)* 42 gnd- gnd- 43 pl26b 6 ldq28 c (lvds)* pl40b 6 ldq42 c (lvds)* 44 vccio6 6 vccio6 6 45 pl28a 6 ldqs28 t (lvds)* pl42a 6 ldqs42 t (lvds)* 4-27 pinout information lattice semiconductor latticeecp2 /m family data sheet 46 pl28b 6 ldq28 c (lvds)* pl42b 6 ldq42 c (lvds)* 47 pl30a 6 ldq28 pl44a 6 ldq42 48 tck - tck - 49 tdi - tdi - 50 tdo- tdo- 51 vccj - vccj - 52 tms - tms - 53 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t 54 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c 55 vccio5 5 vccio5 5 56 pb6a 5 bdqs6 t pb6a 5 bdqs6 t 57 pb6b 5 bdq6 c pb6b 5 bdq6 c 58 pb8a 5 bdq6 t pb8a 5 bdq6 t 59 pb8b 5 bdq6 c pb8b 5 bdq6 c 60 gnd- gnd- 61 pb12a 5 bdq15 t pb12a 5 bdq15 t 62 pb12b 5 bdq15 c pb12b 5 bdq15 c 63 vccio5 5 vccio5 5 64 pb16a 5 bdq15 t pb16a 5 bdq15 t 65 pb16b 5 bdq15 c pb16b 5 bdq15 c 66 pb18a 5 bdq15 t pb18a 5 bdq15 t 67 pb18b 5 bdq15 c pb18b 5 bdq15 c 68 gnd- gnd- 69 pb20a 5 bdq24 t pb30a 5 bdq33 t 70 vccaux - vccaux - 71 pb20b 5 bdq24 c pb30b 5 bdq33 c 72 pb22a 5 bdq24 t pb32a 5 bdq33 t 73 pb22b 5 bdq24 c pb32b 5 bdq33 c 74 vcc - vcc - 75 pb26a 5 pclkt5_0/bdq24 t pb35a 5 pclkt5_0/bdq33 t 76 pb26b 5 pclkc5_0/bdq24 c pb35b 5 pclkc5_0/bdq33 c 77 gnd- gnd- 78 pb31a 4 pclkt4_0/bdq33 t pb40a 4 pclkt4_0/bdq42 t 79 pb31b 4 pclkc4_0/bdq33 c pb40b 4 pclkc4_0/bdq42 c 80 vcc - vcc - 81 gnd- gnd- 82 pb34a 4 bdq33 t pb42a 4 bdqs42 t 83 pb34b 4 bdq33 c pb42b 4 bdq42 c 84 pb36a 4 bdq33 t pb44a 4 bdq42 t 85 pb36b 4 bdq33 c pb44b 4 bdq42 c 86 vccaux - vccaux - 87 pb40a 4 bdq42 t pb50a 4 bdq51 t 88 pb40b 4 bdq42 c pb50b 4 bdq51 c 89 gnd- gnd- 90 pb42a 4 bdqs42 t pb52a 4 bdq51 t 91 pb42b 4 bdq42 c pb52b 4 bdq51 c lfe2-12e/se and lfe2-20e/ se logic signal connecti ons: 208 pqfp (cont.) lfe2-12e/se lfe2-20e/se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-28 pinout information lattice semiconductor latticeecp2 /m family data sheet 92 pb44a 4 bdq42 t pb54a 4 bdq51 t 93 vccio4 4 vccio4 4 94 pb44b 4 bdq42 c pb54b 4 bdq51 c 95 pb48a 4 bdq51 t pb58a 4 bdq60 t 96 pb48b 4 bdq51 c pb58b 4 bdq60 c 97 vcc - vcc - 98 pb52a 4 bdq51 t pb60a 4 bdqs60 t 99 pb52b 4 bdq51 c pb60b 4 bdq60 c 100 vccio4 4 vccio4 4 101 pb54a 4 bdq51 pb63a 4 bdq60 102 gnd - gnd - 103 pb55a 4 vref2_4/bdq51 t pb64a 4 vref2_4/bdq60 t 104 pb55b 4 vref1_4/bdq51 c pb64b 4 vref1_4/bdq60 c 105 cfg1 8 cfg1 8 106 programn 8 programn 8 107 cfg2 8 cfg2 8 108 initn 8 initn 8 109 cfg0 8 cfg0 8 110 cclk 8 cclk 8 111 done 8 done 8 112 pr29a 8 spifastn pr43a 8 spifastn 113 vccio8 8 vccio8 8 114 pr26a 8 pr40a 8 115 gnd - gnd - 116 vcc - vcc - 117 pr25b 8 c pr39b 8 c 118 vccio8 8 vccio8 8 119 pr25a 8 csspi0n t pr39a 8 csspi0n t 120 pr24b 8 dout/cson c pr38b 8 dout/cson c 121 pr24a 8 busy/sispi t pr38a 8 busy/sispi t 122 gnd - gnd - 123 vccio3 3 vccio3 3 124 pr21a 3 rlm0_gpllt_fb_a pr31a 3 rlm0_gpllt_fb_a/rdq34 125 vccaux - vccaux - 126 pr20b 3 rlm0_gpllc_in_a** c (lvds)* p r30b 3 rlm0_gpllc_in_a**/rdq34 c (lvds)* 127 pr20a 3 rlm0_gpllt_in_a** t (lvds)* pr30a 3 rlm0_gpllt_in_a**/rdq34 t (lvds)* 128 rlm0_pllcap 3 rlm0_pllcap 3 129 vcc - vcc - 130 pr18b 3 rlm0_gdllc_fb_a c pr28b 3 rlm0_gdllc_fb_a/rdq25 c 131 pr18a 3 rlm0_gdllt_fb_a t pr28a 3 rlm0_gdllt_fb_a**/rdq25 t 132 pr17b 3 rlm0_gdllc_in_a** c (lvds)* pr27b 3 rlm0_gdllc_in_a/rdq25 c (lvds)* 133 pr17a 3 rlm0_gdllt_in_a** t (lvds)* pr27a 3 rlm0_gdllt_in_a**/rdq25 t (lvds)* 134 pr16b 3 vref2_3 c pr22b 3 vref2_3/rdq25 c 135 vccio3 3 vccio3 3 136 pr16a 3 vref1_3 t pr22a 3 vref1_3/rdq25 t 137 pr15b 3 pclkc3_0 c (lvds)* pr21b 3 pclkc3_0/rdq25 c (lvds)* lfe2-12e/se and lfe2-20e/ se logic signal connecti ons: 208 pqfp (cont.) lfe2-12e/se lfe2-20e/se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-29 pinout information lattice semiconductor latticeecp2 /m family data sheet 138 pr15a 3 pclkt3_0 t (lvds)* pr21a 3 pclkt3_0/rdq25 t (lvds)* 139 gnd - gnd - 140 vcc - vcc - 141 pr13b 2 pclkc2_0/rdq10 c pr19b 2 pclkc2_0/rdq16 c 142 pr13a 2 pclkt2_0/rdq10 t pr19a 2 pclkt2_0/rdq16 t 143 vccio2 2 vccio2 2 144 pr12a 2 rdq10 pr16a 2 rdqs16 145 gnd - gnd - 146 vcc - vcc - 147 pr8b 2 rdq10 c (lvds)* pr14b 2 rdq16 c (lvds)* 148 vccio2 2 vccio2 2 149 pr8a 2 rdq10 t (lvds)* pr14a 2 rdq16 t (lvds)* 150 pr6b 2 rdq10 c (lvds)* pr12b 2 rdq16 c (lvds)* 151 vccaux - vccaux - 152 pr6a 2 rdq10 t (lvds)* pr12a 2 rdq16 t (lvds)* 153 pr4b 2 c (lvds)* pr6b 2 rdq8 c (lvds)* 154 pr4a 2 t (lvds)* pr6a 2 rdq8 t (lvds)* 155 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2 c (lvds)* 156 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2 t (lvds)* 157 pt55b 1 vref2_1 c pt64b 1 vref2_1 c 158 pt55a 1 vref1_1 t pt64a 1 vref1_1 t 159 gnd - gnd - 160 pt54b 1 c pt62b 1 c 161 pt54a 1 t pt62a 1 t 162 vccio1 1 vccio1 1 163 pt52b 1 c pt60b 1 c 164 pt52a 1 t pt60a 1 t 165 pt50b 1 c pt58b 1 c 166 pt50a 1 t pt58a 1 t 167 pt48b 1 c pt56b 1 c 168 pt48a 1 t pt56a 1 t 169 gnd - gnd - 170 vccio1 1 vccio1 1 171 vcc - vcc - 172 pt40b 1 c pt50b 1 c 173 pt40a 1 t pt50a 1 t 174 vccaux - vccaux - 175 gnd - gnd - 176 pt36b 1 c pt44b 1 c 177 pt36a 1 t pt44a 1 t 178 pt34b 1 c pt42b 1 c 179 pt34a 1 t pt42a 1 t 180 pt30b 1 pclkc1_0 c pt39b 1 pclkc1_0 c 181 pt30a 1 pclkt1_0 t pt39a 1 pclkt1_0 t 182 xres 1 xres 1 183 pt28b 0 pclkc0_0 c pt37b 0 pclkc0_0 c lfe2-12e/se and lfe2-20e/ se logic signal connecti ons: 208 pqfp (cont.) lfe2-12e/se lfe2-20e/se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-30 pinout information lattice semiconductor latticeecp2 /m family data sheet 184 gnd - gnd - 185 pt28a 0 pclkt0_0 t pt37a 0 pclkt0_0 t 186 pt26b 0 c pt36b 0 c 187 pt26a 0 t pt36a 0 t 188 vcc - vcc - 189 pt20b 0 c pt30b 0 c 190 vccaux - vccaux - 191 pt20a 0 t pt30a 0 t 192 gnd - gnd - 193 pt18b 0 c pt26b 0 c 194 pt18a 0 t pt26a 0 t 195 vccio0 0 vccio0 0 196 pt16b 0 c pt20b 0 c 197 pt16a 0 t pt20a 0 t 198 vcc - vcc - 199 pt12b 0 c pt12b 0 c 200 pt12a 0 t pt12a 0 t 201 gnd - gnd - 202 pt8b 0 c pt8b 0 c 203 pt8a 0 t pt8a 0 t 204 pt6b 0 c pt6b 0 c 205 pt6a 0 t pt6a 0 t 206 vccio0 0 vccio0 0 207 pt2b 0 vref2_0 c pt2b 0 vref2_0 c 208 pt2a 0 vref1_0 t pt2a 0 vref1_0 t * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the s ubstrate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-12e/se and lfe2-20e/ se logic signal connecti ons: 208 pqfp (cont.) lfe2-12e/se lfe2-20e/se pin number pin/pad function bank dual function differential pin/pad function bank dual function differential 4-31 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-6e/se and lfe2-12e/se logic signal connections: 256 fpbga lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential c3 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7 t (lvds)* c2 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7 c (lvds)* vccio vccio7 7 vccio7 7 --- -- d3pl5a7 tpl5a7 t d4 pl4a 7 t (lvds)* pl4a 7 t (lvds)* d2pl5b7 cpl5b7 c gnd gndio7 - gndio7 - e4 pl4b 7 c (lvds)* pl4b 7 c (lvds)* b1 pl7a 7 ldq10 t pl7a 7 ldq10 t c1 pl7b 7 ldq10 c pl7b 7 ldq10 c f5 pl9a 7 ldq10 t pl9a 7 ldq10 t vccio vccio7 7 vccio7 7 f4 pl8a 7 ldq10 t (lvds)* pl8a 7 ldq10 t (lvds)* g6 pl9b 7 ldq10 c pl9b 7 ldq10 c g4 pl8b 7 ldq10 c (lvds)* pl8b 7 ldq10 c (lvds)* d1 pl10a 7 ldqs10 t (lvds)* pl10a 7 ldqs10 t (lvds)* gnd gndio7 - gndio7 - e1 pl10b 7 ldq10 c (lvds)* pl10b 7 ldq10 c (lvds)* f3 pl11a 7 ldq10 t pl11a 7 ldq10 t g3 pl11b 7 ldq10 c pl11b 7 ldq10 c vccio vccio7 7 vccio7 7 f2 pl12a 7 ldq10 t (lvds)* pl12a 7 ldq10 t (lvds)* f1 pl12b 7 ldq10 c (lvds)* pl12b 7 ldq10 c (lvds)* gnd gndio7 - gndio7 - g2 pl13a 7 pclkt7_0/ldq10 t pl13a 7 pclkt7_0/ldq10 t g1 pl13b 7 pclkc7_0/ldq10 c pl13b 7 pclkc7_0/ldq10 c h6 pl15a 6 pclkt6_0 t (lvds)* pl15a 6 pclkt6_0 t (lvds)* vccio vccio6 6 vccio6 6 h5 pl15b 6 pclkc6_0 c (lvds)* pl15b 6 pclkc6_0 c (lvds)* h4 pl16a 6 vref2_6 t pl16a 6 vref2_6 t gnd gndio6 - gndio6 - h3 pl16b 6 vref1_6 c pl16b 6 vref1_6 c h2 pl17a 6 llm0_gdllt_in_a** t (lvds)* pl17a 6 llm0_gdllt_in_a** t (lvds)* h1 pl17b 6 llm0_gdllc_in_a** c (lvds)* pl17b 6 llm0_gdllc_in_a** c (lvds)* g10 vcc - vcc - j4 pl18a 6 llm0_gdllt_fb_a t pl18a 6 llm0_gdllt_fb_a t j5 pl18b 6 llm0_gdllc_fb_a c pl18b 6 llm0_gdllc_fb_a c j6 llm0_pllcap 6 llm0_pllcap 6 k4 pl20a 6 llm0_gpllt_in_a** t (lvds)* pl20a 6 llm0_gpllt_in_a** t (lvds)* gnd gndio6 - gndio6 - j1 pl21a 6 llm0_gpllt_fb_a t pl21a 6 llm0_gpllt_fb_a t k3 pl20b 6 llm0_gpllc_in_a** c (lvds)* pl20b 6 llm0_gpllc_in_a** c (lvds)* vccio vccio6 6 vccio6 6 j2 pl21b 6 llm0_gpllc_fb_a c pl21b 6 llm0_gpllc_fb_a c 4-32 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gndio6 - gndio6 - l2 pl24a 6 ldq28 t (lvds)* pl24a 6 ldq28 t (lvds)* k2 pl25a 6 ldq28 t pl25a 6 ldq28 t l3 pl24b 6 ldq28 c (lvds)* pl24b 6 ldq28 c (lvds)* k1 pl25b 6 ldq28 c pl25b 6 ldq28 c vccio vccio6 6 vccio6 6 l4 pl26a 6 ldq28 t (lvds)* pl26a 6 ldq28 t (lvds)* l1 pl27a 6 ldq28 t pl27a 6 ldq28 t l5 pl26b 6 ldq28 c (lvds)* pl26b 6 ldq28 c (lvds)* m1 pl27b 6 ldq28 c pl27b 6 ldq28 c gnd gndio6 - gndio6 - n1 pl29a 6 ldq28 t pl29a 6 ldq28 t n2 pl28a 6 ldqs28 t (lvds)* pl28a 6 ldqs28 t (lvds)* p1 pl29b 6 ldq28 c pl29b 6 ldq28 c vccio vccio6 6 vccio6 6 p2 pl28b 6 ldq28 c (lvds)* pl28b 6 ldq28 c (lvds)* r1 pl30a 6 ldq28 t (lvds)* pl30a 6 ldq28 t (lvds)* gnd gndio6 - gndio6 - r2 pl30b 6 ldq28 c (lvds)* pl30b 6 ldq28 c (lvds)* n4 tdi - tdi - m4 tck - tck - p3 tdo - tdo - n3 tms - tms - k7 vccj - vccj - m5 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t k6 nc - pb3a 5 bdq6 m6 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c r3 nc - pb5a 5 bdq6 t p4 nc - pb5b 5 bdq6 c - - - vccio 5 - - - gndio5 5 n5 pb3a 5 bdq6 t pb21a 5 bdq24 t n6 pb3b 5 bdq6 c pb21b 5 bdq24 c t2 pb4a 5 bdq6 t pb22a 5 bdq24 t p6 pb5a 5 bdq6 t pb23a 5 bdq24 t vccio vccio5 5 vccio5 5 t3 pb4b 5 bdq6 c pb22b 5 bdq24 c r6 pb5b 5 bdq6 c pb23b 5 bdq24 c gnd gndio5 - gndio5 - r4 pb6a 5 bdqs6 t pb24a 5 bdqs24 t l6 pb7a 5 bdq6 t pb25a 5 bdq24 t t4 pb6b 5 bdq6 c pb24b 5 bdq24 c l7 pb7b 5 bdq6 c pb25b 5 bdq24 c n7 pb8a 5 pclkt5_0/bdq6 t pb26a 5 pclkt5_0/bdq24 t vccio vccio5 5 vccio5 5 lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-33 pinout information lattice semiconductor latticeecp2 /m family data sheet m8 pb8b 5 pclkc5_0/bdq6 c pb26b 5 pclkc5_0/bdq24 c gnd gndio5 - gndio5 - p7 pb13a 4 pclkt4_0/bdq15 t pb31a 4 pclkt4_0/bdq33 t r8 pb13b 4 pclkc4_0/bdq15 c pb31b 4 pclkc4_0/bdq33 c vccio vccio4 4 vccio4 4 t5 pb14a 4 bdq15 t pb32a 4 bdq33 t t6 pb14b 4 bdq15 c pb32b 4 bdq33 c t8 pb15a 4 bdqs15 t pb33a 4 bdqs33 t gnd gndio4 - gndio4 - r7 pb16a 4 bdq15 t pb34a 4 bdq33 t t9 pb15b 4 bdq15 c pb33b 4 bdq33 c t7 pb16b 4 bdq15 c pb34b 4 bdq33 c l8 pb17a 4 bdq15 t pb35a 4 bdq33 t vccio vccio4 4 vccio4 4 p8 pb18a 4 bdq15 t pb36a 4 bdq33 t l9 pb17b 4 bdq15 c pb35b 4 bdq33 c n8 pb18b 4 bdq15 c pb36b 4 bdq33 c r9 pb19a 4 bdq15 t pb37a 4 bdq33 t gnd gndio4 - gndio4 - r10 pb19b 4 bdq15 c pb37b 4 bdq33 c - - - vccio 4 - - - gndio4 4 n9 pb20a 4 bdq24 t pb47a 4 bdq51 t t10 pb21a 4 bdq24 t pb48a 4 bdq51 t m9 pb20b 4 bdq24 c pb47b 4 bdq51 c r11 pb21b 4 bdq24 c pb48b 4 bdq51 c p10 pb22a 4 bdq24 t pb49a 4 bdq51 t n11 pb23a 4 bdq24 t pb50a 4 bdq51 t vccio vccio4 4 vccio4 4 n10 pb22b 4 bdq24 c pb49b 4 bdq51 c p11 pb23b 4 bdq24 c pb50b 4 bdq51 c t11 pb24a 4 bdqs24 t pb51a 4 bdqs51 t gnd gndio4 - gndio4 - m11 pb25a 4 bdq24 t pb52a 4 bdq51 t t12 pb24b 4 bdq24 c pb51b 4 bdq51 c l11 pb25b 4 bdq24 c pb52b 4 bdq51 c t13 pb26a 4 bdq24 t pb53a 4 bdq51 t r13 pb27a 4 bdq24 t pb54a 4 bdq51 t vccio vccio4 4 vccio4 4 t14 pb26b 4 bdq24 c pb53b 4 bdq51 c p13 pb27b 4 bdq24 c pb54b 4 bdq51 c gnd gndio4 - gndio4 - n12 pb28a 4 vref2_4/bdq24 t pb55a 4 vref2_4/bdq51 t m12 pb28b 4 vref1_4/bdq24 c pb55b 4 vref1_4/bdq51 c r15 cfg2 8 cfg2 8 lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-34 pinout information lattice semiconductor latticeecp2 /m family data sheet n14 cfg1 8 cfg1 8 n13 programn 8 programn 8 n15 cfg0 8 cfg0 8 p15 pr30b 8 writen c pr30b 8 writen c l12 initn 8 initn 8 n16 pr29b 8 csn c pr29b 8 csn c gnd gndio8 - gndio8 - r14 cclk 8 cclk 8 p14 pr30a 8 cs1n t pr30a 8 cs1n t m13 done 8 done 8 r16 pr28b 8 d1 c pr28b 8 d1 c vccio vccio8 8 vccio8 8 m16 pr29a 8 d0/spifastn t pr29a 8 d0/spifastn t p16 pr28a 8 d2 t pr28a 8 d2 t l15 pr27b 8 d3 c pr27b 8 d3 c gnd gndio8 - gndio8 - l14 pr26a 8 d6 t pr26a 8 d6 t l16 pr27a 8 d4 t pr27a 8 d4 t l10 pr25b 8 d7/spid0 c pr25b 8 d7/spid0 c l13 pr26b 8 d5 c pr26b 8 d5 c vccio vccio8 8 vccio8 8 k11 pr25a 8 di/csspi0n t pr25a 8 di/csspi0n t k14 pr24b 8 dout/cson c pr24b 8 dout/cson c k13 pr24a 8 busy/sispi t pr24a 8 busy/sispi t gnd gndio8 - gndio8 - k15 pr21b 3 rlm0_gpllc_fb_a c pr21b 3 rlm0_gpllc_fb_a c vccio vccio3 3 vccio3 3 k16 pr21a 3 rlm0_gpllt_fb_a t pr21a 3 rlm0_gpllt_fb_a t gnd gndio3 - gndio3 - j16 pr20b 3 rlm0_gpllc_in_a** c (lvds)* pr20b 3 rlm0_gpllc_in_a** c (lvds)* j15 pr20a 3 rlm0_gpllt_in_a** t (lvds)* pr20a 3 rlm0_gpllt_in_a** t (lvds)* j14 rlm0_pllcap 3 rlm0_pllcap 3 j13 pr18b 3 rlm0_gdllc_fb_a c pr18b 3 rlm0_gdllc_fb_a c j12 pr18a 3 rlm0_gdllt_fb_a t pr18a 3 rlm0_gdllt_fb_a t h12 pr17b 3 rlm0_gdllc_in_a** c (lvds)* pr17b 3 rlm0_gdllc_in_a** c (lvds)* gnd gndio3 - gndio3 - h13 pr17a 3 rlm0_gdllt_in_a** t (lvds)* pr17a 3 rlm0_gdllt_in_a** t (lvds)* h15 pr16b 3 vref2_3 c pr16b 3 vref2_3 c vccio vccio3 3 vccio3 3 h16 pr16a 3 vref1_3 t pr16a 3 vref1_3 t h11 pr15b 3 pclkc3_0 c (lvds)* pr15b 3 pclkc3_0 c (lvds)* j11 pr15a 3 pclkt3_0 t (lvds)* pr15a 3 pclkt3_0 t (lvds)* g16 pr13b 2 pclkc2_0/rdq10 c pr13b 2 pclkc2_0/rdq10 c gnd gndio2 - gndio2 - g15 pr13a 2 pclkt2_0/rdq10 t pr13a 2 pclkt2_0/rdq10 t lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-35 pinout information lattice semiconductor latticeecp2 /m family data sheet f15 pr11b 2 rdq10 c pr11b 2 rdq10 c g11 pr12b 2 rdq10 c (lvds)* pr12b 2 rdq10 c (lvds)* f14 pr11a 2 rdq10 t pr11a 2 rdq10 t vccio vccio2 2 vccio2 2 f12 pr12a 2 rdq10 t (lvds)* pr12a 2 rdq10 t (lvds)* g14 pr10b 2 rdq10 c (lvds)* pr10b 2 rdq10 c (lvds)* g13 pr10a 2 rdqs10 t (lvds)* pr10a 2 rdqs10 t (lvds)* gnd gndio2 - gndio2 - f16 pr8b 2 rdq10 c (lvds)* pr8b 2 rdq10 c (lvds)* f9 pr9b 2 rdq10 c pr9b 2 rdq10 c e16 pr8a 2 rdq10 t (lvds)* pr8a 2 rdq10 t (lvds)* f10 pr9a 2 rdq10 t pr9a 2 rdq10 t vccio vccio2 2 vccio2 2 d16 pr7b 2 rdq10 c pr7b 2 rdq10 c d15 pr7a 2 rdq10 t pr7a 2 rdq10 t c15 pr4b 2 c (lvds)* pr4b 2 c (lvds)* c16 pr5b 2 c pr5b 2 c gnd gndio2 - gndio2 - d14 pr4a 2 t (lvds)* pr4a 2 t (lvds)* b16 pr5a 2 t pr5a 2 t f13 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2 c (lvds)* vccio vccio2 2 vccio2 2 e13 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2 t (lvds)* f11 pt28b 1 vref2_1 c pt55b 1 vref2_1 c e11 pt28a 1 vref1_1 t pt55a 1 vref1_1 t gnd gndio1 - gndio1 - a15pt27b1 cpt54b1 c e12pt26b1 cpt53b1 c b15pt27a1 tpt54a1 t vccio vccio1 1 vccio1 1 d12pt26a1 tpt53a1 t b14pt25b1 cpt52b1 c c14pt24b1 cpt51b1 c a14pt25a1 tpt52a1 t d13pt24a1 tpt51a1 t c13pt23b1 cpt50b1 c gnd gndio1 - gndio1 - a13pt22b1 cpt49b1 c b13pt23a1 tpt50a1 t vccio vccio1 1 vccio1 1 a12pt22a1 tpt49a1 t b11pt21b1 cpt48b1 c d11pt20b1 cpt47b1 c a11pt21a1 tpt48a1 t c11pt20a1 tpt47a1 t lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-36 pinout information lattice semiconductor latticeecp2 /m family data sheet - - - gndio1 1 - - - vccio 1 d10pt19b1 cpt37b1 c c10pt19a1 tpt37a1 t gnd gndio1 - gndio1 - b10pt18b1 cpt36b1 c a9 pt17b 1 c pt35b 1 c a10pt18a1 tpt36a1 t b9 pt17a 1 t pt35a 1 t vccio vccio1 1 vccio1 1 a8 pt16b 1 c pt34b 1 c d9pt15b1 cpt33b1 c b8 pt16a 1 t pt34a 1 t c9pt15a1 tpt33a1 t gnd gndio1 - gndio1 - b7 pt14b 1 c pt32b 1 c e9 pt13b 1 c pt31b 1 c a7 pt14a 1 t pt32a 1 t d8pt13a1 tpt31a1 t vccio vccio1 1 vccio1 1 a6 pt12b 1 pclkc1_0 c pt30b 1 pclkc1_0 c b6 pt12a 1 pclkt1_0 t pt30a 1 pclkt1_0 t e6 xres - xres 1 f8 pt10b 0 pclkc0_0 c pt28b 0 pclkc0_0 c gnd gndio0 - gndio0 - e8 pt10a 0 pclkt0_0 t pt28a 0 pclkt0_0 t a5 pt9b 0 c pt27b 0 c a3 pt8b 0 c pt26b 0 c a4 pt9a 0 t pt27a 0 t vccio vccio0 0 vccio0 0 b3 pt8a 0 t pt26a 0 t a2 pt7b 0 c pt25b 0 c c7pt6b0 cpt24b0 c b2 pt7a 0 t pt25a 0 t d7pt6a0 tpt24a0 t d6pt5b0 cpt23b0 c gnd gndio0 - gndio0 - f7 pt4b 0 c pt22b 0 c c6pt5a0 tpt23a0 t vccio vccio0 0 vccio0 0 f6 pt4a 0 t pt22a 0 t c4pt3b0 cpt21b0 c b4 pt3a 0 t pt21a 0 t - - - gndio0 0 - - - vccio 0 lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-37 pinout information lattice semiconductor latticeecp2 /m family data sheet d5 pt2b 0 vref2_0 c pt2b 0 vref2_0 c e5 pt2a 0 vref1_0 t pt2a 0 vref1_0 t g7 vcc - vcc - g9 vcc - vcc - h7 vcc - vcc - j10 vcc - vcc - k10 vcc - vcc - k8 vcc - vcc - g8 vccaux - vccaux - h10 vccaux - vccaux - j7 vccaux - vccaux - k9 vccaux - vccaux - c5 vccio0 0 vccio0 0 e7 vccio0 0 vccio0 0 c12 vccio1 1 vccio1 1 e10 vccio1 1 vccio1 1 e14 vccio2 2 vccio2 2 g12 vccio2 2 vccio2 2 k12 vccio3 3 vccio3 3 m14 vccio3 3 vccio3 3 m10 vccio4 4 vccio4 4 p12 vccio4 4 vccio4 4 m7 vccio5 5 vccio5 5 p5 vccio5 5 vccio5 5 k5 vccio6 6 vccio6 6 m3 vccio6 6 vccio6 6 e3 vccio7 7 vccio7 7 g5 vccio7 7 vccio7 7 t15 vccio8 8 vccio8 8 a1 gnd - gnd - a16 gnd - gnd - b12 gnd - gnd - b5 gnd - gnd - c8 gnd - gnd - e15 gnd - gnd - e2 gnd - gnd - h14 gnd - gnd - h8 gnd - gnd - h9 gnd - gnd - j3 gnd - gnd - j8 gnd - gnd - j9 gnd - gnd - m15 gnd - gnd - m2 gnd - gnd - p9 gnd - gnd - lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-38 pinout information lattice semiconductor latticeecp2 /m family data sheet r12 gnd - gnd - r5 gnd - gnd - t1 gnd - gnd - t16 gnd - gnd - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. note: vccio and gnd pads are used to determine the average dc current drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-6e/se and lfe2-12e/se logic sign al connections: 256 fpbga (cont.) lfe2-6e/se lfe2-12e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-39 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-20e/se logic signal connections: 256 fpbga lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential c3 c3 pl2a 7 vref2_7 t (lvds)* c2 c2 pl2b 7 vref1_7 c (lvds)* vccio vccio vccio7 7 - gnd gndio7 7 d3 d3 pl7a 7 ldq8 t d4 d4 pl6a 7 ldq8 t (lvds)* d2 d2 pl7b 7 ldq8 c gnd gnd gndio7 - e4 e4 pl6b 7 ldq8 c (lvds)* b1 b1 pl13a 7 ldq16 t c1 c1 pl13b 7 ldq16 c f5 f5 pl15a 7 ldq16 t vccio vcc vccio 7 f4 f4 pl14a 7 ldq16 t (lvds)* g6 g6 pl15b 7 ldq16 c g4 g4 pl14b 7 ldq16 c (lvds)* d1 d1 pl16a 7 ldqs16 t (lvds)* gnd gnd gndio7 - e1 e1 pl16b 7 ldq16 c (lvds)* f3 f3 pl17a 7 ldq16 t g3 g3 pl17b 7 ldq16 c vccio vccio vccio7 7 f2 f2 pl18a 7 ldq16 t (lvds)* f1 f1 pl18b 7 ldq16 c (lvds)* gnd gnd gndio7 - g2 g2 pl19a 7 pclkt7_0/ldq16 t g1 g1 pl19b 7 pclkc7_0/ldq16 c h6 h6 pl21a 6 pclkt6_0/ldq25 t (lvds)* vccio vccio vccio6 6 h5 h5 pl21b 6 pclkc6_0/ldq25 c (lvds)* h4 h4 pl22a 6 vref2_6/ldq25 t gnd gnd gndio6 - h3 h3 pl22b 6 vref1_6/ldq25 c h2 h2 pl27a 6 llm0_gdllt_in_a**/ldq25 t (lvds)* h1 h1 pl27b 6 llm0_gdllc_in_a**/ldq25 c (lvds)* g10 g10 vcc - j4 j4 pl28a 6 llm0_gdllt_fb_a/ldq25 t j5 j5 pl28b 6 llm0_gdllc_fb_a/ldq25 c j6 j6 llm0_pllcap 6 k4 k4 pl30a 6 llm0_gpllt_in_a**/ldq34 t (lvds)* gnd gnd gndio6 - 4-40 pinout information lattice semiconductor latticeecp2 /m family data sheet j1 j1 pl31a 6 llm0_gpllt_fb_a/ldq34 t k3 k3 pl30b 6 llm0_gpllc_in_a**/ldq34 c (lvds)* vccio vccio vccio6 6 j2 j2 pl31b 6 llm0_gpllc_fb_a/ldq34 c gnd gnd gndio6 - l2 l2 pl38a 6 ldq42 t (lvds)* k2 k2 pl39a 6 ldq42 t l3 l3 pl38b 6 ldq42 c (lvds)* k1 k1 pl39b 6 ldq42 c vccio vccio vccio6 6 l4 l4 pl40a 6 ldq42 t (lvds)* l1 l1 pl41a 6 ldq42 t l5 l5 pl40b 6 ldq42 c (lvds)* m1 m1 pl41b 6 ldq42 c gnd gnd gndio6 - n1 n1 pl43a 6 ldq42 t n2 n2 pl42a 6 ldqs42 t (lvds)* p1 p1 pl43b 6 ldq42 c vccio vccio vccio6 6 p2 p2 pl42b 6 ldq42 c (lvds)* r1 r1 pl44a 6 ldq42 t (lvds)* gnd gnd gndio6 - r2 r2 pl44b 6 ldq42 c (lvds)* n4 n4 tdi - m4 m4 tck - p3 p3 tdo - n3 n3 tms - k7 k7 vccj - m5 m5 pb2a 5 vref2_5/bdq6 t k6 k6 pb3a 5 bdq6 m6 m6 pb2b 5 vref1_5/bdq6 c r3 r3 pb5a 5 bdq6 t p4 p4 pb5b 5 bdq6 c - vcc vccio 5 - gnd gndio5 5 n5 n5 pb30a 5 bdq33 t n6 n6 pb30b 5 bdq33 c t2 t2 pb31a 5 bdq33 t p6 p6 pb32a 5 bdq33 t vccio vccio vccio5 5 t3 t3 pb31b 5 bdq33 c r6 r6 pb32b 5 bdq33 c lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-41 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gnd gndio5 - r4 r4 pb33a 5 bdqs33 t l6 l6 pb34a 5 bdq33 t t4 t4 pb33b 5 bdq33 c l7 l7 pb34b 5 bdq33 c n7 n7 pb35a 5 pclkt5_0/bdq33 t vccio vccio vccio5 5 m8 m8 pb35b 5 pclkc5_0/bdq33 c gnd gnd gndio5 - p7 p7 pb40a 4 pclkt4_0/bdq42 t r8 r8 pb40b 4 pclkc4_0/bdq42 c vccio vccio vccio4 4 t5 t5 pb41a 4 bdq42 t t6 t6 pb41b 4 bdq42 c t8 t8 pb42a 4 bdqs42 t gnd gnd gndio4 - r7 r7 pb43a 4 bdq42 t t9 t9 pb42b 4 bdq42 c t7 t7 pb43b 4 bdq42 c l8 l8 pb44a 4 bdq42 t vccio vccio vccio4 4 p8 p8 pb45a 4 bdq42 t l9 l9 pb44b 4 bdq42 c n8 n8 pb45b 4 bdq42 c r9 r9 pb46a 4 bdq42 t gnd gnd gndio4 - r10 r10 pb46b 4 bdq42 c - vcc vccio 4 - gnd gndio4 4 n9 n9 pb56a 4 bdq60 t t10 t10 pb57a 4 bdq60 t m9 m9 pb56b 4 bdq60 c r11 r11 pb57b 4 bdq60 c p10 p10 pb58a 4 bdq60 t n11 n11 pb59a 4 bdq60 t vccio vccio vccio4 4 n10 n10 pb58b 4 bdq60 c p11 p11 pb59b 4 bdq60 c t11 t11 pb60a 4 bdqs60 t gnd gnd gndio4 - m11 m11 pb61a 4 bdq60 t t12 t12 pb60b 4 bdq60 c lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-42 pinout information lattice semiconductor latticeecp2 /m family data sheet l11 l11 pb61b 4 bdq60 c t13 t13 pb62a 4 bdq60 t r13 r13 pb63a 4 bdq60 t vccio vccio vccio4 4 t14 t14 pb62b 4 bdq60 c p13 p13 pb63b 4 bdq60 c gnd gnd gndio4 - n12 n12 pb64a 4 vref2_4/bdq60 t m12 m12 pb64b 4 vref1_4/bdq60 c r15 r15 cfg2 8 n14 n14 cfg1 8 n13 n13 programn 8 n15 n15 cfg0 8 p15 p15 pr44b 8 writen c l12 l12 initn 8 n16 n16 pr43b 8 csn c gnd gnd gndio8 - r14 r14 cclk 8 p14 p14 pr44a 8 cs1n t m13 m13 done 8 r16 r16 pr42b 8 d1 c vccio vccio vccio8 8 m16 m16 pr43a 8 d0/spifastn t p16 p16 pr42a 8 d2 t l15 l15 pr41b 8 d3 c gnd gnd gndio8 - l14 l14 pr40a 8 d6 t l16 l16 pr41a 8 d4 t l10 l10 pr39b 8 d7/spid0 c l13 l13 pr40b 8 d5 c vccio vccio vccio8 8 k11 k11 pr39a 8 di/csspi0n t k14 k14 pr38b 8 dout/cson c k13 k13 pr38a 8 busy/sispi t gnd gnd gndio8 - k15 k15 pr31b 3 rlm0_gpllc_fb_a/rdq34 c vccio vccio vccio3 3 k16 k16 pr31a 3 rlm0_gpllt_fb_a/rdq34 t gnd gnd gndio3 - j16 j16 pr30b 3 rlm0_gpllc_in_a**/rdq34 c (lvds)* j15 j15 pr30a 3 rlm0_gpllt_in_a**/rdq34 t (lvds)* j14 j14 rlm0_pllcap 3 lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-43 pinout information lattice semiconductor latticeecp2 /m family data sheet j13 j13 pr28b 3 rlm0_gdllc_fb_a/rdq25 c j12 j12 pr28a 3 rlm0_gdllt_fb_a/rdq25 t h12 h12 pr27b 3 rlm0_gdllc_in_a**/rdq25 c (lvds)* gnd gnd gndio3 - h13 h13 pr27a 3 rlm0_gdllt_in_a**/rdq25 t (lvds)* h15 h15 pr22b 3 vref2_3/rdq25 c vccio vccio vccio3 3 h16 h16 pr22a 3 vref1_3/rdq25 t h11 h11 pr21b 3 pclkc3_0/rdq25 c (lvds)* j11 j11 pr21a 3 pclkt3_0/rdq25 t (lvds)* g16 g16 pr19b 2 pclkc2_0/rdq16 c gnd gnd gndio2 - g15 g15 pr19a 2 pclkt2_0/rdq16 t f15 f15 pr17b 2 rdq16 c g11 g11 pr18b 2 rdq16 c (lvds)* f14 f14 pr17a 2 rdq16 t vccio vccio vccio2 2 f12 f12 pr18a 2 rdq16 t (lvds)* g14 g14 pr16b 2 rdq16 c (lvds)* g13 g13 pr16a 2 rdqs16 t (lvds)* gnd gnd gndio2 - f16 f16 pr14b 2 rdq16 c (lvds)* f9 f9 pr15b 2 rdq16 c e16 e16 pr14a 2 rdq16 t (lvds)* f10 f10 pr15a 2 rdq16 t vccio vccio vccio2 2 d16 d16 pr13b 2 rdq16 c d15 d15 pr13a 2 rdq16 t c15 c15 pr6b 2 rdq8 c (lvds)* c16 c16 pr7b 2 rdq8 c gnd gnd gndio2 - d14 d14 pr6a 2 rdq8 t (lvds)* b16 b16 pr7a 2 rdq8 t f13 f13 pr2b 2 vref2_2 c (lvds)* vccio vccio vccio2 2 e13 e13 pr2a 2 vref1_2 t (lvds)* f11 f11 pt64b 1 vref2_1 c e11 e11 pt64a 1 vref1_1 t gnd gnd gndio1 - a15 a15 pt63b 1 c e12 e12 pt62b 1 c b15 b15 pt63a 1 t lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-44 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio vccio1 1 d12 d12 pt62a 1 t b14 b14 pt61b 1 c c14 c14 pt60b 1 c a14 a14 pt61a 1 t d13 d13 pt60a 1 t c13 c13 pt59b 1 c gnd gnd gndio1 - a13 a13 pt58b 1 c b13 b13 pt59a 1 t vccio vccio vccio1 1 a12 a12 pt58a 1 t b11 b11 pt57b 1 c d11 d11 pt56b 1 c a11 a11 pt57a 1 t c11 c11 pt56a 1 t - gnd gndio1 1 - vcc vccio 1 d10 d10 pt46b 1 c c10 c10 pt46a 1 t gnd gnd gndio1 - b10 b10 pt45b 1 c a9 a9 pt44b 1 c a10 a10 pt45a 1 t b9 b9 pt44a 1 t vccio vccio vccio1 1 a8 a8 pt43b 1 c d9 d9 pt42b 1 c b8 b8 pt43a 1 t c9 c9 pt42a 1 t gnd gnd gndio1 - b7 b7 pt41b 1 c e9 e9 pt40b 1 c a7 a7 pt41a 1 t d8 d8 pt40a 1 t vccio vccio vccio1 1 a6 a6 pt39b 1 pclkc1_0 c b6 b6 pt39a 1 pclkt1_0 t e6 e6 xres 1 f8 f8 pt37b 0 pclkc0_0 c gnd gnd gndio0 - e8 e8 pt37a 0 pclkt0_0 t lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-45 pinout information lattice semiconductor latticeecp2 /m family data sheet a5 a5 pt36b 0 c a3 a3 pt35b 0 c a4 a4 pt36a 0 t vccio vccio vccio0 0 b3 b3 pt35a 0 t a2 a2 pt34b 0 c c7 c7 pt33b 0 c b2 b2 pt34a 0 t d7 d7 pt33a 0 t d6 d6 pt32b 0 c gnd gnd gndio0 - f7 f7 pt31b 0 c c6 c6 pt32a 0 t vccio vccio vccio0 0 f6 f6 pt31a 0 t c4 c4 pt30b 0 c b4 b4 pt30a 0 t - gnd gndio0 0 - vcc vccio 0 d5 d5 pt2b 0 vref2_0 c e5 e5 pt2a 0 vref1_0 t g7 g7 vcc - g9 g9 vcc - h7 h7 vcc - j10 j10 vcc - k10 k10 vcc - k8 k8 vcc - g8 g8 vccaux - h10 h10 vccaux - j7 j7 vccaux - k9 k9 vccaux - c5 c5 vccio0 0 e7 e7 vccio0 0 c12 c12 vccio1 1 e10 e10 vccio1 1 e14 e14 vccio2 2 g12 g12 vccio2 2 k12 k12 vccio3 3 m14 m14 vccio3 3 m10 m10 vccio4 4 p12 p12 vccio4 4 m7 m7 vccio5 5 lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-46 pinout information lattice semiconductor latticeecp2 /m family data sheet p5 p5 vccio5 5 k5 k5 vccio6 6 m3 m3 vccio6 6 e3 e3 vccio7 7 g5 g5 vccio7 7 t15 t15 vccio8 8 a1 a1 gnd - a16 a16 gnd - b12 b12 gnd - b5 b5 gnd - c8 c8 gnd - e15 e15 gnd - e2 e2 gnd - h14 h14 gnd - h8 h8 gnd - h9 h9 gnd - j3 j3 gnd - j8 j8 gnd - j9 j9 gnd - m15 m15 gnd - m2 m2 gnd - p9 p9 gnd - r12 r12 gnd - r5 r5 gnd - t1 t1 gnd - t16 t16 gnd - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the s ubstrate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-20e/se logic signal co nnections: 256 fpbga (cont.) lfe2-20e/se ball number ball number ball/pad functi on bank dual function differential 4-47 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential e4 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7 t (lvds)* e5 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7 c (lvds)* - - - gndio7 - e3 nc - pl4a 7 ldq8 t (lvds)* f4 pl3a 7 t pl5a 7 ldq8 t f3 nc - pl4b 7 ldq8 c (lvds)* f5 pl3b 7 c pl5b 7 ldq8 c vccio vccio7 7 vccio7 7 e2 pl4a 7 t (lvds)* pl6a 7 ldq8 t (lvds)* g6 pl5a 7 t pl7a 7 ldq8 t e1 pl4b 7 c (lvds)* pl6b 7 ldq8 c (lvds)* g7 pl5b 7 c pl7b 7 ldq8 c gndio gndio7 - gndio7 - f1 nc - pl9a 7 ldq8 t h4 nc - pl8a 7 ldqs8 t (lvds)* f2 nc - pl9b 7 ldq8 c - - - vccio7 7 h5 nc - pl8b 7 ldq8 c (lvds)* g1 nc - pl11a 7 ldq8 t g3 nc - pl10a 7 ldq8 t (lvds)* g2 nc - pl11b 7 ldq8 c --- gndio- g4 nc - pl10b 7 ldq8 c (lvds)* j4 pl7a 7 ldq10 t pl13a 7 ldq16 t h1 pl6a 7 ldq10 pl12a 7 ldq16 t (lvds)* j5 pl7b 7 ldq10 c pl13b 7 ldq16 c l6 pl9a 7 ldq10 t pl15a 7 ldq16 t vccio vccio7 7 vccio7 7 j2 pl8a 7 ldq10 t (lvds)* pl14a 7 ldq16 t (lvds)* l5 pl9b 7 ldq10 c pl15b 7 ldq16 c j1 pl8b 7 ldq10 c (lvds)* pl14b 7 ldq16 c (lvds)* k3 pl10a 7 ldqs10 t (lvds)* pl16a 7 ldqs16 t (lvds)* gndio gndio7 - gndio - k4 pl10b 7 ldq10 c (lvds)* pl16b 7 ldq16 c (lvds)* k2 pl11a 7 ldq10 t pl17a 7 ldq16 t vccio vccio7 7 vccio7 7 k1 pl11b 7 ldq10 c pl17b 7 ldq16 c l4 pl12a 7 ldq10 t (lvds)* pl18a 7 ldq16 t (lvds)* gndio gndio7 - gndio - l3 pl12b 7 ldq10 c (lvds)* pl18b 7 ldq16 c (lvds)* l2 pl13a 7 pclkt7_0/ldq10 t pl19a 7 pclkt7_0/ldq16 t l1 pl13b 7 pclkc7_0/ldq10 c pl19b 7 pclkc7_0/ldq16 c m5 pl15a 6 pclkt6_0 t (lvds)* pl21a 6 pclkt6_0/ldq25 t (lvds)* vccio vccio6 6 - - m6 pl15b 6 pclkc6_0 c (lvds)* pl21b 6 pclkc6_0/ldq25 c (lvds)* 4-48 pinout information lattice semiconductor latticeecp2 /m family data sheet m3 pl16a 6 vref2_6 t pl22a 6 vref2_6/ldq25 t gndio gndio6 - - - m4 pl16b 6 vref1_6 c pl22b 6 vref1_6/ldq25 c - - - vccio6 6 n1 nc - pl24a 6 ldq25 t m2 nc - pl23a 6 ldq25 t (lvds)* n2 nc - pl24b 6 ldq25 c m1 nc - pl23b 6 ldq25 c (lvds)* --- gndio- n3 nc - pl25a 6 ldqs25 t (lvds)* n5 nc - pl26a 6 ldq25 t n4 nc - pl25b 6 ldq25 c (lvds)* - - - vccio6 6 p5 nc - pl26b 6 ldq25 c p1 pl17a 6 llm0_gdllt_in_a** t (lvds)* pl27a 6 llm0_gdllt_in_a**/ldq25 t (lvds)* p2 pl17b 6 llm0_gdllc_in_a** c (lvds)* pl27b 6 llm0_gdllc_in_a**/ldq25 c (lvds)* p4 pl18a 6 llm0_gdllt_fb_a t pl28a 6 llm0_gdllt_fb_a/ldq25 t --- gndio- r4 pl18b 6 llm0_gdllc_fb_a c pl28b 6 llm0_gdllc_fb_a/ldq25 c p6 llm0_pllcap 6 llm0_pllcap 6 r1 pl20a 6 llm0_gpllt_in_a** t (lvds)* pl30a 6 llm0_gpllt_in_a**/ldq34 t (lvds)* gndio gndio6 - - - r3 pl21a 6 llm0_gpllt_fb_a t pl31a 6 llm0_gpllt_fb_a/ldq34 t r2 pl20b 6 llm0_gpllc_in_a** c (lvds)* pl30b 6 llm0_gpllc_in_a/ldq34 c (lvds)* t4 pl21b 6 llm0_gpllc_fb_a c pl31b 6 llm0_gpllc_fb_a/ldq34 c t5 pl23a 6 t pl33a 6 ldq34 t vccio vccio6 6 vccio6 6 t1 pl22a 6 t (lvds)* pl32a 6 ldq34 t (lvds)* t3 pl23b 6 c pl33b 6 ldq34 c t2 pl22b 6 c (lvds)* pl32b 6 ldq34 c (lvds)* gndio gndio6 - gndio6 - - - - vccio6 6 v1 pl25a 6 ldq28 t pl39a 6 ldq42 t --- gndio- v2 pl25b 6 ldq28 c pl39b 6 ldq42 c u1 pl24a 6 ldq28 t (lvds)* pl38a 6 ldq42 t (lvds)* u3 pl27a 6 ldq28 t pl41a 6 ldq42 t vccio vccio6 6 vccio6 6 u2 pl24b 6 ldq28 c (lvds)* pl38b 6 ldq42 c (lvds)* u4 pl27b 6 ldq28 c pl41b 6 ldq42 c r6 pl26a 6 ldq28 t (lvds)* pl40a 6 ldq42 t (lvds)* r7 pl29a 6 ldq28 t pl43a 6 ldq42 t gndio gndio6 - gndio - t7 pl29b 6 ldq28 c pl43b 6 ldq42 c t6 pl26b 6 ldq28 c (lvds)* pl40b 6 ldq42 c (lvds)* lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-49 pinout information lattice semiconductor latticeecp2 /m family data sheet aa2 pl31a 6 ldq28 t pl45a 6 ldq42 t vccio vccio6 6 vccio6 6 y1 pl28a 6 ldqs28 t (lvds)* pl42a 6 ldqs42 t (lvds)* aa1 pl31b 6 ldq28 c pl45b 6 ldq42 c w1 pl28b 6 ldq28 c (lvds)* pl42b 6 ldq42 c (lvds)* v3 pl30b 6 ldq28 c (lvds)* pl44b 6 ldq42 c (lvds)* gndio gndio6 - gndio - v4 pl30a 6 ldq28 t (lvds)* pl44a 6 ldq42 t (lvds)* u5 tdi - tdi - u7 tck - tck - v6 tdo - tdo - v5 tms - tms - t8 vccj - vccj - w4 pb3a 5 bdq6 t pb3a 5 bdq6 t y3 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t w3 pb3b 5 bdq6 c pb3b 5 bdq6 c y2 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c ab3 pb5a 5 bdq6 t pb5a 5 bdq6 t vccio vccio5 5 vccio5 5 w5 pb4a 5 bdq6 t pb4a 5 bdq6 t ab2 pb5b 5 bdq6 c pb5b 5 bdq6 c w6 pb4b 5 bdq6 c pb4b 5 bdq6 c ab5 pb7a 5 bdq6 t pb7a 5 bdq6 t gndio gndio5 - gndio - y4 pb6a 5 bdqs6 t pb6a 5 bdqs6 t ab4 pb7b 5 bdq6 c pb7b 5 bdq6 c aa3 pb6b 5 bdq6 c pb6b 5 bdq6 c ab6 pb9a 5 bdq6 t pb9a 5 bdq6 t vccio vccio5 5 vccio5 5 aa5 pb8a 5 bdq6 t pb8a 5 bdq6 t aa6 pb9b 5 bdq6 c pb9b 5 bdq6 c y5 pb8b 5 bdq6 c pb8b 5 bdq6 c gndio gndio5 - gndio - - - - vccio5 5 y6 pb12a 5 bdq15 t pb21a 5 bdq24 t w7 pb11a 5 bdq15 t pb20a 5 bdq24 t y7 pb12b 5 bdq15 c pb21b 5 bdq24 c w8 pb11b 5 bdq15 c pb20b 5 bdq24 c u8 pb14a 5 bdq15 t pb23a 5 bdq24 t vccio vccio5 5 vccio5 5 aa7 pb13a 5 bdq15 t pb22a 5 bdq24 t u9 pb14b 5 bdq15 c pb23b 5 bdq24 c ab7 pb13b 5 bdq15 c pb22b 5 bdq24 c y8 pb16a 5 bdq15 t pb25a 5 bdq24 t gndio gndio5 - gndio - lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-50 pinout information lattice semiconductor latticeecp2 /m family data sheet w9 pb15a 5 bdqs15 t pb24a 5 bdqs24 t aa8 pb16b 5 bdq15 c pb25b 5 bdq24 c v9 pb15b 5 bdq15 c pb24b 5 bdq24 c ab8 pb18a 5 bdq15 t pb27a 5 bdq24 t vccio vccio5 5 vccio5 5 w10 pb17a 5 bdq15 t pb26a 5 bdq24 t aa9 pb18b 5 bdq15 c pb27b 5 bdq24 c v10 pb17b 5 bdq15 c pb26b 5 bdq24 c gndio gndio5 - gndio - y10 pb21a 5 bdq24 t pb30a 5 bdq33 t ab9 pb20a 5 bdq24 t pb29a 5 bdq33 t aa10 pb21b 5 bdq24 c pb30b 5 bdq33 c ab10 pb20b 5 bdq24 c pb29b 5 bdq33 c ab11 pb23a 5 bdq24 t pb32a 5 bdq33 t u10 pb22a 5 bdq24 t pb31a 5 bdq33 t vccio vccio5 5 vccio5 5 aa11 pb23b 5 bdq24 c pb32b 5 bdq33 c u11 pb22b 5 bdq24 c pb31b 5 bdq33 c gndio gndio5 - gndio5 - ab12 pb25a 5 bdq24 t pb34a 5 bdq33 t y11 pb24a 5 bdqs24 t pb33a 5 bdqs33 t aa12 pb25b 5 bdq24 c pb34b 5 bdq33 c w11 pb24b 5 bdq24 c pb33b 5 bdq33 c ab13 pb26a 5 pclkt5_0/bdq24 t pb35a 5 pclkt5_0/bdq33 t vccio vccio5 5 vccio5 5 ab14 pb26b 5 pclkc5_0/bdq24 c pb35b 5 pclkc5_0/bdq33 c gndio gndio5 - gndio5 - y12 pb32a 4 bdq33 t pb41a 4 bdq42 t w12 pb32b 4 bdq33 c pb41b 4 bdq42 c vccio vccio4 4 vccio4 4 u12 pb31a 4 pclkt4_0/bdq33 t pb40a 4 pclkt4_0/bdq42 t v12 pb31b 4 pclkc4_0/bdq33 c pb40b 4 pclkc4_0/bdq42 c u13 pb34a 4 bdq33 t pb43a 4 bdq42 t gndio gndio4 - gndio4 - aa13 pb33a 4 bdqs33 t pb42a 4 bdqs42 t u14 pb34b 4 bdq33 c pb43b 4 bdq42 c y13 pb33b 4 bdq33 c pb42b 4 bdq42 c ab16 pb36a 4 bdq33 t pb45a 4 bdq42 t vccio vccio4 4 vccio4 4 ab15 pb35a 4 bdq33 t pb44a 4 bdq42 t ab17 pb36b 4 bdq33 c pb45b 4 bdq42 c aa14 pb35b 4 bdq33 c pb44b 4 bdq42 c w13 pb37a 4 bdq33 t pb46a 4 bdq42 t gndio gndio4 - gndio4 - w14 pb37b 4 bdq33 c pb46b 4 bdq42 c lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-51 pinout information lattice semiconductor latticeecp2 /m family data sheet ab18 pb39a 4 bdq42 t pb48a 4 bdq51 t ab19 pb39b 4 bdq42 c pb48b 4 bdq51 c y15 pb41a 4 bdq42 t pb50a 4 bdq51 t v14 pb40a 4 bdq42 t pb49a 4 bdq51 t vccio vccio4 4 vccio4 4 aa15 pb41b 4 bdq42 c pb50b 4 bdq51 c w15 pb40b 4 bdq42 c pb49b 4 bdq51 c gndio gndio4 - gndio - ab20 pb43a 4 bdq42 t pb52a 4 bdq51 t aa16 pb42a 4 bdqs42 t pb51a 4 bdqs51 t ab21 pb43b 4 bdq42 c pb52b 4 bdq51 c aa17 pb42b 4 bdq42 c pb51b 4 bdq51 c y16 pb45a 4 bdq42 t pb54a 4 bdq51 t u15 pb44a 4 bdq42 t pb53a 4 bdq51 t vccio vccio4 4 vccio4 4 w16 pb45b 4 bdq42 c pb54b 4 bdq51 c u16 pb44b 4 bdq42 c pb53b 4 bdq51 c aa18 pb46a 4 bdq42 t pb55a 4 bdq51 t aa20 pb46b 4 bdq42 c pb55b 4 bdq51 c gndio gndio4 - gndio - v16 pb49a 4 bdq51 t pb58a 4 bdq60 t v17 pb49b 4 bdq51 c pb58b 4 bdq60 c aa21 pb48a 4 bdq51 t pb57a 4 bdq60 t vccio vccio4 4 vccio4 4 y19 pb51a 4 bdqs51 t pb60a 4 bdqs60 t aa22 pb48b 4 bdq51 c pb57b 4 bdq60 c y20 pb51b 4 bdq51 c pb60b 4 bdq60 c y18 pb50a 4 bdq51 t pb59a 4 bdq60 t gndio gndio4 - gndio4 - y21 pb53a 4 bdq51 t pb62a 4 bdq60 t y17 pb50b 4 bdq51 c pb59b 4 bdq60 c y22 pb53b 4 bdq51 c pb62b 4 bdq60 c w17 pb52a 4 bdq51 t pb61a 4 bdq60 t vccio vccio4 4 vccio4 4 u18 pb54a 4 bdq51 t pb63a 4 bdq60 t w18 pb52b 4 bdq51 c pb61b 4 bdq60 c v18 pb54b 4 bdq51 c pb63b 4 bdq60 c gndio gndio4 - gndio4 - t15 pb55a 4 vref2_4/bdq51 t pb64a 4 vref2_4/bdq60 t t16 pb55b 4 vref1_4/bdq51 c pb64b 4 vref1_4/bdq60 c w19 cfg2 8 cfg2 8 v19 cfg1 8 cfg1 8 v20 programn 8 programn 8 w20 cfg0 8 cfg0 8 u22 pr28b 8 d1 c pr42b 8 d1 c lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-52 pinout information lattice semiconductor latticeecp2 /m family data sheet v22 initn 8 initn 8 r16 pr30b 8 writen c pr44b 8 writen c gndio gndio8 - gndio8 - w22 cclk 8 cclk 8 r17 pr30a 8 cs1n t pr44a 8 cs1n t v21 done 8 done 8 vccio vccio8 8 vccio8 8 u19 pr29b 8 csn c pr43b 8 csn c t17 pr26b 8 d5 c pr40b 8 d5 c u20 pr29a 8 d0/spifastn t pr43a 8 d0/spifastn t u21 pr28a 8 d2 t pr42a 8 d2 t gndio gndio8 - gndio8 - t18 pr26a 8 d6 t pr40a 8 d6 t t20 pr27b 8 d3 c pr41b 8 d3 c t21 pr25b 8 d7/spid0 c pr39b 8 d7/spid0 c t19 pr27a 8 d4 t pr41a 8 d4 t vccio vccio8 8 vccio8 8 t22 pr25a 8 di/csspi0n t pr39a 8 di/csspi0n t r18 pr24b 8 dout/cson c pr38b 8 dout/cson c r19 pr24a 8 busy/sispi t pr38a 8 busy/sispi t - - - vccio3 3 gndio gndio3 - gndio3 - p18 pr22b 3 c (lvds)* pr32b 3 rdq34 c (lvds)* r22 pr23b 3 c pr33b 3 rdq34 c p19 pr22a 3 t (lvds)* pr32a 3 rdq34 t (lvds)* r21 pr23a 3 t pr33a 3 rdq34 t vccio vccio3 3 vccio3 3 r20 pr21b 3 rlm0_gpllc_fb_a c pr31b 3 rlm0_gpllc_fb_a/rdq34 c p22 pr21a 3 rlm0_gpllt_fb_a t pr31a 3 rlm0_gpllt_fb_a/rdq34 t p21 pr20b 3 rlm0_gpllc_in_a** c (lvds)* pr30b 3 rlm0_gpllc_in_a**/rdq34 c (lvds)* n21 pr20a 3 rlm0_gpllt_in_a** t (lvds)* pr30a 3 rlm0_gpllt_in_a**/rdq34 t (lvds)* n17 rlm0_pllcap 3 rlm0_pllcap 3 n22 pr18b 3 rlm0_gdllc_fb_a c pr28b 3 rlm0_gdllc_fb_a/rdq25 c m22 pr17b 3 rlm0_gdllc_in_a** c (lvds)* pr27b 3 rlm0_gdllc_in_a**/rdq25 c (lvds)* gndio gndio3 - gndio3 - n20 pr18a 3 rlm0_gdllt_fb_a t pr28a 3 rlm0_gdllt_fb_a/rdq25 t m21 pr17a 3 rlm0_gdllt_in_a** t (lvds)* pr27a 3 rlm0_gdllt_in_a**/rdq25 t (lvds)* n19 nc - pr26b 3 rdq25 c - - - vccio3 3 m19 nc - pr26a 3 rdq25 t j22 nc - pr23b 3 rdq25 c (lvds)* --- gndio- l22 nc - pr24b 3 rdq25 c h22 nc - pr23a 3 rdq25 t (lvds)* k22 nc - pr24a 3 rdq25 t lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-53 pinout information lattice semiconductor latticeecp2 /m family data sheet m20 pr16b 3 vref2_3 c pr22b 3 vref2_3/rdq25 c vccio vccio3 3 vccio3 3 l21 pr16a 3 vref1_3 t pr22a 3 vref1_3/rdq25 t k21 pr15b 3 pclkc3_0 c (lvds)* pr21b 3 pclkc3_0/rdq25 c (lvds)* j21 pr15a 3 pclkt3_0 t (lvds)* pr21a 3 pclkt3_0/rdq25 t (lvds)* m18 pr13b 2 pclkc2_0/rdq10 c pr19b 2 pclkc2_0/rdq16 c gndio gndio2 - gndio2 - l17 pr13a 2 pclkt2_0/rdq10 t pr19a 2 pclkt2_0/rdq16 t l19 pr12b 2 rdq10 c (lvds)* pr18b 2 rdq16 c (lvds)* k18 pr10b 2 rdq10 c (lvds)* pr16b 2 rdq16 c (lvds)* l20 pr12a 2 rdq10 t (lvds)* pr18a 2 rdq16 t (lvds)* vccio vccio2 2 vccio2 2 k19 pr10a 2 rdqs10 t (lvds)* pr16a 2 rdqs16 t (lvds)* l18 pr11b 2 rdq10 c pr17b 2 rdq16 c k17 pr11a 2 rdq10 t pr17a 2 rdq16 t gndio gndio2 - gndio2 - j17 pr8b 2 rdq10 c (lvds)* pr14b 2 rdq16 c (lvds)* g22 pr9b 2 rdq10 c pr15b 2 rdq16 c j18 pr8a 2 rdq10 t (lvds)* pr14a 2 rdq16 t (lvds)* f22 pr9a 2 rdq10 t pr15a 2 rdq16 t vccio vccio2 2 vccio2 2 h21 pr6b 2 rdq10 c (lvds)* pr12b 2 rdq16 c (lvds)* k20 pr7b 2 rdq10 c pr13b 2 rdq16 c g21 pr6a 2 rdq10 t (lvds)* pr12a 2 rdq16 t (lvds)* j19 pr7a 2 rdq10 t pr13a 2 rdq16 t d22 nc - pr10b 2 rdq8 c (lvds)* f21 nc - pr11b 2 rdq8 c --- gndio- e21 nc - pr10a 2 rdq8 t (lvds)* e22 nc - pr11a 2 rdq8 t h19 nc - pr8b 2 rdq8 c (lvds)* g20 nc - pr9b 2 rdq8 c - - - vccio2 2 g19 nc - pr8a 2 rdqs8 t (lvds)* f20 nc - pr9a 2 rdq8 t g17 pr5b 2 c pr7b 2 rdq8 c gndio gndio2 - gndio2 - e20 pr4b 2 c (lvds)* pr6b 2 rdq8 c (lvds)* f19 pr5a 2 t pr7a 2 rdq8 t d20 pr4a 2 t (lvds)* pr6a 2 rdq8 t (lvds)* f18 pr3b 2 c pr5b 2 rdq8 c vccio vccio2 2 vccio2 2 c21 nc - pr4b 2 rdq8 c (lvds)* f16 pr3a 2 t pr5a 2 rdq8 t c22 nc - pr4a 2 rdq8 t (lvds)* lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-54 pinout information lattice semiconductor latticeecp2 /m family data sheet --- gndio- d19 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2 c (lvds)* e19 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2 t (lvds)* b21 pt55b 1 vref2_1 c pt64b 1 vref2_1 c b22 pt55a 1 vref1_1 t pt64a 1 vref1_1 t gndio gndio1 - gndio1 - d18 pt53b 1 c pt62b 1 c c20 pt54b 1 c pt63b 1 c e18 pt53a 1 t pt62a 1 t c19 pt54a 1 t pt63a 1 t vccio vccio1 1 vccio1 1 d17 pt51b 1 c pt60b 1 c b20 pt52b 1 c pt61b 1 c c18 pt51a 1 t pt60a 1 t a19 pt52a 1 t pt61a 1 t gndio gndio1 - gndio1 - a18 pt49b 1 c pt58b 1 c a21 pt50b 1 c pt59b 1 c b18 pt49a 1 t pt58a 1 t a20 pt50a 1 t pt59a 1 t vccio vccio1 1 vccio1 1 d16 pt47b 1 c pt56b 1 c g16 pt48b 1 c pt57b 1 c e16 pt47a 1 t pt56a 1 t g15 pt48a 1 t pt57a 1 t c17 pt46b 1 c pt55b 1 c gndio gndio1 - gndio1 - c16 pt46a 1 t pt55a 1 t a17 pt44b 1 c pt53b 1 c b17 pt45b 1 c pt54b 1 c a16 pt44a 1 t pt53a 1 t vccio vccio1 1 vccio1 1 b16 pt45a 1 t pt54a 1 t e15 pt42b 1 c pt51b 1 c c15 pt43b 1 c pt52b 1 c f15 pt42a 1 t pt51a 1 t d15 pt43a 1 t pt52a 1 t b15 pt40b 1 c pt49b 1 c gndio gndio1 - gndio1 - a15 pt40a 1 t pt49a 1 t vccio vccio1 1 vccio1 1 a14 pt39a 1 t pt48a 1 t b14 pt39b 1 c pt48b 1 c d14 pt37b 1 c pt46b 1 c e14 pt36b 1 c pt45b 1 c lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-55 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio1 - gndio1 - c13 pt37a 1 t pt46a 1 t f14 pt36a 1 t pt45a 1 t a13 pt35b 1 c pt44b 1 c e13 pt34b 1 c pt43b 1 c vccio vccio1 1 vccio1 1 b13 pt35a 1 t pt44a 1 t d13 pt34a 1 t pt43a 1 t e12 pt33b 1 c pt42b 1 c gndio gndio1 - gndio1 - d12 pt33a 1 t pt42a 1 t a12 pt31b 1 c pt40b 1 c b12 pt30b 1 pclkc1_0 c pt39b 1 pclkc1_0 c vccio vccio1 1 vccio1 1 a11 pt31a 1 t pt40a 1 t c12 pt30a 1 pclkt1_0 t pt39a 1 pclkt1_0 t f12 xres 1 xres 1 b10 pt28b 0 pclkc0_0 c pt37b 0 pclkc0_0 c gndio gndio0 - gndio0 - b11 pt28a 0 pclkt0_0 t pt37a 0 pclkt0_0 t c11 pt26b 0 c pt35b 0 c a10 pt27b 0 c pt36b 0 c c10 pt26a 0 t pt35a 0 t vccio vccio0 0 vccio0 0 a9 pt27a 0 t pt36a 0 t a8 pt24b 0 c pt33b 0 c e11 pt25b 0 c pt34b 0 c a7 pt24a 0 t pt33a 0 t f11 pt25a 0 t pt34a 0 t gndio gndio0 - gndio0 - b8 pt23b 0 c pt32b 0 c vccio vccio0 0 vccio0 0 b9 pt23a 0 t pt32a 0 t c8 pt20b 0 c pt29b 0 c b7 pt21b 0 c pt30b 0 c d8 pt20a 0 t pt29a 0 t a6 pt21a 0 t pt30a 0 t gndio gndio0 - gndio0 - c7 pt17b 0 c pt26b 0 c d10 pt18b 0 c pt27b 0 c c6 pt17a 0 t pt26a 0 t e10 pt18a 0 t pt27a 0 t vccio vccio0 0 vccio0 0 f10 pt15b 0 c pt24b 0 c b6 pt16b 0 c pt25b 0 c lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-56 pinout information lattice semiconductor latticeecp2 /m family data sheet d9 pt15a 0 t pt24a 0 t b5 pt16a 0 t pt25a 0 t gndio gndio0 - gndio0 - a5 pt13b 0 c pt22b 0 c f9 pt14b 0 c pt23b 0 c a4 pt13a 0 t pt22a 0 t e9 pt14a 0 t pt23a 0 t vccio vccio0 0 vccio0 0 g8 pt11b 0 c pt20b 0 c a3 pt12b 0 c pt21b 0 c e8 pt11a 0 t pt20a 0 t a2 pt12a 0 t pt21a 0 t gndio gndio0 - gndio0 - - - - vccio0 0 c3 pt10b 0 c pt10b 0 c b3 pt10a 0 t pt10a 0 t - - - gndio0 - e7 pt8b 0 c pt8b 0 c f8 pt9b 0 c pt9b 0 c f7 pt8a 0 t pt8a 0 t d7 pt9a 0 t pt9a 0 t vccio vccio0 0 vccio0 0 d4 pt6b 0 c pt6b 0 c d5 pt7b 0 c pt7b 0 c c4 pt6a 0 t pt6a 0 t d6 pt7a 0 t pt7a 0 t gndio gndio0 - gndio - j7 pt4b 0 c pt4b 0 c b2 pt5b 0 c pt5b 0 c h7 pt4a 0 t pt4a 0 t b1 pt5a 0 t pt5a 0 t vccio vccio0 0 vccio0 0 d1 pt2b 0 vref2_0 c pt2b 0 vref2_0 c d3 pt3b 0 c pt3b 0 c c1 pt2a 0 vref1_0 t pt2a 0 vref1_0 t c2 pt3a 0 t pt3a 0 t j10 vcc - vcc - j11 vcc - vcc - j12 vcc - vcc - j13 vcc - vcc - k14 vcc - vcc - k9 vcc - vcc - l14 vcc - vcc - l9 vcc - vcc - m14 vcc - vcc - lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-57 pinout information lattice semiconductor latticeecp2 /m family data sheet m9 vcc - vcc - n14 vcc - vcc - n9 vcc - vcc - p10 vcc - vcc - p11 vcc - vcc - p12 vcc - vcc - p13 vcc - vcc - g10 vccio0 0 vccio0 0 g9 vccio0 0 vccio0 0 h9 vccio0 0 vccio0 0 h8 vccio0 0 vccio0 0 g11 vccio1 1 vccio1 1 g12 vccio1 1 vccio1 1 g13 vccio1 1 vccio1 1 g14 vccio1 1 vccio1 1 h14 vccio2 2 vccio2 2 h15 vccio2 2 vccio2 2 j15 vccio2 2 vccio2 2 k16 vccio2 2 vccio2 2 l16 vccio3 3 vccio3 3 m16 vccio3 3 vccio3 3 n16 vccio3 3 vccio3 3 p16 vccio3 3 vccio3 3 r14 vccio4 4 vccio4 4 t12 vccio4 4 vccio4 4 t13 vccio4 4 vccio4 4 t14 vccio4 4 vccio4 4 r9 vccio5 5 vccio5 5 t10 vccio5 5 vccio5 5 t11 vccio5 5 vccio5 5 t9 vccio5 5 vccio5 5 n7 vccio6 6 vccio6 6 p7 vccio6 6 vccio6 6 p8 vccio6 6 vccio6 6 r8 vccio6 6 vccio6 6 j8 vccio7 7 vccio7 7 k7 vccio7 7 vccio7 7 l7 vccio7 7 vccio7 7 m7 vccio7 7 vccio7 7 p15 vccio8 8 vccio8 8 r15 vccio8 8 vccio8 8 c5 vccaux - vccaux - d11 vccaux - vccaux - e17 vccaux - vccaux - e6 vccaux - vccaux - lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-58 pinout information lattice semiconductor latticeecp2 /m family data sheet f13 vccaux - vccaux - g18 vccaux - vccaux - g5 vccaux - vccaux - k5 vccaux - vccaux - m17 vccaux - vccaux - p17 vccaux - vccaux - r5 vccaux - vccaux - v11 vccaux - vccaux - v13 vccaux - vccaux - v15 vccaux - vccaux - v7 vccaux - vccaux - v8 vccaux - vccaux - a1 gnd - gnd - a22 gnd - gnd - aa19 gnd - gnd - aa4 gnd - gnd - ab1 gnd - gnd - ab22 gnd - gnd - b19 gnd - gnd - b4 gnd - gnd - c14 gnd - gnd - c9 gnd - gnd - d2 gnd - gnd - d21 gnd - gnd - f17 gnd - gnd - f6 gnd - gnd - h10 gnd - gnd - h11 gnd - gnd - h12 gnd - gnd - h13 gnd - gnd - j14 gnd - gnd - j20 gnd - gnd - j3 gnd - gnd - j9 gnd - gnd - k10 gnd - gnd - k11 gnd - gnd - k12 gnd - gnd - k13 gnd - gnd - k15 gnd - gnd - k8 gnd - gnd - l10 gnd - gnd - l11 gnd - gnd - l12 gnd - gnd - l13 gnd - gnd - l15 gnd - gnd - lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-59 pinout information lattice semiconductor latticeecp2 /m family data sheet l8 gnd - gnd - m10 gnd - gnd - m11 gnd - gnd - m12 gnd - gnd - m13 gnd - gnd - m15 gnd - gnd - m8 gnd - gnd - n10 gnd - gnd - n11 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n15 gnd - gnd - n8 gnd - gnd - p14 gnd - gnd - p20 gnd - gnd - p3 gnd - gnd - p9 gnd - gnd - r10 gnd - gnd - r11 gnd - gnd - r12 gnd - gnd - r13 gnd - gnd - u17 gnd - gnd - u6 gnd - gnd - w2 gnd - gnd - w21 gnd - gnd - y14 gnd - gnd - y9 gnd - gnd - h6 nc - nc - j6 nc - nc - h3 nc - nc - h2 nc - nc - h17 nc - nc - h16 nc - nc - h20 nc - nc - h18 nc - nc - k6 nc - nc - j16 nc - nc - n18 vcc - vcc - n6 vcc - vcc - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between g nd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-12e/se and lfe2- 20e/se logic signal co nnections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-60 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential e4 pl2a 7 vref2_7/ldq6 t (lvds)* pl2a 7 vref2_7 t (lvds)* e5 pl2b 7 vref1_7/ldq6 c (lvds)* pl2b 7 vref1_7 c (lvds)* vccio vccio7 - gndio7 - gndio gndio7 - vccio 7 e3 pl10a 7 ldq14 t (lvds)* pl12a 7 ldq16 t (lvds)* f3 pl10b 7 ldq14 c (lvds)* pl12b 7 ldq16 c (lvds)* f4 pl11a 7 ldq14 t pl13a 7 ldq16 t f5 pl11b 7 ldq14 c pl13b 7 ldq16 c e2 pl12a 7 ldq14 t (lvds)* pl14a 7 ldq16 t (lvds)* vccio vccio7 7 vccio 7 e1 pl12b 7 ldq14 c (lvds)* pl14b 7 ldq16 c (lvds)* g6 pl13a 7 ldq14 t pl15a 7 ldq16 t g7 pl13b 7 ldq14 c pl15b 7 ldq16 c h4 pl14a 7 ldqs14 t (lvds)* pl16a 7 ldqs16 t (lvds)* gndio gndio7 - gndio7 - h5 pl14b 7 ldq14 c (lvds)* pl16b 7 ldq16 c (lvds)* f1 pl15a 7 ldq14 t pl17a 7 ldq16 t f2 pl15b 7 ldq14 c pl17b 7 ldq16 c vccio vccio7 7 vccio 7 g3 pl16a 7 ldq14 t (lvds)* pl18a 7 ldq16 t (lvds)* g4 pl16b 7 ldq14 c (lvds)* pl18b 7 ldq16 c (lvds)* g1 pl17a 7 ldq14 t pl19a 7 ldq16 t g2 pl17b 7 ldq14 c pl19b 7 ldq16 c gndio gndio7 - gndio7 - - - - vccio 7 h6 nc - pl25a 7 lum0_spllt_in_a/ldq24 t - - - vccio 7 j6 nc - pl25b 7 lum0_spllc_in_a/ldq24 c h3 nc - pl26a 7 lum0_spllt_fb_a/ldq24 t h2 nc - pl26b 7 lum0_spllc_fb_a/ldq24 c - - - gndio7 - - - - vccio 7 h1 pl18a 7 ldq22 pl37a 7 ldq41 j4 pl19a 7 ldq22 t pl38a 7 ldq41 t j5 pl19b 7 ldq22 c pl38b 7 ldq41 c vccio vccio7 7 vccio 7 j2 pl20a 7 ldq22 t (lvds)* pl39a 7 ldq41 t (lvds)* j1 pl20b 7 ldq22 c (lvds)* pl39b 7 ldq41 c (lvds)* l6 pl21a 7 ldq22 t pl40a 7 ldq41 t l5 pl21b 7 ldq22 c pl40b 7 ldq41 c gndio gndio7 - gndio7 - k3 pl22a 7 ldqs22 t (lvds)* pl41a 7 ldqs41 t (lvds)* k4 pl22b 7 ldq22 c (lvds)* pl41b 7 ldq41 c (lvds)* k2 pl23a 7 ldq22 t pl42a 7 ldq41 t vccio vccio7 7 vccio 7 k1 pl23b 7 ldq22 c pl42b 7 ldq41 c l4 pl24a 7 ldq22 t (lvds)* pl43a 7 ldq41 t (lvds)* 4-61 pinout information lattice semiconductor latticeecp2 /m family data sheet l3 pl24b 7 ldq22 c (lvds)* pl43b 7 ldq41 c (lvds)* l2 pl25a 7 pclkt7_0/ldq22 t pl44a 7 pclkt7_0/ldq41 t gndio gndio7 - gndio7 - l1 pl25b 7 pclkc7_0/ldq22 c pl44b 7 pclkc7_0/ldq41 c m5 pl27a 6 pclkt6_0/ldq31 t (lvds)* pl46a 6 pclkt6_0/ldq50 t (lvds)* m6 pl27b 6 pclkc6_0/ldq31 c (lvds)* pl46b 6 pclkc6_0/ldq50 c (lvds)* m3 pl28a 6 vref2_6/ldq31 t pl47a 6 vref2_6/ldq50 t m4 pl28b 6 vref1_6/ldq31 c pl47b 6 vref1_6/ldq50 c m2 pl29a 6 ldq31 t (lvds)* pl48a 6 ldq50 t (lvds)* vccio vccio6 6 vccio 6 m1 pl29b 6 ldq31 c (lvds)* pl48b 6 ldq50 c (lvds)* n1 pl30a 6 ldq31 t pl49a 6 ldq50 t n2 pl30b 6 ldq31 c pl49b 6 ldq50 c gndio gndio6 - gndio6 - vccio vccio6 6 vccio 6 n3 pl39a 6 ldqs39*** t (lvds)* pl58a 6 ldqs58*** t (lvds)* n4 pl39b 6 ldq39 c (lvds)* pl58b 6 ldq58 c (lvds)* n5 pl40a 6 ldq39 t pl59a 6 ldq58 t vccio vccio6 6 vccio 6 p5 pl40b 6 ldq39 c pl59b 6 ldq58 c p1 pl41a 6 llm0_gdllt_in_a**/ldq39 t (lvds)* pl60a 6 llm0_gdllt_in_a**/ldq58 t (lvds)* p2 pl41b 6 llm0_gdllc_in_a**/ldq39 c (lvds)* pl60b 6 llm0_gdllc_in_a**/ldq58 c (lvds)* p4 pl42a 6 llm0_gdllt_fb_a/ldq39 t pl61a 6 llm0_gdllt_fb_a/ldq58 t gndio gndio6 - gndio6 - r4 pl42b 6 llm0_gdllc_fb_a/ldq39 c pl61b 6 llm0_gdllc_fb_d/ldq58 c p6 llm0_pllcap 6 llm0_pllcap 6 r1 pl44a 6 llm0_gpllt_in_a**/ldq48 t (lvds) * pl63a 6 llm0_gpllt_in_a**/ldq67 t (lvds)* r2 pl44b 6 llm0_gpllc_in_a**/ldq48 c (lvds)* pl63b 6 llm0_gpllc_in_a**/ldq67 c (lvds)* r3 pl45a 6 llm0_gpllt_fb_a/ldq48 t pl64a 6 llm0_gpllt_fb_a/ldq67 t t4 pl45b 6 llm0_gpllc_fb_a/ldq48 c pl64b 6 llm0_gpllc_fb_a/ldq67 c t1 pl46a 6 ldq48 t (lvds)* pl65a 6 ldq67 t (lvds)* vccio vccio6 6 vccio 6 t2 pl46b 6 ldq48 c (lvds)* pl65b 6 ldq67 c (lvds)* t5 pl47a 6 ldq48 t pl66a 6 ldq67 t t3 pl47b 6 ldq48 c pl66b 6 ldq67 c gndio gndio6 - vccio 6 vccio vccio6 - gndio6 - u1 pl52a 6 ldq56 t (lvds)* pl71a 6 ldq75 t (lvds)* u2 pl52b 6 ldq56 c (lvds)* pl71b 6 ldq75 c (lvds)* v1 pl53a 6 ldq56 t pl72a 6 ldq75 t v2 pl53b 6 ldq56 c pl72b 6 ldq75 c vccio vccio6 6 vccio 6 r6 pl54a 6 ldq56 t (lvds)* pl73a 6 ldq75 t (lvds)* t6 pl54b 6 ldq56 c (lvds)* pl73b 6 ldq75 c (lvds)* u3 pl55a 6 ldq56 t pl74a 6 ldq75 t u4 pl55b 6 ldq56 c pl74b 6 ldq75 c gndio gndio6 - gndio6 - lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-62 pinout information lattice semiconductor latticeecp2 /m family data sheet y1 pl56a 6 ldqs56 t (lvds)* pl75a 6 ldqs75 t (lvds)* w1 pl56b 6 ldq56 c (lvds)* pl75b 6 ldq75 c (lvds)* r7 pl57a 6 ldq56 t pl76a 6 ldq75 t vccio vccio6 6 vccio 6 t7 pl57b 6 ldq56 c pl76b 6 ldq75 c v4 pl58a 6 ldq56 t (lvds)* pl77a 6 ldq75 t (lvds)* v3 pl58b 6 ldq56 c (lvds)* pl77b 6 ldq75 c (lvds)* aa2 pl59a 6 ldq56 t pl78a 6 ldq75 t gndio gndio6 - gndio6 - aa1 pl59b 6 ldq56 c pl78b 6 ldq75 c u7 tck- tck- u5 tdi- tdi- v5 tms - tms - v6 tdo - tdo - t8 vccj - vccj - y3 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t y2 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c w4 pb3a 5 bdq6 t pb3a 5 bdq6 t w3 pb3b 5 bdq6 c pb3b 5 bdq6 c w5 pb4a 5 bdq6 t pb4a 5 bdq6 t w6 pb4b 5 bdq6 c pb4b 5 bdq6 c vccio vccio5 5 vccio 5 ab3 pb5a 5 bdq6 t pb5a 5 bdq6 t ab2 pb5b 5 bdq6 c pb5b 5 bdq6 c gndio gndio5 - gndio5 - y4 pb6a 5 bdqs6 t pb6a 5 bdqs6 t aa3 pb6b 5 bdq6 c pb6b 5 bdq6 c ab5 pb7a 5 bdq6 t pb7a 5 bdq6 t ab4 pb7b 5 bdq6 c pb7b 5 bdq6 c aa5 pb8a 5 bdq6 t pb8a 5 bdq6 t y5 pb8b 5 bdq6 c pb8b 5 bdq6 c vccio vccio5 5 vccio 5 ab6 pb9a 5 bdq6 t pb9a 5 bdq6 t aa6 pb9b 5 bdq6 c pb9b 5 bdq6 c gndio gndio5 - gndio5 - vccio vccio5 5 vccio 5 w7 pb20a 5 bdq24 t pb29a 5 bdq33 t w8 pb20b 5 bdq24 c pb29b 5 bdq33 c y6 pb21a 5 bdq24 t pb30a 5 bdq33 t y7 pb21b 5 bdq24 c pb30b 5 bdq33 c aa7 pb22a 5 bdq24 t pb31a 5 bdq33 t vccio vccio5 5 vccio 5 ab7 pb22b 5 bdq24 c pb31b 5 bdq33 c u8 pb23a 5 bdq24 t pb32a 5 bdq33 t u9 pb23b 5 bdq24 c pb32b 5 bdq33 c w9 pb24a 5 bdqs24 t pb33a 5 bdqs33 t gndio gndio5 - gndio5 - lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-63 pinout information lattice semiconductor latticeecp2 /m family data sheet v9 pb24b 5 bdq24 c pb33b 5 bdq33 c y8 pb25a 5 bdq24 t pb34a 5 bdq33 t aa8 pb25b 5 bdq24 c pb34b 5 bdq33 c w10 pb26a 5 bdq24 t pb35a 5 bdq33 t vccio vccio5 5 vccio 5 v10 pb26b 5 bdq24 c pb35b 5 bdq33 c ab8 pb27a 5 bdq24 t pb36a 5 bdq33 t aa9 pb27b 5 bdq24 c pb36b 5 bdq33 c gndio gndio5 - gndio5 - ab9 pb29a 5 bdq33 t pb38a 5 bdq42 t ab10 pb29b 5 bdq33 c pb38b 5 bdq42 c y10 pb30a 5 bdq33 t pb39a 5 bdq42 t aa10 pb30b 5 bdq33 c pb39b 5 bdq42 c u10 pb31a 5 bdq33 t pb40a 5 bdq42 t u11 pb31b 5 bdq33 c pb40b 5 bdq42 c vccio vccio5 5 vccio 5 ab11 pb32a 5 bdq33 t pb41a 5 bdq42 t aa11 pb32b 5 bdq33 c pb41b 5 bdq42 c gndio gndio5 - gndio5 - y11 pb33a 5 bdqs33 t pb42a 5 bdqs42 t w11 pb33b 5 bdq33 c pb42b 5 bdq42 c ab12 pb34a 5 bdq33 t pb43a 5 bdq42 t aa12 pb34b 5 bdq33 c pb43b 5 bdq42 c ab13 pb35a 5 pclkt5_0/bdq33 t pb44a 5 pclkt5_0/bdq42 t ab14 pb35b 5 pclkc5_0/bdq33 c pb44b 5 pclkc5_0/bdq42 c vccio vccio5 5 vccio 5 gndio gndio5 - gndio5 - u12 pb40a 4 pclkt4_0/bdq42 t pb49a 4 pclkt4_0/bdq51 t vccio vccio4 4 vccio 4 v12 pb40b 4 pclkc4_0/bdq42 c pb49b 4 pclkc4_0/bdq51 c y12 pb41a 4 bdq42 t pb50a 4 bdq51 t w12 pb41b 4 bdq42 c pb50b 4 bdq51 c aa13 pb42a 4 bdqs42 t pb51a 4 bdqs51 t gndio gndio4 - gndio4 - y13 pb42b 4 bdq42 c pb51b 4 bdq51 c u13 pb43a 4 bdq42 t pb52a 4 bdq51 t u14 pb43b 4 bdq42 c pb52b 4 bdq51 c ab15 pb44a 4 bdq42 t pb53a 4 bdq51 t vccio vccio4 4 vccio 4 aa14 pb44b 4 bdq42 c pb53b 4 bdq51 c ab16 pb45a 4 bdq42 t pb54a 4 bdq51 t ab17 pb45b 4 bdq42 c pb54b 4 bdq51 c w13 pb46a 4 bdq42 t pb55a 4 bdq51 t gndio gndio4 - gndio4 - w14 pb46b 4 bdq42 c pb55b 4 bdq51 c ab18 pb48a 4 bdq51 t pb57a 4 bdq60 t ab19 pb48b 4 bdq51 c pb57b 4 bdq60 c lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-64 pinout information lattice semiconductor latticeecp2 /m family data sheet v14 pb49a 4 bdq51 t pb58a 4 bdq60 t w15 pb49b 4 bdq51 c pb58b 4 bdq60 c vccio vccio4 4 vccio 4 y15 pb50a 4 bdq51 t pb59a 4 bdq60 t aa15 pb50b 4 bdq51 c pb59b 4 bdq60 c gndio gndio4 - gndio4 - aa16 pb51a 4 bdqs51 t pb60a 4 bdqs60 t aa17 pb51b 4 bdq51 c pb60b 4 bdq60 c ab20 pb52a 4 bdq51 t pb61a 4 bdq60 t ab21 pb52b 4 bdq51 c pb61b 4 bdq60 c u15 pb53a 4 bdq51 t pb62a 4 bdq60 t u16 pb53b 4 bdq51 c pb62b 4 bdq60 c vccio vccio4 4 vccio 4 y16 pb54a 4 bdq51 t pb63a 4 bdq60 t w16 pb54b 4 bdq51 c pb63b 4 bdq60 c aa18 pb55a 4 bdq51 t pb64a 4 bdq60 t aa20 pb55b 4 bdq51 c pb64b 4 bdq60 c gndio gndio4 - gndio4 - vccio vccio4 4 vccio 4 aa21 pb66a 4 bdq69 t pb75a 4 bdq78 t aa22 pb66b 4 bdq69 c pb75b 4 bdq78 c v16 pb67a 4 bdq69 t pb76a 4 bdq78 t v17 pb67b 4 bdq69 c pb76b 4 bdq78 c vccio vccio4 4 vccio 4 y18 pb68a 4 bdq69 t pb77a 4 bdq78 t y17 pb68b 4 bdq69 c pb77b 4 bdq78 c gndio gndio4 - gndio4 - y19 pb69a 4 bdqs69 t pb78a 4 bdqs78 t y20 pb69b 4 bdq69 c pb78b 4 bdq78 c w17 pb70a 4 bdq69 t pb79a 4 bdq78 t w18 pb70b 4 bdq69 c pb79b 4 bdq78 c y21 pb71a 4 bdq69 t pb80a 4 bdq78 t y22 pb71b 4 bdq69 c pb80b 4 bdq78 c vccio vccio4 4 vccio 4 u18 pb72a 4 bdq69 t pb81a 4 bdq78 t v18 pb72b 4 bdq69 c pb81b 4 bdq78 c t15 pb73a 4 vref2_4/bdq69 t pb82a 4 vref2_4/bdq78 t t16 pb73b 4 vref1_4/bdq69 c pb82b 4 vref1_4/bdq78 c gndio gndio4 - gndio4 - w19 cfg2 8 cfg2 8 v19 cfg1 8 cfg1 8 w20 cfg0 8 cfg0 8 v20 programn 8 programn 8 w22 cclk 8 cclk 8 v22 initn 8 initn 8 v21 done 8 done 8 gndio gndio8 - gndio8 - lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-65 pinout information lattice semiconductor latticeecp2 /m family data sheet r16 pr58b 8 writen c pr77b 8 writen c r17 pr58a 8 cs1n t pr77a 8 cs1n t u19 pr57b 8 csn c pr76b 8 csn c u20 pr57a 8 d0/spifastn t pr76a 8 d0/spifastn t vccio vccio8 8 vccio 8 u22 pr56b 8 d1 c pr75b 8 d1 c u21 pr56a 8 d2 t pr75a 8 d2 t t20 pr55b 8 d3 c pr74b 8 d3 c gndio gndio8 - gndio8 - t19 pr55a 8 d4 t pr74a 8 d4 t t17 pr54b 8 d5 c pr73b 8 d5 c t18 pr54a 8 d6 t pr73a 8 d6 t t21 pr53b 8 d7/spid0 c pr72b 8 d7/spid0 c vccio vccio8 8 vccio 8 t22 pr53a 8 di/csspi0n t pr72a 8 di/csspi0n t r18 pr52b 8 dout/cson c pr71b 8 dout/cson c r19 pr52a 8 busy/sispi t pr71a 8 busy/sispi t gndio gndio3 - gndio3 - vccio vccio3 3 vccio 3 r22 pr47b 3 rdq48 c pr66b 3 rdq67 c r21 pr47a 3 rdq48 t pr66a 3 rdq67 t p18 pr46b 3 rdq48 c (lvds)* pr65b 3 rdq67 c (lvds)* p19 pr46a 3 rdq48 t (lvds)* pr65a 3 rdq67 t (lvds)* vccio vccio3 3 vccio 3 r20 pr45b 3 rlm0_gpllc_fb_a/rdq48 c pr64b 3 rlm0_gpllc_fb_a/rdq67 c p22 pr45a 3 rlm0_gpllt_fb_a/rdq48 t pr64a 3 rlm0_gpllt_fb_a/rdq67 t p21 pr44b 3 rlm0_gpllc_in_a**/rdq48 c (lvds)* pr63b 3 rlm0_gpllc_in_a**/rdq67 c (lvds)* n21 pr44a 3 rlm0_gpllt_in_a**/rdq48 t (lvds) * pr63a 3 rlm0_gpllt_in_a**/rdq67 t (lvds)* n17 rlm0_pllcap 3 rlm0_pllcap 3 n22 pr42b 3 rlm0_gdllc_fb_a/rdq39 c pr61b 3 rlm0_gdllc_fb_a/rdq58 c n20 pr42a 3 rlm0_gdllt_fb_a/rdq39 t pr61a 3 rlm0_gdllt_fb_a/rdq58 t gndio gndio3 - gndio3 - m22 pr41b 3 rlm0_gdllc_in_a**/rdq39 c (lvds) * pr60b 3 rlm0_gdllc_in_a**/rdq58 c (lvds)* m21 pr41a 3 rlm0_gdllt_in_a**/rdq39 t (lvds)* p r60a 3 rlm0_gdllt_in_a**/rdq58 t (lvds)* n19 pr40b 3 rdq39 c pr59b 3 rdq58 c m19 pr40a 3 rdq39 t pr59a 3 rdq58 t vccio vccio3 3 vccio 3 gndio gndio3 - gndio3 - l22 pr30b 3 rdq31 c pr49b 3 rdq50 c k22 pr30a 3 rdq31 t pr49a 3 rdq50 t j22 pr29b 3 rdq31 c (lvds)* pr48b 3 rdq50 c (lvds)* h22 pr29a 3 rdq31 t (lvds)* pr48a 3 rdq50 t (lvds)* vccio vccio3 3 vccio 3 m20 pr28b 3 vref2_3/rdq31 c pr47b 3 vref2_3/rdq50 c l21 pr28a 3 vref1_3/rdq31 t pr47a 3 vref1_3/rdq50 t k21 pr27b 3 pclkc3_0/rdq31 c (lvds)* pr46b 3 pclkc3_0/rdq50 c (lvds)* j21 pr27a 3 pclkt3_0/rdq31 t (lvds)* pr46a 3 pclkt3_0/rdq50 t (lvds)* lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-66 pinout information lattice semiconductor latticeecp2 /m family data sheet m18 pr25b 2 pclkc2_0/rdq22 c pr44b 2 pclkc2_0/rdq41 c l17 pr25a 2 pclkt2_0/rdq22 t pr44a 2 pclkt2_0/rdq41 t gndio gndio2 - gndio2 - l19 pr24b 2 rdq22 c (lvds)* pr43b 2 rdq41 c (lvds)* l20 pr24a 2 rdq22 t (lvds)* pr43a 2 rdq41 t (lvds)* l18 pr23b 2 rdq22 c pr42b 2 rdq41 c k17 pr23a 2 rdq22 t pr42a 2 rdq41 t vccio vccio2 2 vccio 2 k18 pr22b 2 rdq22 c (lvds)* pr41b 2 rdq41 c (lvds)* k19 pr22a 2 rdqs22 t (lvds)* pr41a 2 rdqs41 t (lvds)* g22 pr21b 2 rdq22 c pr40b 2 rdq41 c gndio gndio2 - gndio2 - f22 pr21a 2 rdq22 t pr40a 2 rdq41 t j17 pr20b 2 rdq22 c (lvds)* pr39b 2 rdq41 c (lvds)* j18 pr20a 2 rdq22 t (lvds)* pr39a 2 rdq41 t (lvds)* k20 pr19b 2 rdq22 c pr38b 2 rdq41 c vccio vccio2 2 vccio 2 j19 pr19a 2 rdq22 t pr38a 2 rdq41 t h21 pr18b 2 rdq22 c (lvds)* pr37b 2 rdq41 c (lvds)* g21 pr18a 2 rdq22 t (lvds)* pr37a 2 rdq41 t (lvds)* - - - gndio2 - - - - vccio 2 h17 nc - pr26b 2 rum0_spllc_fb_a/rdq24 c h16 nc - pr26a 2 rum0_spllt_fb_a/rdq24 t h20 nc - pr25b 2 rum0_spllc_in_a/rdq24 c h18 nc - pr25a 2 rum0_spllt_in_a/rdq24 t - - - gndio2 - - - - vccio 2 f21 pr17b 2 rdq14 c pr19b 2 rdq16 c gndio gndio2 - gndio2 - e22 pr17a 2 rdq14 t pr19a 2 rdq16 t d22 pr16b 2 rdq14 c (lvds)* pr18b 2 rdq16 c (lvds)* e21 pr16a 2 rdq14 t (lvds)* pr18a 2 rdq16 t (lvds)* g20 pr15b 2 rdq14 c pr17b 2 rdq16 c vccio vccio2 2 vccio 2 f20 pr15a 2 rdq14 t pr17a 2 rdq16 t h19 pr14b 2 rdq14 c (lvds)* pr16b 2 rdq16 c (lvds)* g19 pr14a 2 rdqs14 t (lvds)* pr16a 2 rdqs16 t (lvds)* gndio gndio2 - gndio2 - g17 pr13b 2 rdq14 c pr15b 2 rdq16 c f19 pr13a 2 rdq14 t pr15a 2 rdq16 t e20 pr12b 2 rdq14 c (lvds)* pr14b 2 rdq16 c (lvds)* d20 pr12a 2 rdq14 t (lvds)* pr14a 2 rdq16 t (lvds)* vccio vccio2 2 vccio 2 f18 pr11b 2 rdq14 c pr13b 2 rdq16 c f16 pr11a 2 rdq14 t pr13a 2 rdq16 t c21 pr10b 2 rdq14 c (lvds)* pr12b 2 rdq16 c (lvds)* lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-67 pinout information lattice semiconductor latticeecp2 /m family data sheet c22 pr10a 2 rdq14 t (lvds)* pr12a 2 rdq16 t (lvds)* vccio vccio2 2 vccio 2 gndio gndio2 - gndio2 - d19 pr2b 2 vref2_2/rdq6 c (lvds)* pr2b 2 vref2_2 c (lvds)* e19 pr2a 2 vref1_2/rdq6 t (lvds)* pr2a 2 vref1_2 t (lvds)* b21 pt73b 1 vref2_1 c pt82b 1 vref2_1 c gndio gndio1 - gndio1 - b22 pt73a 1 vref1_1 t pt82a 1 vref1_1 t c20 pt72b 1 c pt81b 1 c c19 pt72a 1 t pt81a 1 t d18 pt71b 1 c pt80b 1 c vccio vccio1 1 vccio 1 e18 pt71a 1 t pt80a 1 t b20 pt70b 1 c pt79b 1 c a19 pt70a 1 t pt79a 1 t d17 pt69b 1 c pt78b 1 c c18 pt69a 1 t pt78a 1 t a21 pt68b 1 c pt77b 1 c gndio gndio1 - gndio1 - a20 pt68a 1 t pt77a 1 t a18 pt67b 1 c pt76b 1 c vccio vccio1 1 vccio 1 b18 pt67a 1 t pt76a 1 t g16 pt66b 1 c pt75b 1 c g15 pt66a 1 t pt75a 1 t d16 pt65b 1 c pt74b 1 c e16 pt65a 1 t pt74a 1 t gndio gndio1 - gndio1 - vccio vccio1 1 vccio 1 c17 pt55b 1 c pt64b 1 c gndio gndio1 - gndio1 - c16 pt55a 1 t pt64a 1 t b17 pt54b 1 c pt63b 1 c b16 pt54a 1 t pt63a 1 t a17 pt53b 1 c pt62b 1 c vccio vccio1 1 vccio 1 a16 pt53a 1 t pt62a 1 t c15 pt52b 1 c pt61b 1 c d15 pt52a 1 t pt61a 1 t e15 pt51b 1 c pt60b 1 c f15 pt51a 1 t pt60a 1 t gndio gndio1 - gndio1 - b15 pt49b 1 c pt58b 1 c vccio vccio1 1 vccio 1 a15 pt49a 1 t pt58a 1 t b14 pt48b 1 c pt57b 1 c a14 pt48a 1 t pt57a 1 t lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-68 pinout information lattice semiconductor latticeecp2 /m family data sheet d14 pt46b 1 c pt55b 1 c c13 pt46a 1 t pt55a 1 t gndio gndio1 - gndio1 - e14 pt45b 1 c pt54b 1 c f14 pt45a 1 t pt54a 1 t a13 pt44b 1 c pt53b 1 c b13 pt44a 1 t pt53a 1 t vccio vccio1 1 vccio 1 e13 pt43b 1 c pt52b 1 c d13 pt43a 1 t pt52a 1 t e12 pt42b 1 c pt51b 1 c d12 pt42a 1 t pt51a 1 t gndio gndio1 - gndio1 - a12 pt40b 1 c pt49b 1 c a11 pt40a 1 t pt49a 1 t vccio vccio1 1 vccio 1 b12 pt39b 1 pclkc1_0 c pt48b 1 pclkc1_0 c c12 pt39a 1 pclkt1_0 t pt48a 1 pclkt1_0 t f12 xres 1 xres 1 b10 pt37b 0 pclkc0_0 c pt46b 0 pclkc0_0 c gndio gndio0 - gndio0 0 b11 pt37a 0 pclkt0_0 t pt46a 0 pclkt0_0 t a10 pt36b 0 c pt45b 0 c a9 pt36a 0 t pt45a 0 t c11 pt35b 0 c pt44b 0 c vccio vccio0 0 vccio 0 c10 pt35a 0 t pt44a 0 t e11 pt34b 0 c pt43b 0 c f11 pt34a 0 t pt43a 0 t a8 pt33b 0 c pt42b 0 c a7 pt33a 0 t pt42a 0 t b8 pt32b 0 c pt41b 0 c gndio gndio0 - gndio0 0 b9 pt32a 0 t pt41a 0 t vccio vccio0 0 vccio 0 b7 pt30b 0 c pt39b 0 c a6 pt30a 0 t pt39a 0 t c8 pt29b 0 c pt38b 0 c d8 pt29a 0 t pt38a 0 t gndio gndio0 - gndio0 0 d10 pt27b 0 c pt36b 0 c e10 pt27a 0 t pt36a 0 t c7 pt26b 0 c pt35b 0 c c6 pt26a 0 t pt35a 0 t vccio vccio0 0 vccio 0 b6 pt25b 0 c pt34b 0 c b5 pt25a 0 t pt34a 0 t lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-69 pinout information lattice semiconductor latticeecp2 /m family data sheet f10 pt24b 0 c pt33b 0 c d9 pt24a 0 t pt33a 0 t gndio gndio0 - gndio0 0 f9 pt23b 0 c pt32b 0 c e9 pt23a 0 t pt32a 0 t a5 pt22b 0 c pt31b 0 c a4 pt22a 0 t pt31a 0 t vccio vccio0 0 vccio 0 a3 pt21b 0 c pt30b 0 c a2 pt21a 0 t pt30a 0 t g8 pt20b 0 c pt29b 0 c e8 pt20a 0 t pt29a 0 t gndio gndio0 - gndio0 0 vccio vccio0 0 vccio 0 c3 pt10b 0 c pt10b 0 c b3 pt10a 0 t pt10a 0 t gndio gndio0 - gndio0 0 f8 pt9b 0 c pt9b 0 c d7 pt9a 0 t pt9a 0 t e7 pt8b 0 c pt8b 0 c vccio vccio0 0 vccio 0 f7 pt8a 0 t pt8a 0 t d5 pt7b 0 c pt7b 0 c d6 pt7a 0 t pt7a 0 t d4 pt6b 0 c pt6b 0 c c4 pt6a 0 t pt6a 0 t gndio gndio0 - gndio0 0 b2 pt5b 0 c pt5b 0 c b1 pt5a 0 t pt5a 0 t j7 pt4b 0 c pt4b 0 c vccio vccio0 0 vccio 0 h7 pt4a 0 t pt4a 0 t d3 pt3b 0 c pt3b 0 c c2 pt3a 0 t pt3a 0 t d1 pt2b 0 vref2_0 c pt2b 0 vref2_0 c c1 pt2a 0 vref1_0 t pt2a 0 vref1_0 t j10 vcc - vcc - j11 vcc - vcc - j12 vcc - vcc - j13 vcc - vcc - k14 vcc - vcc - k9 vcc - vcc - l14 vcc - vcc - l9 vcc- vcc- m14 vcc - vcc - m9 vcc- vcc- n14 vcc - vcc - lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-70 pinout information lattice semiconductor latticeecp2 /m family data sheet n9 vcc- vcc- p10 vcc - vcc - p11 vcc - vcc - p12 vcc - vcc - p13 vcc - vcc - g5 vccaux - vccaux 0 k5 vccaux - vccaux 0 r5 vccaux - vccaux 1 v7 vccaux - vccaux 1 v11 vccaux - vccaux 2 v8 vccaux - vccaux 2 v13 vccaux - vccaux 3 v15 vccaux - vccaux 3 m17 vccaux - vccaux 4 p17 vccaux - vccaux 4 e17 vccaux - vccaux 5 g18 vccaux - vccaux 5 d11 vccaux - vccaux 6 f13 vccaux - vccaux 6 c5 vccaux - vccaux 7 e6 vccaux - vccaux 7 g10 vccio0 0 vccio0 0 g9 vccio0 0 vccio0 0 h8 vccio0 0 vccio0 0 h9 vccio0 0 vccio0 0 g11 vccio1 1 vccio1 1 g12 vccio1 1 vccio1 1 g13 vccio1 1 vccio1 1 g14 vccio1 1 vccio1 1 h14 vccio2 2 vccio2 2 h15 vccio2 2 vccio2 2 j15 vccio2 2 vccio2 2 k16 vccio2 2 vccio2 2 l16 vccio3 3 vccio3 3 m16 vccio3 3 vccio3 3 n16 vccio3 3 vccio3 3 p16 vccio3 3 vccio3 3 r14 vccio4 4 vccio4 4 t12 vccio4 4 vccio4 4 t13 vccio4 4 vccio4 4 t14 vccio4 4 vccio4 4 r9 vccio5 5 vccio5 5 t10 vccio5 5 vccio5 5 t11 vccio5 5 vccio5 5 t9 vccio5 5 vccio5 5 n7 vccio6 6 vccio6 6 p7 vccio6 6 vccio6 6 lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-71 pinout information lattice semiconductor latticeecp2 /m family data sheet p8 vccio6 6 vccio6 6 r8 vccio6 6 vccio6 6 j8 vccio7 7 vccio7 7 k7 vccio7 7 vccio7 7 l7 vccio7 7 vccio7 7 m7 vccio7 7 vccio7 7 p15 vccio8 8 vccio8 8 r15 vccio8 8 vccio8 8 a22 gnd - gnd - aa19gnd- gnd- aa4 gnd - gnd - ab1 gnd - gnd - ab22gnd- gnd- b19 gnd - gnd - b4 gnd- gnd- c14 gnd - gnd - c9 gnd - gnd - d2 gnd - gnd - d21 gnd - gnd - f17 gnd - gnd - f6 gnd- gnd- h10 gnd - gnd - h11 gnd - gnd - h12 gnd - gnd - h13 gnd - gnd - j14 gnd - gnd - j20 gnd - gnd - j3 gnd- gnd- j9 gnd- gnd- k10 gnd - gnd - k11 gnd - gnd - k12 gnd - gnd - k13 gnd - gnd - k15 gnd - gnd - k8 gnd- gnd- l10 gnd - gnd - l11 gnd - gnd - l12 gnd - gnd - l13 gnd - gnd - l15 gnd - gnd - l8 gnd- gnd- m10 gnd - gnd - m11 gnd - gnd - m12 gnd - gnd - m13 gnd - gnd - m15 gnd - gnd - m8 gnd- gnd- lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-72 pinout information lattice semiconductor latticeecp2 /m family data sheet n10 gnd - gnd - n11 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n15 gnd - gnd - n8 gnd - gnd - p14 gnd - gnd - p20 gnd - gnd - p3 gnd- gnd- p9 gnd- gnd- r10 gnd - gnd - r11 gnd - gnd - r12 gnd - gnd - r13 gnd - gnd - u17 gnd - gnd - u6 gnd - gnd - w2gnd- gnd- w21 gnd - gnd - y14 gnd - gnd - y9 gnd- gnd- a1 gnd- gnd- n18 vccpll - vccpll - k6 nc - vccpll - n6 vccpll - vccpll - j16 nc - vccpll - * supports true lvds. other differential si gnals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. ***due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the substr ate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-35e/se and lfe2-50e/se logic signal connections: 484 fpbga lfe2-35e/se lfe2-50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-73 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential d2 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7/ldq6 t (lvds)* d1 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7/ldq6 c (lvds)* gnd gndio7 - gndio7 - f6 pl3a 7 t pl3a 7 ldq6 t f5 pl3b 7 c pl3b 7 ldq6 c vccio vccio7 7 vccio7 7 e4 nc - pl4a 7 ldq6 t (lvds)* e3 nc - pl4b 7 ldq6 c (lvds)* e2 nc - pl5a 7 ldq6 t e1 nc - pl5b 7 ldq6 c gnd gndio7 - gndio7 - h6 nc - pl6a 7 ldqs6 t (lvds)* h5 nc - pl6b 7 ldq6 c (lvds)* f2 nc - pl7a 7 ldq6 t vccio vccio7 7 vccio7 7 f1 nc - pl7b 7 ldq6 c h8 nc - pl8a 7 ldq6 t (lvds)* j9 nc - pl8b 7 ldq6 c (lvds)* g4 nc - pl9a 7 ldq6 t gnd gndio7 - gndio7 - g3 nc - pl9b 7 ldq6 c h7 pl4a 7 ldq8 t (lvds)* pl10a 7 ldq14 t (lvds)* j8 pl4b 7 ldq8 c (lvds)* pl10b 7 ldq14 c (lvds)* g2 pl5a 7 ldq8 t pl11a 7 ldq14 t g1 pl5b 7 ldq8 c pl11b 7 ldq14 c h3 pl6a 7 ldq8 t (lvds)* pl12a 7 ldq14 t (lvds)* vccio vccio7 7 vccio7 7 h4 pl6b 7 ldq8 c (lvds)* pl12b 7 ldq14 c (lvds)* j5 pl7a 7 ldq8 t pl13a 7 ldq14 t j4 pl7b 7 ldq8 c pl13b 7 ldq14 c j3 pl8a 7 ldqs8 t (lvds)* pl14a 7 ldqs14 t (lvds)* gnd gndio7 - gndio7 - k4 pl8b 7 ldq8 c (lvds)* pl14b 7 ldq14 c (lvds)* h1 pl9a 7 ldq8 t pl15a 7 ldq14 t h2 pl9b 7 ldq8 c pl15b 7 ldq14 c vccio vccio7 7 vccio7 7 k6 pl10a 7 ldq8 t (lvds)* pl16a 7 ldq14 t (lvds)* k7 pl10b 7 ldq8 c (lvds)* pl16b 7 ldq14 c (lvds)* j1 pl11a 7 ldq8 t pl17a 7 ldq14 t j2 pl11b 7 ldq8 c pl17b 7 ldq14 c gnd gndio7 - gndio7 - vccio vccio7 7 vccio7 7 k3 nc - nc - k2 nc - nc - gnd gndio7 - gndio7 - k1 nc - nc - l2 nc - nc - 4-74 pinout information lattice semiconductor latticeecp2 /m family data sheet l1 nc - nc - vccio vccio7 7 vccio7 7 m2 nc - nc - m1 nc - nc - n2 nc - nc - gnd gndio7 - gndio7 - m8 vcc - nc - vccio vccio7 7 vccio7 7 gnd gndio7 - gndio7 - n1 pl12a 7 ldq16 pl18a 7 ldq22 l8 pl13a 7 ldq16 t pl19a 7 ldq22 t k8 pl13b 7 ldq16 c pl19b 7 ldq22 c vccio vccio7 7 vccio7 7 l6 pl14a 7 ldq16 t (lvds)* pl20a 7 ldq22 t (lvds)* k5 pl14b 7 ldq16 c (lvds)* pl20b 7 ldq22 c (lvds)* l7 pl15a 7 ldq16 t pl21a 7 ldq22 t l5 pl15b 7 ldq16 c pl21b 7 ldq22 c gnd gndio7 - gndio7 - p1 pl16a 7 ldqs16 t (lvds)* pl22a 7 ldqs22 t (lvds)* p2 pl16b 7 ldq16 c (lvds)* pl22b 7 ldq22 c (lvds)* m6 pl17a 7 ldq16 t pl23a 7 ldq22 t vccio vccio7 7 vccio7 7 n8 pl17b 7 ldq16 c pl23b 7 ldq22 c r1 pl18a 7 ldq16 t (lvds)* pl24a 7 ldq22 t (lvds)* r2 pl18b 7 ldq16 c (lvds)* pl24b 7 ldq22 c (lvds)* m7 pl19a 7 pclkt7_0/ldq16 t pl25a 7 pclkt7_0/ldq22 t gnd gndio7 - gndio7 - n9 pl19b 7 pclkc7_0/ldq16 c pl25b 7 pclkc7_0/ldq22 c m4 pl21a 6 pclkt6_0/ldq25 t (lvds)* pl27a 6 pclkt6_0/ldq31 t (lvds)* m5 pl21b 6 pclkc6_0/ldq25 c (lvds)* pl27b 6 pclkc6_0/ldq31 c (lvds)* n7 pl22a 6 vref2_6/ldq25 t pl28a 6 vref2_6/ldq31 t p9 pl22b 6 vref1_6/ldq25 c pl28b 6 vref1_6/ldq31 c n3 pl23a 6 ldq25 t (lvds)* pl29a 6 ldq31 t (lvds)* vccio vccio6 6 vccio6 6 n4 pl23b 6 ldq25 c (lvds)* pl29b 6 ldq31 c (lvds)* n5 pl24a 6 ldq25 t pl30a 6 ldq31 t p7 pl24b 6 ldq25 c pl30b 6 ldq31 c t1 nc - pl31a 6 ldqs31 t (lvds)* gnd gndio6 - gndio6 - t2 nc - pl31b 6 ldq31 c (lvds)* p8 nc - pl32a 6 ldq31 t p6 nc - pl32b 6 ldq31 c vccio vccio6 6 vccio6 6 p5 nc - pl33a 6 ldq31 t (lvds)* p4 nc - pl33b 6 ldq31 c (lvds)* u1 nc - pl34a 6 ldq31 t v1 nc - pl34b 6 ldq31 c lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-75 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gndio6 - gndio6 - p3 nc - nc - r3 nc - nc - r4 nc - nc - u2 nc - nc - vccio vccio6 6 vccio6 6 v2 nc - nc - w2 nc - nc - t6 nc - pl38a 6 ldq39 t r5 nc - pl38b 6 ldq39 c gnd gndio6 - gndio6 - r6 pl25a 6 ldqs25*** t (lvds)* pl39a 6 ldqs39*** t (lvds)* r7 pl25b 6 ldq25 c (lvds)* pl39b 6 ldq39 c (lvds)* w1 pl26a 6 ldq25 t pl40a 6 ldq39 t vccio vccio6 6 vccio6 6 y2 pl26b 6 ldq25 c pl40b 6 ldq39 c y1 pl27a 6 llm0_gdllt_in_a**/ldq25 t (lvds)* pl41a 6 llm0_gdllt_in_a**/ldq39 t (lvds)* aa2 pl27b 6 llm0_gdllc_in_a**/ldq25 c (lvds)* pl41b 6 llm0_gdllc_in_a**/ldq39 c (lvds)* t5 pl28a 6 llm0_gdllt_fb_a/ldq25 t pl42a 6 llm0_gdllt_fb_a/ldq39 t gnd gndio6 - gndio6 - t7 pl28b 6 llm0_gdllc_fb_a/ldq25 c pl42b 6 llm0_gdllc_fb_a/ldq39 c r8 vcc 6 vccpll 6 t8 llm0_pllcap 6 llm0_pllcap 6 u3 pl30a 6 llm0_gpllt_in_a**/ldq34 t (lvds)* pl44a 6 llm0_gpllt_in_a**/ldq48 t (lvds)* u4 pl30b 6 llm0_gpllc_in_a**/ldq34 c (lvds)* pl44b 6 llm0_gpllc_in_a**/ldq48 c (lvds)* v3 pl31a 6 llm0_gpllt_fb_a/ldq34 t pl45a 6 llm0_gpllt_fb_a/ldq48 t u5 pl31b 6 llm0_gpllc_fb_a/ldq34 c pl45b 6 llm0_gpllc_fb_a/ldq48 c v4 pl32a 6 ldq34 t (lvds)* pl46a 6 ldq48 t (lvds)* vccio vccio6 6 vccio6 6 v5 pl32b 6 ldq34 c (lvds)* pl46b 6 ldq48 c (lvds)* y3 pl33a 6 ldq34 t pl47a 6 ldq48 t y4 pl33b 6 ldq34 c pl47b 6 ldq48 c w3 pl34a 6 ldqs34 t (lvds)* pl48a 6 ldqs48 t (lvds)* gnd gndio6 - gndio6 - w4 pl34b 6 ldq34 c (lvds)* pl48b 6 ldq48 c (lvds)* aa1 pl35a 6 ldq34 t pl49a 6 ldq48 t ab1 pl35b 6 ldq34 c pl49b 6 ldq48 c vccio vccio6 6 vccio6 6 u8 pl36a 6 ldq34 t (lvds)* pl50a 6 ldq48 t (lvds)* u7 pl36b 6 ldq34 c (lvds)* pl50b 6 ldq48 c (lvds)* v8 pl37a 6 ldq34 t pl51a 6 ldq48 t u6 pl37b 6 ldq34 c pl51b 6 ldq48 c gnd gndio6 - gndio6 - w6 pl38a 6 ldq42 t (lvds)* pl52a 6 ldq56 t (lvds)* w5 pl38b 6 ldq42 c (lvds)* pl52b 6 ldq56 c (lvds)* ac1 pl39a 6 ldq42 t pl53a 6 ldq56 t ad1 pl39b 6 ldq42 c pl53b 6 ldq56 c lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-76 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio6 6 vccio6 6 y6 pl40a 6 ldq42 t (lvds)* pl54a 6 ldq56 t (lvds)* y5 pl40b 6 ldq42 c (lvds)* pl54b 6 ldq56 c (lvds)* ae2 pl41a 6 ldq42 t pl55a 6 ldq56 t ad2 pl41b 6 ldq42 c pl55b 6 ldq56 c gnd gndio6 - gndio6 - ab3 pl42a 6 ldqs42 t (lvds)* pl56a 6 ldqs56 t (lvds)* ab2 pl42b 6 ldq42 c (lvds)* pl56b 6 ldq56 c (lvds)* w7 pl43a 6 ldq42 t pl57a 6 ldq56 t vccio vccio6 6 vccio6 6 w8 pl43b 6 ldq42 c pl57b 6 ldq56 c y7 pl44a 6 ldq42 t (lvds)* pl58a 6 ldq56 t (lvds)* y8 pl44b 6 ldq42 c (lvds)* pl58b 6 ldq56 c (lvds)* ac2 pl45a 6 ldq42 t pl59a 6 ldq56 t gnd gndio6 - gndio6 - ad3 pl45b 6 ldq42 c pl59b 6 ldq56 c ac3 tck - tck - aa8 tdi - tdi - ab4 tms - tms - aa5 tdo - tdo - ab5 vccj - vccj - ae3 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t af3 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c ac4 pb3a 5 bdq6 t pb3a 5 bdq6 t ad4 pb3b 5 bdq6 c pb3b 5 bdq6 c ae4 pb4a 5 bdq6 t pb4a 5 bdq6 t af4 pb4b 5 bdq6 c pb4b 5 bdq6 c vccio vccio5 5 vccio5 5 v9 pb5a 5 bdq6 t pb5a 5 bdq6 t w9 pb5b 5 bdq6 c pb5b 5 bdq6 c gnd gndio5 - gndio5 - aa6 pb6a 5 bdqs6 t pb6a 5 bdqs6 t ab6 pb6b 5 bdq6 c pb6b 5 bdq6 c ac5 pb7a 5 bdq6 t pb7a 5 bdq6 t ad5 pb7b 5 bdq6 c pb7b 5 bdq6 c aa7 pb8a 5 bdq6 t pb8a 5 bdq6 t ab7 pb8b 5 bdq6 c pb8b 5 bdq6 c vccio vccio5 5 vccio5 5 ae5 pb9a 5 bdq6 t pb9a 5 bdq6 t af5 pb9b 5 bdq6 c pb9b 5 bdq6 c ac7 pb10a 5 bdq6 t pb10a 5 bdq6 t ad7 pb10b 5 bdq6 c pb10b 5 bdq6 c vccio vccio5 5 vccio5 5 gnd gndio5 - gndio5 - w10 pb11a 5 bdq15 t pb11a 5 bdq15 t y10 pb11b 5 bdq15 c pb11b 5 bdq15 c w11 pb12a 5 bdq15 t pb12a 5 bdq15 t lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-77 pinout information lattice semiconductor latticeecp2 /m family data sheet aa10 pb12b 5 bdq15 c pb12b 5 bdq15 c ac8 pb13a 5 bdq15 t pb13a 5 bdq15 t ad8 pb13b 5 bdq15 c pb13b 5 bdq15 c vccio vccio5 5 vccio5 5 ab8 pb14a 5 bdq15 t pb14a 5 bdq15 t ab10 pb14b 5 bdq15 c pb14b 5 bdq15 c gnd gndio5 - gndio5 - ae6 pb15a 5 bdqs15 t pb15a 5 bdqs15 t af6 pb15b 5 bdq15 c pb15b 5 bdq15 c aa11 pb16a 5 bdq15 t pb16a 5 bdq15 t ac9 pb16b 5 bdq15 c pb16b 5 bdq15 c ab9 pb17a 5 bdq15 t pb17a 5 bdq15 t ad9 pb17b 5 bdq15 c pb17b 5 bdq15 c vccio vccio5 5 vccio5 5 y11 pb18a 5 bdq15 t pb18a 5 bdq15 t ab11 pb18b 5 bdq15 c pb18b 5 bdq15 c ae7 pb19a 5 bdq15 t pb19a 5 bdq15 t af7 pb19b 5 bdq15 c pb19b 5 bdq15 c gnd gndio5 - gndio5 - ac10 pb20a 5 bdq24 t pb20a 5 bdq24 t ad10 pb20b 5 bdq24 c pb20b 5 bdq24 c aa12 pb21a 5 bdq24 t pb21a 5 bdq24 t w12 pb21b 5 bdq24 c pb21b 5 bdq24 c ab12 pb22a 5 bdq24 t pb22a 5 bdq24 t vccio vccio5 5 vccio5 5 y12 pb22b 5 bdq24 c pb22b 5 bdq24 c ad12 pb23a 5 bdq24 t pb23a 5 bdq24 t ac12 pb23b 5 bdq24 c pb23b 5 bdq24 c ac13 pb24a 5 bdqs24 t pb24a 5 bdqs24 t gnd gndio5 - gndio5 - aa13 pb24b 5 bdq24 c pb24b 5 bdq24 c ad13 pb25a 5 bdq24 t pb25a 5 bdq24 t ac14 pb25b 5 bdq24 c pb25b 5 bdq24 c ae8 pb26a 5 bdq24 t pb26a 5 bdq24 t vccio vccio5 5 vccio5 5 af8 pb26b 5 bdq24 c pb26b 5 bdq24 c ab15 pb27a 5 bdq24 t pb27a 5 bdq24 t y13 pb27b 5 bdq24 c pb27b 5 bdq24 c ae9 pb28a 5 bdq24 t pb28a 5 bdq24 t gnd gndio5 - gndio5 - af9 pb28b 5 bdq24 c pb28b 5 bdq24 c w13 pb29a 5 bdq33 t pb29a 5 bdq33 t aa14 pb29b 5 bdq33 c pb29b 5 bdq33 c ae10 pb30a 5 bdq33 t pb30a 5 bdq33 t af10 pb30b 5 bdq33 c pb30b 5 bdq33 c w14 pb31a 5 bdq33 t pb31a 5 bdq33 t ab13 pb31b 5 bdq33 c pb31b 5 bdq33 c lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-78 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio5 5 vccio5 5 y14 pb32a 5 bdq33 t pb32a 5 bdq33 t ab14 pb32b 5 bdq33 c pb32b 5 bdq33 c gnd gndio5 - gndio5 - ae11 pb33a 5 bdqs33 t pb33a 5 bdqs33 t af11 pb33b 5 bdq33 c pb33b 5 bdq33 c ad14 pb34a 5 bdq33 t pb34a 5 bdq33 t aa15 pb34b 5 bdq33 c pb34b 5 bdq33 c ae12 pb35a 5 pclkt5_0/bdq33 t pb35a 5 pclkt5_0/bdq33 t af12 pb35b 5 pclkc5_0/bdq33 c pb35b 5 pclkc5_0/bdq33 c vccio vccio5 5 vccio5 5 gnd gndio5 - gndio5 - ad15 pb40a 4 pclkt4_0/bdq42 t pb40a 4 pclkt4_0/bdq42 t vccio vccio4 4 vccio4 4 ac15 pb40b 4 pclkc4_0/bdq42 c pb40b 4 pclkc4_0/bdq42 c ae13 pb41a 4 bdq42 t pb41a 4 bdq42 t af13 pb41b 4 bdq42 c pb41b 4 bdq42 c ab17 pb42a 4 bdqs42 t pb42a 4 bdqs42 t gnd gndio4 - gndio4 - y15 pb42b 4 bdq42 c pb42b 4 bdq42 c ae14 pb43a 4 bdq42 t pb43a 4 bdq42 t af14 pb43b 4 bdq42 c pb43b 4 bdq42 c aa16 pb44a 4 bdq42 t pb44a 4 bdq42 t vccio vccio4 4 vccio4 4 w15 pb44b 4 bdq42 c pb44b 4 bdq42 c ac17 pb45a 4 bdq42 t pb45a 4 bdq42 t ab16 pb45b 4 bdq42 c pb45b 4 bdq42 c ae15 pb46a 4 bdq42 t pb46a 4 bdq42 t gnd gndio4 - gndio4 - af15 pb46b 4 bdq42 c pb46b 4 bdq42 c ae16 pb47a 4 bdq51 t pb47a 4 bdq51 t af16 pb47b 4 bdq51 c pb47b 4 bdq51 c y16 pb48a 4 bdq51 t pb48a 4 bdq51 t ab18 pb48b 4 bdq51 c pb48b 4 bdq51 c ad17 pb49a 4 bdq51 t pb49a 4 bdq51 t ad18 pb49b 4 bdq51 c pb49b 4 bdq51 c vccio vccio4 4 vccio4 4 ac18 pb50a 4 bdq51 t pb50a 4 bdq51 t ad19 pb50b 4 bdq51 c pb50b 4 bdq51 c gnd gndio4 - gndio4 - ac19 pb51a 4 bdqs51 t pb51a 4 bdqs51 t ae17 pb51b 4 bdq51 c pb51b 4 bdq51 c ab19 pb52a 4 bdq51 t pb52a 4 bdq51 t ae19 pb52b 4 bdq51 c pb52b 4 bdq51 c af17 pb53a 4 bdq51 t pb53a 4 bdq51 t ae18 pb53b 4 bdq51 c pb53b 4 bdq51 c vccio vccio4 4 vccio4 4 lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-79 pinout information lattice semiconductor latticeecp2 /m family data sheet w16 pb54a 4 bdq51 t pb54a 4 bdq51 t aa17 pb54b 4 bdq51 c pb54b 4 bdq51 c af18 pb55a 4 bdq51 t pb55a 4 bdq51 t af19 pb55b 4 bdq51 c pb55b 4 bdq51 c gnd gndio4 - gndio4 - aa19 nc - pb56a 4 bdq60 t w17 nc - pb56b 4 bdq60 c y19 nc - pb57a 4 bdq60 t y17 nc - pb57b 4 bdq60 c af20 nc - nc - vccio vccio4 4 vccio4 4 ae20 nc - nc - aa20 nc - nc - w18 nc - nc - ad20 nc - nc - gnd gndio4 - gndio4 - ae21 nc - nc - af21 nc - nc - af22 nc - nc - vccio vccio4 4 vccio4 4 gnd gndio4 - gndio4 - ae22 pb56a 4 bdq60 t pb65a 4 bdq69 t ad22 pb56b 4 bdq60 c pb65b 4 bdq69 c af23 pb57a 4 bdq60 t pb66a 4 bdq69 t ae23 pb57b 4 bdq60 c pb66b 4 bdq69 c ad23 pb58a 4 bdq60 t pb67a 4 bdq69 t ac23 pb58b 4 bdq60 c pb67b 4 bdq69 c vccio vccio4 4 vccio4 4 ab20 pb59a 4 bdq60 t pb68a 4 bdq69 t ac20 pb59b 4 bdq60 c pb68b 4 bdq69 c gnd gndio4 - gndio4 - ab21 pb60a 4 bdqs60 t pb69a 4 bdqs69 t ac22 pb60b 4 bdq60 c pb69b 4 bdq69 c w19 pb61a 4 bdq60 t pb70a 4 bdq69 t aa21 pb61b 4 bdq60 c pb70b 4 bdq69 c af24 pb62a 4 bdq60 t pb71a 4 bdq69 t ae24 pb62b 4 bdq60 c pb71b 4 bdq69 c vccio vccio4 4 vccio4 4 y20 pb63a 4 bdq60 t pb72a 4 bdq69 t ab22 pb63b 4 bdq60 c pb72b 4 bdq69 c y21 pb64a 4 vref2_4/bdq60 t pb73a 4 vref2_4/bdq69 t ab23 pb64b 4 vref1_4/bdq60 c pb73b 4 vref1_4/bdq69 c gnd gndio4 - gndio4 - ad24 cfg2 8 cfg2 8 w20 cfg1 8 cfg1 8 ac24 cfg0 8 cfg0 8 v19 programn 8 programn 8 lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-80 pinout information lattice semiconductor latticeecp2 /m family data sheet aa22 cclk 8 cclk 8 ab24 initn 8 initn 8 ad25 done 8 done 8 gnd gndio8 - gndio8 - w21 pr44b 8 writen c pr58b 8 writen c y22 pr44a 8 cs1n t pr58a 8 cs1n t ac25 pr43b 8 csn c pr57b 8 csn c ab25 pr43a 8 d0/spifastn t pr57a 8 d0/spifastn t vccio vccio8 8 vccio8 8 ad26 pr42b 8 d1 c pr56b 8 d1 c ac26 pr42a 8 d2 t pr56a 8 d2 t y23 pr41b 8 d3 c pr55b 8 d3 c gnd gndio8 - gndio8 - w22 pr41a 8 d4 t pr55a 8 d4 t aa25 pr40b 8 d5 c pr54b 8 d5 c ab26 pr40a 8 d6 t pr54a 8 d6 t w23 pr39b 8 d7/spid0 c pr53b 8 d7/spid0 c vccio vccio8 8 vccio8 8 v22 pr39a 8 di/csspi0n t pr53a 8 di/csspi0n t y24 pr38b 8 dout/cson c pr52b 8 dout/cson c y25 pr38a 8 busy/sispi t pr52a 8 busy/sispi t w24 pr37b 3 rdq34 c pr51b 3 rdq48 c gnd gndio3 - gndio3 - v23 pr37a 3 rdq34 t pr51a 3 rdq48 t aa26 pr36b 3 rdq34 c (lvds)* pr50b 3 rdq48 c (lvds)* y26 pr36a 3 rdq34 t (lvds)* pr50a 3 rdq48 t (lvds)* u21 pr35b 3 rdq34 c pr49b 3 rdq48 c vccio vccio3 3 vccio3 3 u19 pr35a 3 rdq34 t pr49a 3 rdq48 t w25 pr34b 3 rdq34 c (lvds)* pr48b 3 rdq48 c (lvds)* w26 pr34a 3 rdqs34 t (lvds)* pr48a 3 rdqs48 t (lvds)* gnd gndio3 - gndio3 - v24 pr33b 3 rdq34 c pr47b 3 rdq48 c v25 pr33a 3 rdq34 t pr47a 3 rdq48 t v26 pr32b 3 rdq34 c (lvds)* pr46b 3 rdq48 c (lvds)* u26 pr32a 3 rdq34 t (lvds)* pr46a 3 rdq48 t (lvds)* vccio vccio3 3 vccio3 3 u22 pr31b 3 rlm0_gpllc_fb_a/rdq34 c pr45b 3 rlm0_gpllc_fb_a/rdq48 c u23 pr31a 3 rlm0_gpllt_fb_a/rdq34 t pr45a 3 rlm0_gpllt_fb_a/rdq48 t u24 pr30b 3 rlm0_gpllc_in_a**/rdq34 c (lvds)* pr44b 3 rlm0_gpllc_in_a**/rdq48 c (lvds)* u25 pr30a 3 rlm0_gpllt_in_a**/rdq34 t (lvds)* pr44a 3 rlm0_gpllt_in_a**/rdq48 t (lvds)* r20 rlm0_pllcap 3 rlm0_pllcap 3 p18 vcc 3 vccpll 3 t19 pr28b 3 rlm0_gdllc_fb_a/rdq25 c pr42b 3 rlm0_gdllc_fb_a/rdq39 c u20 pr28a 3 rlm0_gdllt_fb_a/rdq25 t pr42a 3 rlm0_gdllt_fb_a/rdq39 t gnd gndio3 - gndio3 - t25 pr27b 3 rlm0_gdllc_in_a**/rdq25 c (lvds)* pr41b 3 rlm0_gdllc_in_a**/rdq39 c (lvds)* lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-81 pinout information lattice semiconductor latticeecp2 /m family data sheet t26 pr27a 3 rlm0_gdllt_in_a**/rdq25 t (lvds)* p r41a 3 rlm0_gdllt_in_a**/rdq39 t (lvds)* t20 pr26b 3 rdq25 c pr40b 3 rdq39 c t22 pr26a 3 rdq25 t pr40a 3 rdq39 t vccio vccio3 3 vccio3 3 r26 pr25b 3 rdq25 c (lvds)* pr39b 3 rdq39 c (lvds)* r25 pr25a 3 rdqs25*** t (lvds)* pr39a 3 rdqs39*** t (lvds)* r22 nc - pr38b 3 rdq39 c gnd gndio3 - gndio3 - t21 nc - pr38a 3 rdq39 t p26 nc - nc - p25 nc - nc - r24 nc - nc - vccio vccio3 3 vccio3 3 r23 nc - nc - p20 nc - nc - r19 nc - nc - p21 nc - pr34b 3 rdq31 c gnd gndio3 - gndio3 - p19 nc - pr34a 3 rdq31 t p23 nc - pr33b 3 rdq31 c (lvds)* p22 nc - pr33a 3 rdq31 t (lvds)* n22 nc - pr32b 3 rdq31 c vccio vccio3 3 vccio3 3 r21 nc - pr32a 3 rdq31 t n26 nc - pr31b 3 rdq31 c (lvds)* n25 nc - pr31a 3 rdqs31 t (lvds)* gnd gndio3 - gndio3 - n19 pr24b 3 rdq25 c pr30b 3 rdq31 c n20 pr24a 3 rdq25 t pr30a 3 rdq31 t m26 pr23b 3 rdq25 c (lvds)* pr29b 3 rdq31 c (lvds)* m25 pr23a 3 rdq25 t (lvds)* pr29a 3 rdq31 t (lvds)* vccio vccio3 3 vccio3 3 n18 pr22b 3 vref2_3/rdq25 c pr28b 3 vref2_3/rdq31 c n21 pr22a 3 vref1_3/rdq25 t pr28a 3 vref1_3/rdq31 t l26 pr21b 3 pclkc3_0/rdq25 c (lvds)* pr27b 3 pclkc3_0/rdq31 c (lvds)* l25 pr21a 3 pclkt3_0/rdq25 t (lvds)* pr27a 3 pclkt3_0/rdq31 t (lvds)* n24 pr19b 2 pclkc2_0/rdq16 c pr25b 2 pclkc2_0/rdq22 c m23 pr19a 2 pclkt2_0/rdq16 t pr25a 2 pclkt2_0/rdq22 t gnd gndio2 - gndio2 - l21 pr18b 2 rdq16 c (lvds)* pr24b 2 rdq22 c (lvds)* k22 pr18a 2 rdq16 t (lvds)* pr24a 2 rdq22 t (lvds)* m24 pr17b 2 rdq16 c pr23b 2 rdq22 c n23 pr17a 2 rdq16 t pr23a 2 rdq22 t vccio vccio2 2 vccio2 2 k26 pr16b 2 rdq16 c (lvds)* pr22b 2 rdq22 c (lvds)* k25 pr16a 2 rdqs16 t (lvds)* pr22a 2 rdqs22 t (lvds)* m20 pr15b 2 rdq16 c pr21b 2 rdq22 c lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-82 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gndio2 - gndio2 - m19 pr15a 2 rdq16 t pr21a 2 rdq22 t l22 pr14b 2 rdq16 c (lvds)* pr20b 2 rdq22 c (lvds)* m22 pr14a 2 rdq16 t (lvds)* pr20a 2 rdq22 t (lvds)* k21 pr13b 2 rdq16 c pr19b 2 rdq22 c vccio vccio2 2 vccio2 2 m21 pr13a 2 rdq16 t pr19a 2 rdq22 t k24 pr12b 2 rdq16 c (lvds)* pr18b 2 rdq22 c (lvds)* j24 pr12a 2 rdq16 t (lvds)* pr18a 2 rdq22 t (lvds)* gnd gndio2 - gndio2 - vccio vccio2 2 vccio2 2 l20 vcc - nc - gnd gndio2 - gndio2 - j26 nc - nc - j25 nc - nc - j23 nc - nc - k23 nc - nc - vccio vccio2 2 vccio2 2 h26 nc - nc - h25 nc - nc - h24 nc - nc - gnd gndio2 - gndio2 - h23 nc - nc - vccio vccio2 2 vccio2 2 g26 pr11b 2 rdq8 c pr17b 2 rdq14 c gnd gndio2 - gndio2 - g25 pr11a 2 rdq8 t pr17a 2 rdq14 t f26 pr10b 2 rdq8 c (lvds)* pr16b 2 rdq14 c (lvds)* f25 pr10a 2 rdq8 t (lvds)* pr16a 2 rdq14 t (lvds)* k20 pr9b 2 rdq8 c pr15b 2 rdq14 c vccio vccio2 2 vccio2 2 l19 pr9a 2 rdq8 t pr15a 2 rdq14 t e26 pr8b 2 rdq8 c (lvds)* pr14b 2 rdq14 c (lvds)* e25 pr8a 2 rdqs8 t (lvds)* pr14a 2 rdqs14 t (lvds)* gnd gndio2 - gndio2 - j22 pr7b 2 rdq8 c pr13b 2 rdq14 c h22 pr7a 2 rdq8 t pr13a 2 rdq14 t g24 pr6b 2 rdq8 c (lvds)* pr12b 2 rdq14 c (lvds)* g23 pr6a 2 rdq8 t (lvds)* pr12a 2 rdq14 t (lvds)* vccio vccio2 2 vccio2 2 k19 pr5b 2 rdq8 c pr11b 2 rdq14 c j19 pr5a 2 rdq8 t pr11a 2 rdq14 t d26 pr4b 2 rdq8 c (lvds)* pr10b 2 rdq14 c (lvds)* c26 pr4a 2 rdq8 t (lvds)* pr10a 2 rdq14 t (lvds)* f22 nc - pr9b 2 rdq6 c e24 nc - pr9a 2 rdq6 t gnd gndio2 - gndio2 - lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-83 pinout information lattice semiconductor latticeecp2 /m family data sheet d25 nc - pr8b 2 rdq6 c (lvds)* c25 nc - pr8a 2 rdq6 t (lvds)* d24 nc - pr7b 2 rdq6 c b25 nc - pr7a 2 rdq6 t vccio vccio2 2 vccio2 2 h21 nc - pr6b 2 rdq6 c (lvds)* g22 nc - pr6a 2 rdqs6 t (lvds)* b24 nc - pr5b 2 rdq6 c gnd gndio2 - gndio2 - c24 nc - pr5a 2 rdq6 t d23 nc - pr4b 2 rdq6 c (lvds)* c23 nc - pr4a 2 rdq6 t (lvds)* g21 pr3b 2 c pr3b 2 rdq6 c vccio vccio2 2 vccio2 2 h20 pr3a 2 t pr3a 2 rdq6 t gnd gndio2 - gndio2 - e22 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2/rdq6 c (lvds)* f21 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2/rdq6 t (lvds)* e23 pt64b 1 vref2_1 c pt73b 1 vref2_1 c gnd gndio1 - gndio1 - d22 pt64a 1 vref1_1 t pt73a 1 vref1_1 t g20 pt63b 1 c pt72b 1 c j18 pt63a 1 t pt72a 1 t f20 pt62b 1 c pt71b 1 c vccio vccio1 1 vccio1 1 h19 pt62a 1 t pt71a 1 t a24 pt61b 1 c pt70b 1 c a23 pt61a 1 t pt70a 1 t e21 pt60b 1 c pt69b 1 c f19 pt60a 1 t pt69a 1 t c22 pt59b 1 c pt68b 1 c gnd gndio1 - gndio1 - e20 pt59a 1 t pt68a 1 t b22 pt58b 1 c pt67b 1 c vccio vccio1 1 vccio1 1 b23 pt58a 1 t pt67a 1 t c20 pt57b 1 c pt66b 1 c d20 pt57a 1 t pt66a 1 t a22 pt56b 1 c pt65b 1 c a21 pt56a 1 t pt65a 1 t gnd gndio1 - gndio1 - e19 nc - nc - c19 nc - nc - vccio vccio1 1 vccio1 1 b21 nc - nc - b20 nc - nc - d19 nc - nc - lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-84 pinout information lattice semiconductor latticeecp2 /m family data sheet b19 nc - nc - gnd gndio1 - gndio1 - g17 nc - nc - e18 nc - nc - g19 nc - nc - f17 nc - nc - vccio vccio1 1 vccio1 1 a20 nc - nc - a19 nc - nc - e17 nc - nc - d18 nc - nc - b18 pt55b 1 c pt55b 1 c gnd gndio1 - gndio1 - a18 pt55a 1 t pt55a 1 t e16 pt54b 1 c pt54b 1 c g16 pt54a 1 t pt54a 1 t f16 pt53b 1 c pt53b 1 c vccio vccio1 1 vccio1 1 h18 pt53a 1 t pt53a 1 t a17 pt52b 1 c pt52b 1 c b17 pt52a 1 t pt52a 1 t c18 pt51b 1 c pt51b 1 c b16 pt51a 1 t pt51a 1 t c17 pt50b 1 c pt50b 1 c gnd gndio1 - gndio1 - d17 pt50a 1 t pt50a 1 t e15 pt49b 1 c pt49b 1 c vccio vccio1 1 vccio1 1 g15 pt49a 1 t pt49a 1 t a16 pt48b 1 c pt48b 1 c b15 pt48a 1 t pt48a 1 t d15 pt47b 1 c pt47b 1 c f15 pt47a 1 t pt47a 1 t a14 pt46b 1 c pt46b 1 c b14 pt46a 1 t pt46a 1 t gnd gndio1 - gndio1 - c15 pt45b 1 c pt45b 1 c a15 pt45a 1 t pt45a 1 t a13 pt44b 1 c pt44b 1 c b13 pt44a 1 t pt44a 1 t vccio vccio1 1 vccio1 1 h17 pt43b 1 c pt43b 1 c h15 pt43a 1 t pt43a 1 t d13 pt42b 1 c pt42b 1 c c14 pt42a 1 t pt42a 1 t gnd gndio1 - gndio1 - g14 pt41b 1 c pt41b 1 c lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-85 pinout information lattice semiconductor latticeecp2 /m family data sheet e14 pt41a 1 t pt41a 1 t a12 pt40b 1 c pt40b 1 c b12 pt40a 1 t pt40a 1 t vccio vccio1 1 vccio1 1 f14 pt39b 1 pclkc1_0 c pt39b 1 pclkc1_0 c d14 pt39a 1 pclkt1_0 t pt39a 1 pclkt1_0 t h16 xres 1 xres 1 h14 pt37b 0 pclkc0_0 c pt37b 0 pclkc0_0 c gnd gndio0 - gndio0 - h13 pt37a 0 pclkt0_0 t pt37a 0 pclkt0_0 t a11 pt36b 0 c pt36b 0 c b11 pt36a 0 t pt36a 0 t c13 pt35b 0 c pt35b 0 c vccio vccio0 0 vccio0 0 e13 pt35a 0 t pt35a 0 t d12 pt34b 0 c pt34b 0 c f13 pt34a 0 t pt34a 0 t a10 pt33b 0 c pt33b 0 c b10 pt33a 0 t pt33a 0 t c12 pt32b 0 c pt32b 0 c gnd gndio0 - gndio0 - c10 pt32a 0 t pt32a 0 t g13 pt31b 0 c pt31b 0 c vccio vccio0 0 vccio0 0 h12 pt31a 0 t pt31a 0 t a9 pt30b 0 c pt30b 0 c b9 pt30a 0 t pt30a 0 t e12 pt29b 0 c pt29b 0 c g12 pt29a 0 t pt29a 0 t a8 pt28b 0 c pt28b 0 c b8 pt28a 0 t pt28a 0 t gnd gndio0 - gndio0 - e11 pt27b 0 c pt27b 0 c c9 pt27a 0 t pt27a 0 t a7 pt26b 0 c pt26b 0 c b7 pt26a 0 t pt26a 0 t vccio vccio0 0 vccio0 0 f12 pt25b 0 c pt25b 0 c d10 pt25a 0 t pt25a 0 t h11 pt24b 0 c pt24b 0 c g11 pt24a 0 t pt24a 0 t gnd gndio0 - gndio0 - a6 pt23b 0 c pt23b 0 c b6 pt23a 0 t pt23a 0 t d8 pt22b 0 c pt22b 0 c c8 pt22a 0 t pt22a 0 t vccio vccio0 0 vccio0 0 lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-86 pinout information lattice semiconductor latticeecp2 /m family data sheet f11 pt21b 0 c pt21b 0 c e10 pt21a 0 t pt21a 0 t e9 pt20b 0 c pt20b 0 c d9 pt20a 0 t pt20a 0 t g10 pt19b 0 c pt19b 0 c gnd gndio0 - gndio0 - h10 pt19a 0 t pt19a 0 t a5 pt18b 0 c pt18b 0 c b5 pt18a 0 t pt18a 0 t c7 pt17b 0 c pt17b 0 c vccio vccio0 0 vccio0 0 d7 pt17a 0 t pt17a 0 t e8 pt16b 0 c pt16b 0 c f10 pt16a 0 t pt16a 0 t f8 pt15b 0 c pt15b 0 c h9 pt15a 0 t pt15a 0 t c5 pt14b 0 c pt14b 0 c gnd gndio0 - gndio0 - d5 pt14a 0 t pt14a 0 t b4 pt13b 0 pt13b 0 vccio vccio0 0 vccio0 0 gnd gndio0 - gndio0 - vccio vccio0 0 vccio0 0 gnd gndio0 - gndio0 - vccio vccio0 0 vccio0 0 c4 pt10b 0 c pt10b 0 c gnd gndio0 - gndio0 - c3 pt10a 0 t pt10a 0 t a4 pt9b 0 c pt9b 0 c a3 pt9a 0 t pt9a 0 t b3 pt8b 0 c pt8b 0 c vccio vccio0 0 vccio0 0 b2 pt8a 0 t pt8a 0 t d4 pt7b 0 c pt7b 0 c d3 pt7a 0 t pt7a 0 t c2 pt6b 0 c pt6b 0 c c1 pt6a 0 t pt6a 0 t g8 pt5b 0 c pt5b 0 c gnd gndio0 - gndio0 - g7 pt5a 0 t pt5a 0 t e7 pt4b 0 c pt4b 0 c vccio vccio0 0 vccio0 0 f7 pt4a 0 t pt4a 0 t e6 pt3b 0 c pt3b 0 c e5 pt3a 0 t pt3a 0 t g6 pt2b 0 vref2_0 c pt2b 0 vref2_0 c g5 pt2a 0 vref1_0 t pt2a 0 vref1_0 t lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-87 pinout information lattice semiconductor latticeecp2 /m family data sheet l12 vcc - vcc - l13 vcc - vcc - l14 vcc - vcc - l15 vcc - vcc - m11 vcc - vcc - m12 vcc - vcc - m15 vcc - vcc - m16 vcc - vcc - n11 vcc - vcc - n16 vcc - vcc - p11 vcc - vcc - p16 vcc - vcc - r11 vcc - vcc - r12 vcc - vcc - r15 vcc - vcc - r16 vcc - vcc - t12 vcc - vcc - t13 vcc - vcc - t14 vcc - vcc - t15 vcc - vcc - d11 vccio0 0 vccio0 0 d6 vccio0 0 vccio0 0 g9 vccio0 0 vccio0 0 k12 vccio0 0 vccio0 0 j12 vccio0 0 vccio0 0 d16 vccio1 1 vccio1 1 d21 vccio1 1 vccio1 1 g18 vccio1 1 vccio1 1 j15 vccio1 1 vccio1 1 k15 vccio1 1 vccio1 1 f23 vccio2 2 vccio2 2 j20 vccio2 2 vccio2 2 l23 vccio2 2 vccio2 2 m17 vccio2 2 vccio2 2 m18 vccio2 2 vccio2 2 aa23 vccio3 3 vccio3 3 r17 vccio3 3 vccio3 3 r18 vccio3 3 vccio3 3 t23 vccio3 3 vccio3 3 v20 vccio3 3 vccio3 3 ac16 vccio4 4 vccio4 4 ac21 vccio4 4 vccio4 4 u15 vccio4 4 vccio4 4 v15 vccio4 4 vccio4 4 y18 vccio4 4 vccio4 4 ac11 vccio5 5 vccio5 5 ac6 vccio5 5 vccio5 5 lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-88 pinout information lattice semiconductor latticeecp2 /m family data sheet u12 vccio5 5 vccio5 5 v12 vccio5 5 vccio5 5 y9 vccio5 5 vccio5 5 aa4 vccio6 6 vccio6 6 r10 vccio6 6 vccio6 6 r9 vccio6 6 vccio6 6 t4 vccio6 6 vccio6 6 v7 vccio6 6 vccio6 6 f4 vccio7 7 vccio7 7 j7 vccio7 7 vccio7 7 l4 vccio7 7 vccio7 7 m10 vccio7 7 vccio7 7 m9 vccio7 7 vccio7 7 ae25 vccio8 8 vccio8 8 v18 vccio8 8 vccio8 8 j10 vccaux - vccaux - j11 vccaux - vccaux - j16 vccaux - vccaux - j17 vccaux - vccaux - k18 vccaux - vccaux - k9 vccaux - vccaux - l18 vccaux - vccaux - l9 vccaux - vccaux - t18 vccaux - vccaux - t9 vccaux - vccaux - u18 vccaux - vccaux - u9 vccaux - vccaux - v10 vccaux - vccaux - v11 vccaux - vccaux - v16 vccaux - vccaux - v17 vccaux - vccaux - a2 gnd - gnd - a25 gnd - gnd - aa18 gnd - gnd - aa24 gnd - gnd - aa3 gnd - gnd - aa9 gnd - gnd - ad11 gnd - gnd - ad16 gnd - gnd - ad21 gnd - gnd - ad6 gnd - gnd - ae1 gnd - gnd - ae26 gnd - gnd - af2 gnd - gnd - af25 gnd - gnd - b1 gnd - gnd - b26 gnd - gnd - lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-89 pinout information lattice semiconductor latticeecp2 /m family data sheet c11 gnd - gnd - c16 gnd - gnd - c21 gnd - gnd - c6 gnd - gnd - f18 gnd - gnd - f24 gnd - gnd - f3 gnd - gnd - f9 gnd - gnd - j13 gnd - gnd - j14 gnd - gnd - j21 gnd - gnd - j6 gnd - gnd - k10 gnd - gnd - k11 gnd - gnd - k13 gnd - gnd - k14 gnd - gnd - k16 gnd - gnd - k17 gnd - gnd - l10 gnd - gnd - l11 gnd - gnd - l16 gnd - gnd - l17 gnd - gnd - l24 gnd - gnd - l3 gnd - gnd - m13 gnd - gnd - m14 gnd - gnd - n10 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n14 gnd - gnd - n15 gnd - gnd - n17 gnd - gnd - p10 gnd - gnd - p12 gnd - gnd - p13 gnd - gnd - p14 gnd - gnd - p15 gnd - gnd - p17 gnd - gnd - r13 gnd - gnd - r14 gnd - gnd - t10 gnd - gnd - t11 gnd - gnd - t16 gnd - gnd - t17 gnd - gnd - t24 gnd - gnd - t3 gnd - gnd - u10 gnd - gnd - lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-90 pinout information lattice semiconductor latticeecp2 /m family data sheet u11 gnd - gnd - u13 gnd - gnd - u14 gnd - gnd - u16 gnd - gnd - u17 gnd - gnd - v13 gnd - gnd - v14 gnd - gnd - v21 gnd - gnd - v6 gnd - gnd - m3 nc - nc - n6 nc - nc - p24 nc - nc - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. ***due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the s ubstrate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-20e/se and lfe2-35e/se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-91 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential d2 pl2a 7 vref2_7 t (lvds)* pl2a 7 vref2_7 t (lvds)* d1 pl2b 7 vref1_7 c (lvds)* pl2b 7 vref1_7 c (lvds)* gnd gndio7 - gndio7 - f6 pl5a 7 ldq8 t pl18a 7 ldq21 t f5 pl5b 7 ldq8 c pl18b 7 ldq21 c vccio vccio7 7 vccio7 7 e4 pl6a 7 ldq8 t (lvds)* pl19a 7 ldq21 t (lvds)* e3 pl6b 7 ldq8 c (lvds)* pl19b 7 ldq21 c (lvds)* e2 pl7a 7 ldq8 t pl20a 7 ldq21 t e1 pl7b 7 ldq8 c pl20b 7 ldq21 c gnd gndio7 - gndio7 - h6 pl8a 7 ldqs8 t (lvds)* pl21a 7 ldqs21 t (lvds)* h5 pl8b 7 ldq8 c (lvds)* pl21b 7 ldq21 c (lvds)* f2 pl9a 7 ldq8 t pl22a 7 ldq21 t vccio vccio7 7 vccio7 7 f1 pl9b 7 ldq8 c pl22b 7 ldq21 c h8 pl10a 7 ldq8 t (lvds)* pl23a 7 ldq21 t (lvds)* j9 pl10b 7 ldq8 c (lvds)* pl23b 7 ldq21 c (lvds)* g4 pl11a 7 ldq8 t pl24a 7 ldq21 t gnd gndio7 - gndio7 - g3 pl11b 7 ldq8 c pl24b 7 ldq21 c h7 pl12a 7 ldq16 t (lvds)* pl25a 7 ldq29 t (lvds)* j8 pl12b 7 ldq16 c (lvds)* pl25b 7 ldq29 c (lvds)* g2 pl13a 7 ldq16 t pl26a 7 ldq29 t g1 pl13b 7 ldq16 c pl26b 7 ldq29 c h3 pl14a 7 ldq16 t (lvds)* pl27a 7 ldq29 t (lvds)* vccio vccio7 7 vccio7 7 h4 pl14b 7 ldq16 c (lvds)* pl27b 7 ldq29 c (lvds)* j5 pl15a 7 ldq16 t pl28a 7 ldq29 t j4 pl15b 7 ldq16 c pl28b 7 ldq29 c j3 pl16a 7 ldqs16 t (lvds)* pl29a 7 ldqs29 t (lvds)* gnd gndio7 - gndio7 - k4 pl16b 7 ldq16 c (lvds)* pl29b 7 ldq29 c (lvds)* h1 pl17a 7 ldq16 t pl30a 7 ldq29 t h2 pl17b 7 ldq16 c pl30b 7 ldq29 c vccio vccio7 7 vccio7 7 k6 pl18a 7 ldq16 t (lvds)* pl31a 7 ldq29 t (lvds)* k7 pl18b 7 ldq16 c (lvds)* pl31b 7 ldq29 c (lvds)* j1 pl19a 7 ldq16 t pl32a 7 ldq29 t j2 pl19b 7 ldq16 c pl32b 7 ldq29 c gnd gndio7 - gndio7 - vccio vccio7 7 vccio7 7 k3 pl23a 7 ldq24 t pl36a 7 ldq37 t k2 pl23b 7 ldq24 c pl36b 7 ldq37 c gnd gndio7 - gndio7 - k1 pl24a 7 ldqs24*** t (lvds)* pl37a 7 ldqs37*** t (lvds)* l2 pl24b 7 ldq24 c (lvds)* pl37b 7 ldq37 c (lvds)* 4-92 pinout information lattice semiconductor latticeecp2 /m family data sheet l1 pl25a 7 lum0_spllt_in_a/ldq24 t pl38a 7 lum0_spllt_in_a/ldq37 t vccio vccio7 7 vccio7 7 m2 pl25b 7 lum0_spllc_in_a/ldq24 c pl38b 7 lum0_spllc_in_a/ldq37 c m1 pl26a 7 lum0_spllt_fb_a/ldq24 t pl39a 7 lum0_spllt_fb_a/ldq37 t n2 pl26b 7 lum0_spllc_fb_a/ldq24 c pl39b 7 lum0_spllc_fb_a/ldq37 c gnd gndio7 - gndio7 - m8 vccpll 7 nc - vccio vccio7 7 vccio7 7 gnd gndio7 - gndio7 - n1 pl37a 7 ldq41 pl50a 7 ldq54 l8 pl38a 7 ldq41 t pl51a 7 ldq54 t k8 pl38b 7 ldq41 c pl51b 7 ldq54 c vccio vccio7 7 vccio7 7 l6 pl39a 7 ldq41 t (lvds)* pl52a 7 ldq54 t (lvds)* k5 pl39b 7 ldq41 c (lvds)* pl52b 7 ldq54 c (lvds)* l7 pl40a 7 ldq41 t pl53a 7 ldq54 t l5 pl40b 7 ldq41 c pl53b 7 ldq54 c gnd gndio7 - gndio7 - p1 pl41a 7 ldqs41 t (lvds)* pl54a 7 ldqs54 t (lvds)* p2 pl41b 7 ldq41 c (lvds)* pl54b 7 ldq54 c (lvds)* m6 pl42a 7 ldq41 t pl55a 7 ldq54 t vccio vccio7 7 vccio7 7 n8 pl42b 7 ldq41 c pl55b 7 ldq54 c r1 pl43a 7 ldq41 t (lvds)* pl56a 7 ldq54 t (lvds)* r2 pl43b 7 ldq41 c (lvds)* pl56b 7 ldq54 c (lvds)* m7 pl44a 7 pclkt7_0/ldq41 t pl57a 7 pclkt7_0/ldq54 t gnd gndio7 - gndio7 - n9 pl44b 7 pclkc7_0/ldq41 c pl57b 7 pclkc7_0/ldq54 c m4 pl46a 6 pclkt6_0/ldq50 t (lvds)* pl59a 6 pclkt6_0/ldq63 t (lvds)* m5 pl46b 6 pclkc6_0/ldq50 c (lvds)* pl59b 6 pclkc6_0/ldq63 c (lvds)* n7 pl47a 6 vref2_6/ldq50 t pl60a 6 vref2_6/ldq63 t p9 pl47b 6 vref1_6/ldq50 c pl60b 6 vref1_6/ldq63 c n3 pl48a 6 ldq50 t (lvds)* pl61a 6 ldq63 t (lvds)* vccio vccio6 6 vccio6 6 n4 pl48b 6 ldq50 c (lvds)* pl61b 6 ldq63 c (lvds)* n5 pl49a 6 ldq50 t pl62a 6 ldq63 t p7 pl49b 6 ldq50 c pl62b 6 ldq63 c t1 pl50a 6 ldqs50 t (lvds)* pl63a 6 ldqs63 t (lvds)* gnd gndio6 - gndio6 - t2 pl50b 6 ldq50 c (lvds)* pl63b 6 ldq63 c (lvds)* p8 pl51a 6 ldq50 t pl64a 6 ldq63 t p6 pl51b 6 ldq50 c pl64b 6 ldq63 c vccio vccio6 6 vccio6 6 p5 pl52a 6 ldq50 t (lvds)* pl65a 6 ldq63 t (lvds)* p4 pl52b 6 ldq50 c (lvds)* pl65b 6 ldq63 c (lvds)* u1 pl53a 6 ldq50 t pl66a 6 ldq63 t v1 pl53b 6 ldq50 c pl66b 6 ldq63 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-93 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gndio6 - gndio6 - p3 pl54a 6 ldq58 t (lvds)* pl67a 6 ldq71 t (lvds)* r3 pl54b 6 ldq58 c (lvds)* pl67b 6 ldq71 c (lvds)* r4 pl55a 6 ldq58 t pl68a 6 ldq71 t u2 pl55b 6 ldq58 c pl68b 6 ldq71 c vccio vccio6 6 vccio6 6 v2 pl56a 6 ldq58 t (lvds)* pl69a 6 ldq71 t (lvds)* w2 pl56b 6 ldq58 c (lvds)* pl69b 6 ldq71 c (lvds)* t6 pl57a 6 ldq58 t pl70a 6 ldq71 t r5 pl57b 6 ldq58 c pl70b 6 ldq71 c gnd gndio6 - gndio6 - r6 pl58a 6 ldqs58 t (lvds)* pl71a 6 ldqs71 t (lvds)* r7 pl58b 6 ldq58 c (lvds)* pl71b 6 ldq71 c (lvds)* w1 pl59a 6 ldq58 t pl72a 6 ldq71 t vccio vccio6 6 vccio6 6 y2 pl59b 6 ldq58 c pl72b 6 ldq71 c y1 pl60a 6 llm0_gdllt_in_a**/ldq58 t (lvds)* pl73a 6 llm0_gdllt_in_a**/ldq71 t (lvds)* aa2 pl60b 6 llm0_gdllc_in_a**/ldq58 c (lvds)* pl73b 6 llm0_gdllc_in_a**/ldq71 c (lvds)* t5 pl61a 6 llm0_gdllt_fb_a/ldq58 t pl74a 6 llm0_gdllt_fb_a/ldq71 t gnd gndio6 - gndio6 - t7 pl61b 6 llm0_gdllc_fb_d/ldq58 c pl74b 6 llm0_gdllc_fb_d/ldq71 c r8 vccpll 6 vccpll - t8 llm0_pllcap 6 llm0_pllcap 6 u3 pl63a 6 llm0_gpllt_in_a**/ldq67 t (lvds)* pl76a 6 llm0_gpllt_in_a**/ldq80 t (lvds)* u4 pl63b 6 llm0_gpllc_in_a**/ldq67 c (lvds)* pl76b 6 llm0_gpllc_in_a**/ldq80 c (lvds)* v3 pl64a 6 llm0_gpllt_fb_a/ldq67 t pl77a 6 llm0_gpllt_fb_a/ldq80 t u5 pl64b 6 llm0_gpllc_fb_a/ldq67 c pl77b 6 llm0_gpllc_fb_a/ldq80 c v4 pl65a 6 ldq67 t (lvds)* pl78a 6 ldq80 t (lvds)* vccio vccio6 6 vccio6 6 v5 pl65b 6 ldq67 c (lvds)* pl78b 6 ldq80 c (lvds)* y3 pl66a 6 ldq67 t pl79a 6 ldq80 t y4 pl66b 6 ldq67 c pl79b 6 ldq80 c w3 pl67a 6 ldqs67 t (lvds)* pl80a 6 ldqs80 t (lvds)* gnd gndio6 - gndio6 - w4 pl67b 6 ldq67 c (lvds)* pl80b 6 ldq80 c (lvds)* aa1 pl68a 6 ldq67 t pl81a 6 ldq80 t ab1 pl68b 6 ldq67 c pl81b 6 ldq80 c vccio vccio6 6 vccio6 6 u8 pl69a 6 ldq67 t (lvds)* pl82a 6 ldq80 t (lvds)* u7 pl69b 6 ldq67 c (lvds)* pl82b 6 ldq80 c (lvds)* v8 pl70a 6 ldq67 t pl83a 6 ldq80 t u6 pl70b 6 ldq67 c pl83b 6 ldq80 c gnd gndio6 - gndio6 - w6 pl71a 6 ldq75 t (lvds)* pl84a 6 ldq88 t (lvds)* w5 pl71b 6 ldq75 c (lvds)* pl84b 6 ldq88 c (lvds)* ac1 pl72a 6 ldq75 t pl85a 6 ldq88 t ad1 pl72b 6 ldq75 c pl85b 6 ldq88 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-94 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio6 6 vccio6 6 y6 pl73a 6 ldq75 t (lvds)* pl86a 6 ldq88 t (lvds)* y5 pl73b 6 ldq75 c (lvds)* pl86b 6 ldq88 c (lvds)* ae2 pl74a 6 ldq75 t pl87a 6 ldq88 t ad2 pl74b 6 ldq75 c pl87b 6 ldq88 c gnd gndio6 - gndio6 - ab3 pl75a 6 ldqs75 t (lvds)* pl88a 6 ldqs88 t (lvds)* ab2 pl75b 6 ldq75 c (lvds)* pl88b 6 ldq88 c (lvds)* w7 pl76a 6 ldq75 t pl89a 6 ldq88 t vccio vccio6 6 vccio6 6 w8 pl76b 6 ldq75 c pl89b 6 ldq88 c y7 pl77a 6 ldq75 t (lvds)* pl90a 6 ldq88 t (lvds)* y8 pl77b 6 ldq75 c (lvds)* pl90b 6 ldq88 c (lvds)* ac2 pl78a 6 ldq75 t pl91a 6 ldq88 t gnd gndio6 - gndio6 - ad3 pl78b 6 ldq75 c pl91b 6 ldq88 c ac3 tck - tck - aa8 tdi - tdi - ab4 tms - tms - aa5 tdo - tdo - ab5 vccj - vccj - ae3 pb2a 5 vref2_5/bdq6 t pb2a 5 vref2_5/bdq6 t af3 pb2b 5 vref1_5/bdq6 c pb2b 5 vref1_5/bdq6 c ac4 pb3a 5 bdq6 t pb3a 5 bdq6 t ad4 pb3b 5 bdq6 c pb3b 5 bdq6 c ae4 pb4a 5 bdq6 t pb4a 5 bdq6 t af4 pb4b 5 bdq6 c pb4b 5 bdq6 c vccio vccio5 5 vccio5 5 v9 pb5a 5 bdq6 t pb5a 5 bdq6 t w9 pb5b 5 bdq6 c pb5b 5 bdq6 c gnd gndio5 - gndio5 - aa6 pb6a 5 bdqs6 t pb6a 5 bdqs6 t ab6 pb6b 5 bdq6 c pb6b 5 bdq6 c ac5 pb7a 5 bdq6 t pb7a 5 bdq6 t ad5 pb7b 5 bdq6 c pb7b 5 bdq6 c aa7 pb8a 5 bdq6 t pb8a 5 bdq6 t ab7 pb8b 5 bdq6 c pb8b 5 bdq6 c vccio vccio5 5 vccio5 5 ae5 pb9a 5 bdq6 t pb9a 5 bdq6 t af5 pb9b 5 bdq6 c pb9b 5 bdq6 c ac7 pb10a 5 bdq6 t pb10a 5 bdq6 t ad7 pb10b 5 bdq6 c pb10b 5 bdq6 c vccio vccio5 5 vccio5 5 gnd gndio5 - gndio5 - w10 pb20a 5 bdq24 t pb29a 5 bdq33 t y10 pb20b 5 bdq24 c pb29b 5 bdq33 c w11 pb21a 5 bdq24 t pb30a 5 bdq33 t lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-95 pinout information lattice semiconductor latticeecp2 /m family data sheet aa10 pb21b 5 bdq24 c pb30b 5 bdq33 c ac8 pb22a 5 bdq24 t pb31a 5 bdq33 t ad8 pb22b 5 bdq24 c pb31b 5 bdq33 c vccio vccio5 5 vccio5 5 ab8 pb23a 5 bdq24 t pb32a 5 bdq33 t ab10 pb23b 5 bdq24 c pb32b 5 bdq33 c gnd gndio5 - gndio5 - ae6 pb24a 5 bdqs24 t pb33a 5 bdqs33 t af6 pb24b 5 bdq24 c pb33b 5 bdq33 c aa11 pb25a 5 bdq24 t pb34a 5 bdq33 t ac9 pb25b 5 bdq24 c pb34b 5 bdq33 c ab9 pb26a 5 bdq24 t pb35a 5 bdq33 t ad9 pb26b 5 bdq24 c pb35b 5 bdq33 c vccio vccio5 5 vccio5 5 y11 pb27a 5 bdq24 t pb36a 5 bdq33 t ab11 pb27b 5 bdq24 c pb36b 5 bdq33 c ae7 pb28a 5 bdq24 t pb37a 5 bdq33 t af7 pb28b 5 bdq24 c pb37b 5 bdq33 c gnd gndio5 - gndio5 - ac10 pb29a 5 bdq33 t pb38a 5 bdq42 t ad10 pb29b 5 bdq33 c pb38b 5 bdq42 c aa12 pb30a 5 bdq33 t pb39a 5 bdq42 t w12 pb30b 5 bdq33 c pb39b 5 bdq42 c ab12 pb31a 5 bdq33 t pb40a 5 bdq42 t vccio vccio5 5 vccio5 5 y12 pb31b 5 bdq33 c pb40b 5 bdq42 c ad12 pb32a 5 bdq33 t pb41a 5 bdq42 t ac12 pb32b 5 bdq33 c pb41b 5 bdq42 c ac13 pb33a 5 bdqs33 t pb42a 5 bdqs42 t gnd gndio5 - gndio5 - aa13 pb33b 5 bdq33 c pb42b 5 bdq42 c ad13 pb34a 5 bdq33 t pb43a 5 bdq42 t ac14 pb34b 5 bdq33 c pb43b 5 bdq42 c ae8 pb35a 5 bdq33 t pb44a 5 bdq42 t vccio vccio5 5 vccio5 5 af8 pb35b 5 bdq33 c pb44b 5 bdq42 c ab15 pb36a 5 bdq33 t pb45a 5 bdq42 t y13 pb36b 5 bdq33 c pb45b 5 bdq42 c ae9 pb37a 5 bdq33 t pb46a 5 bdq42 t gnd gndio5 - gndio5 - af9 pb37b 5 bdq33 c pb46b 5 bdq42 c w13 pb38a 5 bdq42 t pb47a 5 bdq51 t aa14 pb38b 5 bdq42 c pb47b 5 bdq51 c ae10 pb39a 5 bdq42 t pb48a 5 bdq51 t af10 pb39b 5 bdq42 c pb48b 5 bdq51 c w14 pb40a 5 bdq42 t pb49a 5 bdq51 t ab13 pb40b 5 bdq42 c pb49b 5 bdq51 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-96 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio5 5 vccio5 5 y14 pb41a 5 bdq42 t pb50a 5 bdq51 t ab14 pb41b 5 bdq42 c pb50b 5 bdq51 c gnd gndio5 - gndio5 - ae11 pb42a 5 bdqs42 t pb51a 5 bdqs51 t af11 pb42b 5 bdq42 c pb51b 5 bdq51 c ad14 pb43a 5 bdq42 t pb52a 5 bdq51 t aa15 pb43b 5 bdq42 c pb52b 5 bdq51 c ae12 pb44a 5 pclkt5_0/bdq42 t pb53a 5 pclkt5_0/bdq51 t af12 pb44b 5 pclkc5_0/bdq42 c pb53b 5 pclkc5_0/bdq51 c vccio vccio5 5 vccio5 5 gnd gndio5 - gndio5 - ad15 pb49a 4 pclkt4_0/bdq51 t pb58a 4 pclkt4_0/bdq60 t vccio vccio4 4 vccio4 4 ac15 pb49b 4 pclkc4_0/bdq51 c pb58b 4 pclkc4_0/bdq60 c ae13 pb50a 4 bdq51 t pb59a 4 bdq60 t af13 pb50b 4 bdq51 c pb59b 4 bdq60 c ab17 pb51a 4 bdqs51 t pb60a 4 bdqs60 t gnd gndio4 - gndio4 - y15 pb51b 4 bdq51 c pb60b 4 bdq60 c ae14 pb52a 4 bdq51 t pb61a 4 bdq60 t af14 pb52b 4 bdq51 c pb61b 4 bdq60 c aa16 pb53a 4 bdq51 t pb62a 4 bdq60 t vccio vccio4 4 vccio4 4 w15 pb53b 4 bdq51 c pb62b 4 bdq60 c ac17 pb54a 4 bdq51 t pb63a 4 bdq60 t ab16 pb54b 4 bdq51 c pb63b 4 bdq60 c ae15 pb55a 4 bdq51 t pb64a 4 bdq60 t gnd gndio4 - gndio4 - af15 pb55b 4 bdq51 c pb64b 4 bdq60 c ae16 pb56a 4 bdq60 t pb65a 4 bdq69 t af16 pb56b 4 bdq60 c pb65b 4 bdq69 c y16 pb57a 4 bdq60 t pb66a 4 bdq69 t ab18 pb57b 4 bdq60 c pb66b 4 bdq69 c ad17 pb58a 4 bdq60 t pb67a 4 bdq69 t ad18 pb58b 4 bdq60 c pb67b 4 bdq69 c vccio vccio4 4 vccio4 4 ac18 pb59a 4 bdq60 t pb68a 4 bdq69 t ad19 pb59b 4 bdq60 c pb68b 4 bdq69 c gnd gndio4 - gndio4 - ac19 pb60a 4 bdqs60 t pb69a 4 bdqs69 t ae17 pb60b 4 bdq60 c pb69b 4 bdq69 c ab19 pb61a 4 bdq60 t pb70a 4 bdq69 t ae19 pb61b 4 bdq60 c pb70b 4 bdq69 c af17 pb62a 4 bdq60 t pb71a 4 bdq69 t ae18 pb62b 4 bdq60 c pb71b 4 bdq69 c vccio vccio4 4 vccio4 4 lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-97 pinout information lattice semiconductor latticeecp2 /m family data sheet w16 pb63a 4 bdq60 t pb72a 4 bdq69 t aa17 pb63b 4 bdq60 c pb72b 4 bdq69 c af18 pb64a 4 bdq60 t pb73a 4 bdq69 t af19 pb64b 4 bdq60 c pb73b 4 bdq69 c gnd gndio4 - gndio4 - aa19 pb65a 4 bdq69 t pb74a 4 bdq78 t w17 pb65b 4 bdq69 c pb74b 4 bdq78 c y19 pb66a 4 bdq69 t pb75a 4 bdq78 t y17 pb66b 4 bdq69 c pb75b 4 bdq78 c af20 pb67a 4 bdq69 t pb76a 4 bdq78 t vccio vccio4 4 vccio4 4 ae20 pb67b 4 bdq69 c pb76b 4 bdq78 c aa20 pb68a 4 bdq69 t pb77a 4 bdq78 t w18 pb68b 4 bdq69 c pb77b 4 bdq78 c ad20 pb69a 4 bdqs69 t pb78a 4 bdqs78 t gnd gndio4 - gndio4 - ae21 pb69b 4 bdq69 c pb78b 4 bdq78 c af21 pb70a 4 bdq69 t pb79a 4 bdq78 t af22 pb70b 4 bdq69 c pb79b 4 bdq78 c vccio vccio4 4 vccio4 4 gnd gndio4 - gndio4 - ae22 pb74a 4 bdq78 t pb92a 4 bdq96 t ad22 pb74b 4 bdq78 c pb92b 4 bdq96 c af23 pb75a 4 bdq78 t pb93a 4 bdq96 t ae23 pb75b 4 bdq78 c pb93b 4 bdq96 c ad23 pb76a 4 bdq78 t pb94a 4 bdq96 t ac23 pb76b 4 bdq78 c pb94b 4 bdq96 c vccio vccio4 4 vccio4 4 ab20 pb77a 4 bdq78 t pb95a 4 bdq96 t ac20 pb77b 4 bdq78 c pb95b 4 bdq96 c gnd gndio4 - gndio4 - ab21 pb78a 4 bdqs78 t pb96a 4 bdqs96 t ac22 pb78b 4 bdq78 c pb96b 4 bdq96 c w19 pb79a 4 bdq78 t pb97a 4 bdq96 t aa21 pb79b 4 bdq78 c pb97b 4 bdq96 c af24 pb80a 4 bdq78 t pb98a 4 bdq96 t ae24 pb80b 4 bdq78 c pb98b 4 bdq96 c vccio vccio4 4 vccio4 4 y20 pb81a 4 bdq78 t pb99a 4 bdq96 t ab22 pb81b 4 bdq78 c pb99b 4 bdq96 c y21 pb82a 4 vref2_4/bdq78 t pb100a 4 vref2_4/bdq96 t ab23 pb82b 4 vref1_4/bdq78 c pb100b 4 vref1_4/bdq96 c gnd gndio4 - gndio4 - ad24 cfg2 8 cfg2 8 w20 cfg1 8 cfg1 8 ac24 cfg0 8 cfg0 8 v19 programn 8 programn 8 lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-98 pinout information lattice semiconductor latticeecp2 /m family data sheet aa22 cclk 8 cclk 8 ab24 initn 8 initn 8 ad25 done 8 done 8 gnd gndio8 - gndio8 - w21 pr77b 8 writen c pr90b 8 writen c y22 pr77a 8 cs1n t pr90a 8 cs1n t ac25 pr76b 8 csn c pr89b 8 csn c ab25 pr76a 8 d0/spifastn t pr89a 8 d0/spifastn t vccio vccio8 8 vccio8 8 ad26 pr75b 8 d1 c pr88b 8 d1 c ac26 pr75a 8 d2 t pr88a 8 d2 t y23 pr74b 8 d3 c pr87b 8 d3 c gnd gndio8 - gndio8 - w22 pr74a 8 d4 t pr87a 8 d4 t aa25 pr73b 8 d5 c pr86b 8 d5 c ab26 pr73a 8 d6 t pr86a 8 d6 t w23 pr72b 8 d7/spid0 c pr85b 8 d7/spid0 c vccio vccio8 8 vccio8 8 v22 pr72a 8 di/csspi0n t pr85a 8 di/csspi0n t y24 pr71b 8 dout/cson c pr84b 8 dout/cson c y25 pr71a 8 busy/sispi t pr84a 8 busy/sispi t w24 pr70b 3 rdq67 c pr83b 3 rdq80 c gnd gndio3 - gndio3 - v23 pr70a 3 rdq67 t pr83a 3 rdq80 t aa26 pr69b 3 rdq67 c (lvds)* pr82b 3 rdq80 c (lvds)* y26 pr69a 3 rdq67 t (lvds)* pr82a 3 rdq80 t (lvds)* u21 pr68b 3 rdq67 c pr81b 3 rdq80 c vccio vccio3 3 vccio3 3 u19 pr68a 3 rdq67 t pr81a 3 rdq80 t w25 pr67b 3 rdq67 c (lvds)* pr80b 3 rdq80 c (lvds)* w26 pr67a 3 rdqs67 t (lvds)* pr80a 3 rdqs80 t (lvds)* gnd gndio3 - gndio3 - v24 pr66b 3 rdq67 c pr79b 3 rdq80 c v25 pr66a 3 rdq67 t pr79a 3 rdq80 t v26 pr65b 3 rdq67 c (lvds)* pr78b 3 rdq80 c (lvds)* u26 pr65a 3 rdq67 t (lvds)* pr78a 3 rdq80 t (lvds)* vccio vccio3 3 vccio3 3 u22 pr64b 3 rlm0_gpllc_fb_a/rdq67 c pr77b 3 rlm0_gpllc_fb_a/rdq80 c u23 pr64a 3 rlm0_gpllt_fb_a/rdq67 t pr77a 3 rlm0_gpllt_fb_a/rdq80 t u24 pr63b 3 rlm0_gpllc_in_a**/rdq67 c (lvds)* pr76b 3 rlm0_gpllc_in_a**/rdq80 c (lvds)* u25 pr63a 3 rlm0_gpllt_in_a**/rdq67 t (lvds) * pr76a 3 rlm0_gpllt_in_a**/rdq80 t (lvds)* r20 rlm0_pllcap 3 rlm0_pllcap 3 p18 vccpll 3 vccpll - t19 pr61b 3 rlm0_gdllc_fb_a/rdq58 c pr74b 3 rlm0_gdllc_fb_a/rdq71 c u20 pr61a 3 rlm0_gdllt_fb_a/rdq58 t pr74a 3 rlm0_gdllt_fb_a/rdq71 t gnd gndio3 - gndio3 - t25 pr60b 3 rlm0_gdllc_in_a**/rdq58 c (lvds) * pr73b 3 rlm0_gdllc_in_a**/rdq71 c (lvds)* lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-99 pinout information lattice semiconductor latticeecp2 /m family data sheet t26 pr60a 3 rlm0_gdllt_in_a**/rdq58 t (lvds) * pr73a 3 rlm0_gdllt_in_a**/rdq71 t (lvds)* t20 pr59b 3 rdq58 c pr72b 3 rdq71 c t22 pr59a 3 rdq58 t pr72a 3 rdq71 t vccio vccio3 3 vccio3 3 r26 pr58b 3 rdq58 c (lvds)* pr71b 3 rdq71 c (lvds)* r25 pr58a 3 rdqs58 t (lvds)* pr71a 3 rdqs71 t (lvds)* r22 pr57b 3 rdq58 c pr70b 3 rdq71 c gnd gndio3 - gndio3 - t21 pr57a 3 rdq58 t pr70a 3 rdq71 t p26 pr56b 3 rdq58 c (lvds)* pr69b 3 rdq71 c (lvds)* p25 pr56a 3 rdq58 t (lvds)* pr69a 3 rdq71 t (lvds)* r24 pr55b 3 rdq58 c pr68b 3 rdq71 c vccio vccio3 3 vccio3 3 r23 pr55a 3 rdq58 t pr68a 3 rdq71 t p20 pr54b 3 rdq58 c (lvds)* pr67b 3 rdq71 c (lvds)* r19 pr54a 3 rdq58 t (lvds)* pr67a 3 rdq71 t (lvds)* p21 pr53b 3 rdq50 c pr66b 3 rdq63 c gnd gndio3 - gndio3 - p19 pr53a 3 rdq50 t pr66a 3 rdq63 t p23 pr52b 3 rdq50 c (lvds)* pr65b 3 rdq63 c (lvds)* p22 pr52a 3 rdq50 t (lvds)* pr65a 3 rdq63 t (lvds)* n22 pr51b 3 rdq50 c pr64b 3 rdq63 c vccio vccio3 3 vccio3 3 r21 pr51a 3 rdq50 t pr64a 3 rdq63 t n26 pr50b 3 rdq50 c (lvds)* pr63b 3 rdq63 c (lvds)* n25 pr50a 3 rdqs50 t (lvds)* pr63a 3 rdqs63 t (lvds)* gnd gndio3 - gndio3 - n19 pr49b 3 rdq50 c pr62b 3 rdq63 c n20 pr49a 3 rdq50 t pr62a 3 rdq63 t m26 pr48b 3 rdq50 c (lvds)* pr61b 3 rdq63 c (lvds)* m25 pr48a 3 rdq50 t (lvds)* pr61a 3 rdq63 t (lvds)* vccio vccio3 3 vccio3 3 n18 pr47b 3 vref2_3/rdq50 c pr60b 3 vref2_3/rdq63 c n21 pr47a 3 vref1_3/rdq50 t pr60a 3 vref1_3/rdq63 t l26 pr46b 3 pclkc3_0/rdq50 c (lvds)* pr59b 3 pclkc3_0/rdq63 c (lvds)* l25 pr46a 3 pclkt3_0/rdq50 t (lvds)* pr59a 3 pclkt3_0/rdq63 t (lvds)* n24 pr44b 2 pclkc2_0/rdq41 c pr57b 2 pclkc2_0/rdq54 c m23 pr44a 2 pclkt2_0/rdq41 t pr57a 2 pclkt2_0/rdq54 t gnd gndio2 - gndio2 - l21 pr43b 2 rdq41 c (lvds)* pr56b 2 rdq54 c (lvds)* k22 pr43a 2 rdq41 t (lvds)* pr56a 2 rdq54 t (lvds)* m24 pr42b 2 rdq41 c pr55b 2 rdq54 c n23 pr42a 2 rdq41 t pr55a 2 rdq54 t vccio vccio2 2 vccio2 2 k26 pr41b 2 rdq41 c (lvds)* pr54b 2 rdq54 c (lvds)* k25 pr41a 2 rdqs41 t (lvds)* pr54a 2 rdqs54 t (lvds)* m20 pr40b 2 rdq41 c pr53b 2 rdq54 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-100 pinout information lattice semiconductor latticeecp2 /m family data sheet gnd gndio2 - gndio2 - m19 pr40a 2 rdq41 t pr53a 2 rdq54 t l22 pr39b 2 rdq41 c (lvds)* pr52b 2 rdq54 c (lvds)* m22 pr39a 2 rdq41 t (lvds)* pr52a 2 rdq54 t (lvds)* k21 pr38b 2 rdq41 c pr51b 2 rdq54 c vccio vccio2 2 vccio2 2 m21 pr38a 2 rdq41 t pr51a 2 rdq54 t k24 pr37b 2 rdq41 c (lvds)* pr50b 2 rdq54 c (lvds)* j24 pr37a 2 rdq41 t (lvds)* pr50a 2 rdq54 t (lvds)* gnd gndio2 - gndio2 - vccio vccio2 2 vccio2 2 l20 vccpll 2 nc - gnd gndio2 - gndio2 - j26 pr26b 2 rum0_spllc_fb_a/rdq24 c pr39b 2 rum0_spllc_fb_a/rdq37 c j25 pr26a 2 rum0_spllt_fb_a/rdq24 t pr39a 2 rum0_spllt_fb_a/rdq37 t j23 pr25b 2 rum0_spllc_in_a/rdq24 c pr38b 2 rum0_spllc_in_a/rdq37 c k23 pr25a 2 rum0_spllt_in_a/rdq24 t pr38a 2 rum0_spllt_in_a/rdq37 t vccio vccio2 2 vccio2 2 h26 pr24b 2 rdq24 c (lvds)* pr37b 2 rdq37 c (lvds)* h25 pr24a 2 rdqs24*** t (lvds)* pr37a 2 rdqs37*** t (lvds)* h24 pr23b 2 rdq24 c pr36b 2 rdq37 c gnd gndio2 - gndio2 - h23 pr23a 2 rdq24 t pr36a 2 rdq37 t vccio vccio2 2 vccio2 2 g26 pr19b 2 rdq16 c pr32b 2 rdq29 c gnd gndio2 - gndio2 - g25 pr19a 2 rdq16 t pr32a 2 rdq29 t f26 pr18b 2 rdq16 c (lvds)* pr31b 2 rdq29 c (lvds)* f25 pr18a 2 rdq16 t (lvds)* pr31a 2 rdq29 t (lvds)* k20 pr17b 2 rdq16 c pr30b 2 rdq29 c vccio vccio2 2 vccio2 2 l19 pr17a 2 rdq16 t pr30a 2 rdq29 t e26 pr16b 2 rdq16 c (lvds)* pr29b 2 rdq29 c (lvds)* e25 pr16a 2 rdqs16 t (lvds)* pr29a 2 rdqs29 t (lvds)* gnd gndio2 - gndio2 - j22 pr15b 2 rdq16 c pr28b 2 rdq29 c h22 pr15a 2 rdq16 t pr28a 2 rdq29 t g24 pr14b 2 rdq16 c (lvds)* pr27b 2 rdq29 c (lvds)* g23 pr14a 2 rdq16 t (lvds)* pr27a 2 rdq29 t (lvds)* vccio vccio2 2 vccio2 2 k19 pr13b 2 rdq16 c pr26b 2 rdq29 c j19 pr13a 2 rdq16 t pr26a 2 rdq29 t d26 pr12b 2 rdq16 c (lvds)* pr25b 2 rdq29 c (lvds)* c26 pr12a 2 rdq16 t (lvds)* pr25a 2 rdq29 t (lvds)* f22 pr11b 2 rdq8 c pr24b 2 rdq21 c e24 pr11a 2 rdq8 t pr24a 2 rdq21 t gnd gndio2 - gndio2 - lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-101 pinout information lattice semiconductor latticeecp2 /m family data sheet d25 pr10b 2 rdq8 c (lvds)* pr23b 2 rdq21 c (lvds)* c25 pr10a 2 rdq8 t (lvds)* pr23a 2 rdq21 t (lvds)* d24 pr9b 2 rdq8 c pr22b 2 rdq21 c b25 pr9a 2 rdq8 t pr22a 2 rdq21 t vccio vccio2 2 vccio2 2 h21 pr8b 2 rdq8 c (lvds)* pr21b 2 rdq21 c (lvds)* g22 pr8a 2 rdqs8 t (lvds)* pr21a 2 rdqs21 t (lvds)* b24 pr7b 2 rdq8 c pr20b 2 rdq21 c gnd gndio2 - gndio2 - c24 pr7a 2 rdq8 t pr20a 2 rdq21 t d23 pr6b 2 rdq8 c (lvds)* pr19b 2 rdq21 c (lvds)* c23 pr6a 2 rdq8 t (lvds)* pr19a 2 rdq21 t (lvds)* g21 pr5b 2 rdq8 c pr18b 2 rdq21 c vccio vccio2 2 vccio2 2 h20 pr5a 2 rdq8 t pr18a 2 rdq21 t gnd gndio2 - gndio2 - e22 pr2b 2 vref2_2 c (lvds)* pr2b 2 vref2_2 c (lvds)* f21 pr2a 2 vref1_2 t (lvds)* pr2a 2 vref1_2 t (lvds)* e23 pt82b 1 vref2_1 c pt100b 1 vref2_1 c gnd gndio1 - gndio1 - d22 pt82a 1 vref1_1 t pt100a 1 vref1_1 t g20 pt81b 1 c pt99b 1 c j18 pt81a 1 t pt99a 1 t f20 pt80b 1 c pt98b 1 c vccio vccio1 1 vccio1 1 h19 pt80a 1 t pt98a 1 t a24 pt79b 1 c pt97b 1 c a23 pt79a 1 t pt97a 1 t e21 pt78b 1 c pt96b 1 c f19 pt78a 1 t pt96a 1 t c22 pt77b 1 c pt95b 1 c gnd gndio1 - gndio1 - e20 pt77a 1 t pt95a 1 t b22 pt76b 1 c pt94b 1 c vccio vccio1 1 vccio1 1 b23 pt76a 1 t pt94a 1 t c20 pt75b 1 c pt93b 1 c d20 pt75a 1 t pt93a 1 t a22 pt74b 1 c pt92b 1 c a21 pt74a 1 t pt92a 1 t gnd gndio1 - gndio1 - e19 pt71b 1 c pt85b 1 c c19 pt71a 1 t pt85a 1 t vccio vccio1 1 vccio1 1 b21 pt70b 1 c pt79b 1 c b20 pt70a 1 t pt79a 1 t d19 pt69b 1 c pt78b 1 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-102 pinout information lattice semiconductor latticeecp2 /m family data sheet b19 pt69a 1 t pt78a 1 t gnd gndio1 - gndio1 - g17 pt68b 1 c pt77b 1 c e18 pt68a 1 t pt77a 1 t g19 pt67b 1 c pt76b 1 c f17 pt67a 1 t pt76a 1 t vccio vccio1 1 vccio1 1 a20 pt66b 1 c pt75b 1 c a19 pt66a 1 t pt75a 1 t e17 pt65b 1 c pt74b 1 c d18 pt65a 1 t pt74a 1 t b18 pt64b 1 c pt73b 1 c gnd gndio1 - gndio1 - a18 pt64a 1 t pt73a 1 t e16 pt63b 1 c pt72b 1 c g16 pt63a 1 t pt72a 1 t f16 pt62b 1 c pt71b 1 c vccio vccio1 1 vccio1 1 h18 pt62a 1 t pt71a 1 t a17 pt61b 1 c pt70b 1 c b17 pt61a 1 t pt70a 1 t c18 pt60b 1 c pt69b 1 c b16 pt60a 1 t pt69a 1 t c17 pt59b 1 c pt68b 1 c gnd gndio1 - gndio1 - d17 pt59a 1 t pt68a 1 t e15 pt58b 1 c pt67b 1 c vccio vccio1 1 vccio1 1 g15 pt58a 1 t pt67a 1 t a16 pt57b 1 c pt66b 1 c b15 pt57a 1 t pt66a 1 t d15 pt56b 1 c pt65b 1 c f15 pt56a 1 t pt65a 1 t a14 pt55b 1 c pt64b 1 c b14 pt55a 1 t pt64a 1 t gnd gndio1 - gndio1 - c15 pt54b 1 c pt63b 1 c a15 pt54a 1 t pt63a 1 t a13 pt53b 1 c pt62b 1 c b13 pt53a 1 t pt62a 1 t vccio vccio1 1 vccio1 1 h17 pt52b 1 c pt61b 1 c h15 pt52a 1 t pt61a 1 t d13 pt51b 1 c pt60b 1 c c14 pt51a 1 t pt60a 1 t gnd gndio1 - gndio1 - g14 pt50b 1 c pt59b 1 c lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-103 pinout information lattice semiconductor latticeecp2 /m family data sheet e14 pt50a 1 t pt59a 1 t a12 pt49b 1 c pt58b 1 c b12 pt49a 1 t pt58a 1 t vccio vccio1 1 vccio1 1 f14 pt48b 1 pclkc1_0 c pt57b 1 pclkc1_0 c d14 pt48a 1 pclkt1_0 t pt57a 1 pclkt1_0 t h16 xres 1 xres 1 h14 pt46b 0 pclkc0_0 c pt55b 0 pclkc0_0 c gnd gndio0 - gndio0 - h13 pt46a 0 pclkt0_0 t pt55a 0 pclkt0_0 t a11 pt45b 0 c pt54b 0 c b11 pt45a 0 t pt54a 0 t c13 pt44b 0 c pt53b 0 c vccio vccio0 0 vccio0 0 e13 pt44a 0 t pt53a 0 t d12 pt43b 0 c pt52b 0 c f13 pt43a 0 t pt52a 0 t a10 pt42b 0 c pt51b 0 c b10 pt42a 0 t pt51a 0 t c12 pt41b 0 c pt50b 0 c gnd gndio0 - gndio0 - c10 pt41a 0 t pt50a 0 t g13 pt40b 0 c pt49b 0 c vccio vccio0 0 vccio0 0 h12 pt40a 0 t pt49a 0 t a9 pt39b 0 c pt48b 0 c b9 pt39a 0 t pt48a 0 t e12 pt38b 0 c pt47b 0 c g12 pt38a 0 t pt47a 0 t a8 pt37b 0 c pt46b 0 c b8 pt37a 0 t pt46a 0 t gnd gndio0 - gndio0 - e11 pt36b 0 c pt45b 0 c c9 pt36a 0 t pt45a 0 t a7 pt35b 0 c pt44b 0 c b7 pt35a 0 t pt44a 0 t vccio vccio0 0 vccio0 0 f12 pt34b 0 c pt43b 0 c d10 pt34a 0 t pt43a 0 t h11 pt33b 0 c pt42b 0 c g11 pt33a 0 t pt42a 0 t gnd gndio0 - gndio0 - a6 pt32b 0 c pt41b 0 c b6 pt32a 0 t pt41a 0 t d8 pt31b 0 c pt40b 0 c c8 pt31a 0 t pt40a 0 t vccio vccio0 0 vccio0 0 lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-104 pinout information lattice semiconductor latticeecp2 /m family data sheet f11 pt30b 0 c pt39b 0 c e10 pt30a 0 t pt39a 0 t e9 pt29b 0 c pt38b 0 c d9 pt29a 0 t pt38a 0 t g10 pt28b 0 c pt37b 0 c gnd gndio0 - gndio0 - h10 pt28a 0 t pt37a 0 t a5 pt27b 0 c pt36b 0 c b5 pt27a 0 t pt36a 0 t c7 pt26b 0 c pt35b 0 c vccio vccio0 0 vccio0 0 d7 pt26a 0 t pt35a 0 t e8 pt25b 0 c pt34b 0 c f10 pt25a 0 t pt34a 0 t f8 pt24b 0 c pt33b 0 c h9 pt24a 0 t pt33a 0 t c5 pt23b 0 c pt32b 0 c gnd gndio0 - gndio0 - d5 pt23a 0 t pt32a 0 t b4 pt22b 0 pt31b 0 vccio vccio0 0 vccio0 0 gnd gndio0 - gndio0 - vccio vccio0 0 vccio0 0 gnd gndio0 - gndio0 - vccio vccio0 0 vccio0 0 c4 pt10b 0 c pt10b 0 c gnd gndio0 - gndio0 - c3 pt10a 0 t pt10a 0 t a4 pt9b 0 c pt9b 0 c a3 pt9a 0 t pt9a 0 t b3 pt8b 0 c pt8b 0 c vccio vccio0 0 vccio0 0 b2 pt8a 0 t pt8a 0 t d4 pt7b 0 c pt7b 0 c d3 pt7a 0 t pt7a 0 t c2 pt6b 0 c pt6b 0 c c1 pt6a 0 t pt6a 0 t g8 pt5b 0 c pt5b 0 c gnd gndio0 - gndio0 - g7 pt5a 0 t pt5a 0 t e7 pt4b 0 c pt4b 0 c vccio vccio0 0 vccio0 0 f7 pt4a 0 t pt4a 0 t e6 pt3b 0 c pt3b 0 c e5 pt3a 0 t pt3a 0 t g6 pt2b 0 vref2_0 c pt2b 0 vref2_0 c g5 pt2a 0 vref1_0 t pt2a 0 vref1_0 t lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-105 pinout information lattice semiconductor latticeecp2 /m family data sheet l12 vcc - vcc - l13 vcc - vcc - l14 vcc - vcc - l15 vcc - vcc - m11 vcc - vcc - m12 vcc - vcc - m15 vcc - vcc - m16 vcc - vcc - n11 vcc - vcc - n16 vcc - vcc - p11 vcc - vcc - p16 vcc - vcc - r11 vcc - vcc - r12 vcc - vcc - r15 vcc - vcc - r16 vcc - vcc - t12 vcc - vcc - t13 vcc - vcc - t14 vcc - vcc - t15 vcc - vcc - d11 vccio0 0 vccio0 0 d6 vccio0 0 vccio0 0 g9 vccio0 0 vccio0 0 k12 vccio0 0 vccio0 0 j12 vccio0 0 vccio0 0 d16 vccio1 1 vccio1 1 d21 vccio1 1 vccio1 1 g18 vccio1 1 vccio1 1 j15 vccio1 1 vccio1 1 k15 vccio1 1 vccio1 1 f23 vccio2 2 vccio2 2 j20 vccio2 2 vccio2 2 l23 vccio2 2 vccio2 2 m17 vccio2 2 vccio2 2 m18 vccio2 2 vccio2 2 aa23 vccio3 3 vccio3 3 r17 vccio3 3 vccio3 3 r18 vccio3 3 vccio3 3 t23 vccio3 3 vccio3 3 v20 vccio3 3 vccio3 3 ac16 vccio4 4 vccio4 4 ac21 vccio4 4 vccio4 4 u15 vccio4 4 vccio4 4 v15 vccio4 4 vccio4 4 y18 vccio4 4 vccio4 4 ac11 vccio5 5 vccio5 5 ac6 vccio5 5 vccio5 5 lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-106 pinout information lattice semiconductor latticeecp2 /m family data sheet u12 vccio5 5 vccio5 5 v12 vccio5 5 vccio5 5 y9 vccio5 5 vccio5 5 aa4 vccio6 6 vccio6 6 r10 vccio6 6 vccio6 6 r9 vccio6 6 vccio6 6 t4 vccio6 6 vccio6 6 v7 vccio6 6 vccio6 6 f4 vccio7 7 vccio7 7 j7 vccio7 7 vccio7 7 l4 vccio7 7 vccio7 7 m10 vccio7 7 vccio7 7 m9 vccio7 7 vccio7 7 ae25 vccio8 8 vccio8 8 v18 vccio8 8 vccio8 8 j10 vccaux - vccaux - j11 vccaux - vccaux - j16 vccaux - vccaux - j17 vccaux - vccaux - k18 vccaux - vccaux - k9 vccaux - vccaux - l18 vccaux - vccaux - l9 vccaux - vccaux - t18 vccaux - vccaux - t9 vccaux - vccaux - u18 vccaux - vccaux - u9 vccaux - vccaux - v10 vccaux - vccaux - v11 vccaux - vccaux - v16 vccaux - vccaux - v17 vccaux - vccaux - a2 gnd - gnd - a25 gnd - gnd - aa18 gnd - gnd - aa24 gnd - gnd - aa3 gnd - gnd - aa9 gnd - gnd - ad11 gnd - gnd - ad16 gnd - gnd - ad21 gnd - gnd - ad6 gnd - gnd - ae1 gnd - gnd - ae26 gnd - gnd - af2 gnd - gnd - af25 gnd - gnd - b1 gnd - gnd - b26 gnd - gnd - lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-107 pinout information lattice semiconductor latticeecp2 /m family data sheet c11 gnd - gnd - c16 gnd - gnd - c21 gnd - gnd - c6 gnd - gnd - f18 gnd - gnd - f24 gnd - gnd - f3 gnd - gnd - f9 gnd - gnd - j13 gnd - gnd - j14 gnd - gnd - j21 gnd - gnd - j6 gnd - gnd - k10 gnd - gnd - k11 gnd - gnd - k13 gnd - gnd - k14 gnd - gnd - k16 gnd - gnd - k17 gnd - gnd - l10 gnd - gnd - l11 gnd - gnd - l16 gnd - gnd - l17 gnd - gnd - l24 gnd - gnd - l3 gnd - gnd - m13 gnd - gnd - m14 gnd - gnd - n10 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n14 gnd - gnd - n15 gnd - gnd - n17 gnd - gnd - p10 gnd - gnd - p12 gnd - gnd - p13 gnd - gnd - p14 gnd - gnd - p15 gnd - gnd - p17 gnd - gnd - r13 gnd - gnd - r14 gnd - gnd - t10 gnd - gnd - t11 gnd - gnd - t16 gnd - gnd - t17 gnd - gnd - t24 gnd - gnd - t3 gnd - gnd - u10 gnd - gnd - lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-108 pinout information lattice semiconductor latticeecp2 /m family data sheet u11 gnd - gnd - u13 gnd - gnd - u14 gnd - gnd - u16 gnd - gnd - u17 gnd - gnd - v13 gnd - gnd - v14 gnd - gnd - v21 gnd - gnd - v6 gnd - gnd - m3 nc - nc - n6 nc - nc - p24 nc - nc - * supports true lvds. other differential si gnals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. ***due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the substr ate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2-50e/se and lfe2-70e/se logic signal connections: 672 fpbga lfe2-50e/se lfe2-70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-109 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2-70e/se logic signal connections: 900 fpbga lfe2-70e/se ball number ball/pad function bank dual function differential vccio vccio7 7 f4 pl2a 7 vref2_7 t (lvds)* f3 pl2b 7 vref1_7 c (lvds)* h4 pl3a 7 t g5 pl3b 7 c gnd gndio7 - d2 pl4a 7 t (lvds)* d1 pl4b 7 c (lvds)* e2 pl5a 7 t vccio vccio7 7 e1 pl5b 7 c gnd gndio7 - vccio vccio7 7 f1 pl14a 7 lum1_spllt_in_a/ldq12 t (lvds)* f2 pl14b 7 lum1_spllc_in_a/ldq12 c (lvds)* g1 pl15a 7 lum1_spllt_fb_a/ldq12 t g2 pl15b 7 lum1_spllc_fb_a/ldq12 c gnd gndio7 - h8 pl18a 7 ldq21 t h6 pl18b 7 ldq21 c vccio vccio7 7 g4 pl19a 7 ldq21 t (lvds)* g3 pl19b 7 ldq21 c (lvds)* h7 pl20a 7 ldq21 t h5 pl20b 7 ldq21 c gnd gndio7 - h2 pl21a 7 ldqs21 t (lvds)* h1 pl21b 7 ldq21 c (lvds)* j6 pl22a 7 ldq21 t vccio vccio7 7 j8 pl22b 7 ldq21 c j2 pl23a 7 ldq21 t (lvds)* j1 pl23b 7 ldq21 c (lvds)* j5 pl24a 7 ldq21 t gnd gndio7 - j7 pl24b 7 ldq21 c j4 pl25a 7 ldq29 t (lvds)* j3 pl25b 7 ldq29 c (lvds)* k6 pl26a 7 ldq29 t k8 pl26b 7 ldq29 c vccio vccio7 7 k2 pl27a 7 ldq29 t (lvds)* 4-110 pinout information lattice semiconductor latticeecp2 /m family data sheet k1 pl27b 7 ldq29 c (lvds)* k5 pl28a 7 ldq29 t k7 pl28b 7 ldq29 c gnd gndio7 - k4 pl29a 7 ldqs29 t (lvds)* k3 pl29b 7 ldq29 c (lvds)* l8 pl30a 7 ldq29 t vccio vccio7 7 l6 pl30b 7 ldq29 c l2 pl31a 7 ldq29 t (lvds)* l1 pl31b 7 ldq29 c (lvds)* l7 pl32a 7 ldq29 t gnd gndio7 - l5 pl32b 7 ldq29 c l4 pl33a 7 ldq37 t (lvds)* l3 pl33b 7 ldq37 c (lvds)* m8 pl34a 7 ldq37 t m6 pl34b 7 ldq37 c vccio vccio7 7 m2 pl35a 7 ldq37 t (lvds)* m1 pl35b 7 ldq37 c (lvds)* m7 pl36a 7 ldq37 t m5 pl36b 7 ldq37 c gnd gndio7 - m4 pl37a 7 ldqs37 t (lvds)* m3 pl37b 7 ldq37 c (lvds)* n6 pl38a 7 lum0_spllt_in_a/ldq37 t vccio vccio7 7 n8 pl38b 7 lum0_spllc_in_a/ldq37 c n5 pl39a 7 lum0_spllt_fb_a/ldq37 t n7 pl39b 7 lum0_spllc_fb_a/ldq37 c gnd gndio7 - vccio vccio7 7 t9 pl50a 7 ldq54 r9 pl51a 7 ldq54 t p7 pl51b 7 ldq54 c vccio vccio7 7 n2 pl52a 7 ldq54 t (lvds)* n1 pl52b 7 ldq54 c (lvds)* p6 pl53a 7 ldq54 t p5 pl53b 7 ldq54 c gnd gndio7 - p4 pl54a 7 ldqs54 t (lvds)* lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-111 pinout information lattice semiconductor latticeecp2 /m family data sheet p3 pl54b 7 ldq54 c (lvds)* r6 pl55a 7 ldq54 t vccio vccio7 7 r8 pl55b 7 ldq54 c p2 pl56a 7 ldq54 t (lvds)* p1 pl56b 7 ldq54 c (lvds)* r5 pl57a 7 pclkt7_0/ldq54 t gnd gndio7 - r7 pl57b 7 pclkc7_0/ldq54 c r4 pl59a 6 pclkt6_0/ldq63 t (lvds)* r3 pl59b 6 pclkc6_0/ldq63 c (lvds)* t5 pl60a 6 vref2_6/ldq63 t t7 pl60b 6 vref1_6/ldq63 c t3 pl61a 6 ldq63 t (lvds)* vccio vccio6 6 t4 pl61b 6 ldq63 c (lvds)* t6 pl62a 6 ldq63 t t8 pl62b 6 ldq63 c t2 pl63a 6 ldqs63 t (lvds)* gnd gndio6 - t1 pl63b 6 ldq63 c (lvds)* u7 pl64a 6 ldq63 t u5 pl64b 6 ldq63 c vccio vccio6 6 u4 pl65a 6 ldq63 t (lvds)* u3 pl65b 6 ldq63 c (lvds)* u8 pl66a 6 ldq63 t u6 pl66b 6 ldq63 c gnd gndio6 - u2 pl67a 6 ldq71 t (lvds)* u1 pl67b 6 ldq71 c (lvds)* v7 pl68a 6 ldq71 t v5 pl68b 6 ldq71 c vccio vccio6 6 v2 pl69a 6 ldq71 t (lvds)* v1 pl69b 6 ldq71 c (lvds)* v8 pl70a 6 ldq71 t v6 pl70b 6 ldq71 c gnd gndio6 - w1 pl71a 6 ldqs71 t (lvds)* w2 pl71b 6 ldq71 c (lvds)* w5 pl72a 6 ldq71 t vccio vccio6 6 lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-112 pinout information lattice semiconductor latticeecp2 /m family data sheet w7 pl72b 6 ldq71 c w4 pl73a 6 llm0_gdllt_in_a**/ldq71 t (lvds)* w3 pl73b 6 llm0_gdllc_in_a**/ldq71 c (lvds)* w6 pl74a 6 llm0_gdllt_fb_a/ldq71 t gnd gndio6 - w8 pl74b 6 llm0_gdllc_fb_d/ldq71 c y8 llm0_pllcap 6 y1 pl76a 6 llm0_gpllt_in_a**/ldq80 t (lvds)* y2 pl76b 6 llm0_gpllc_in_a**/ldq80 c (lvds)* y5 pl77a 6 llm0_gpllt_fb_a/ldq80 t y6 pl77b 6 llm0_gpllc_fb_a/ldq80 c y4 pl78a 6 ldq80 t (lvds)* vccio vccio6 6 y3 pl78b 6 ldq80 c (lvds)* aa6 pl79a 6 ldq80 t aa8 pl79b 6 ldq80 c aa2 pl80a 6 ldqs80 t (lvds)* gnd gndio6 - aa1 pl80b 6 ldq80 c (lvds)* aa7 pl81a 6 ldq80 t aa5 pl81b 6 ldq80 c vccio vccio6 6 aa4 pl82a 6 ldq80 t (lvds)* aa3 pl82b 6 ldq80 c (lvds)* ab7 pl83a 6 ldq80 t ab5 pl83b 6 ldq80 c gnd gndio6 - ab2 pl84a 6 ldq88 t (lvds)* ab1 pl84b 6 ldq88 c (lvds)* ab8 pl85a 6 ldq88 t ab6 pl85b 6 ldq88 c vccio vccio6 6 ab4 pl86a 6 ldq88 t (lvds)* ab3 pl86b 6 ldq88 c (lvds)* ac7 pl87a 6 ldq88 t ac5 pl87b 6 ldq88 c gnd gndio6 - ac2 pl88a 6 ldqs88 t (lvds)* ac1 pl88b 6 ldq88 c (lvds)* ac6 pl89a 6 ldq88 t vccio vccio6 6 ad6 pl89b 6 ldq88 c ad1 pl90a 6 ldq88 t (lvds)* lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-113 pinout information lattice semiconductor latticeecp2 /m family data sheet ad2 pl90b 6 ldq88 c (lvds)* ad7 pl91a 6 ldq88 t gnd gndio6 - ab9 pl91b 6 ldq88 c ad5 tck - ae7 tdi - ad4 tms - aa9 tdo - ad3 vccj - ac8 pb2a 5 vref2_5/bdq6 t ae8 pb2b 5 vref1_5/bdq6 c ad8 pb3a 5 bdq6 t af8 pb3b 5 bdq6 c ag7 pb4a 5 bdq6 t vccio vccio5 5 ah7 pb4b 5 bdq6 c ac9 pb5a 5 bdq6 t ae9 pb5b 5 bdq6 c ad9 pb6a 5 bdqs6 t gnd gndio5 - af9 pb6b 5 bdq6 c ab10 pb7a 5 bdq6 t aa10 pb7b 5 bdq6 c aj7 pb8a 5 bdq6 t vccio vccio5 5 ak7 pb8b 5 bdq6 c ac10 pb9a 5 bdq6 t ae10 pb9b 5 bdq6 c aj8 pb10a 5 bdq6 t gnd gndio5 - ak8 pb10b 5 bdq6 c af6 pb11a 5 bdq15 t af7 pb11b 5 bdq15 c ag5 pb12a 5 bdq15 t ah5 pb12b 5 bdq15 c ag6 pb13a 5 bdq15 t ah6 pb13b 5 bdq15 c vccio vccio5 5 aj4 pb14a 5 bdq15 t ak4 pb14b 5 bdq15 c gnd gndio5 - aj5 pb15a 5 bdqs15 t ak5 pb15b 5 bdq15 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-114 pinout information lattice semiconductor latticeecp2 /m family data sheet aj6 pb16a 5 bdq15 t ak6 pb16b 5 bdq15 c vccio vccio5 5 gnd gndio5 - ad10 pb29a 5 bdq33 t af10 pb29b 5 bdq33 c ac11 pb30a 5 bdq33 t ad11 pb30b 5 bdq33 c ag9 pb31a 5 bdq33 t ah9 pb31b 5 bdq33 c vccio vccio5 99 ae11 pb32a 5 bdq33 t ag10 pb32b 5 bdq33 c gnd gndio5 - aj9 pb33a 5 bdqs33 t ak9 pb33b 5 bdq33 c af11 pb34a 5 bdq33 t ah10 pb34b 5 bdq33 c ac12 pb35a 5 bdq33 t ae12 pb35b 5 bdq33 c vccio vccio5 5 ad12 pb36a 5 bdq33 t af12 pb36b 5 bdq33 c aj10 pb37a 5 bdq33 t ak10 pb37b 5 bdq33 c gnd gndio5 - ag11 pb38a 5 bdq42 t ah11 pb38b 5 bdq42 c ae13 pb39a 5 bdq42 t ac13 pb39b 5 bdq42 c af13 pb40a 5 bdq42 t vccio vccio5 5 ad13 pb40b 5 bdq42 c aj11 pb41a 5 bdq42 t ak11 pb41b 5 bdq42 c ad14 pb42a 5 bdqs42 t gnd gndio5 - ac14 pb42b 5 bdq42 c ag12 pb43a 5 bdq42 t ae14 pb43b 5 bdq42 c aj12 pb44a 5 bdq42 t vccio vccio5 5 ak12 pb44b 5 bdq42 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-115 pinout information lattice semiconductor latticeecp2 /m family data sheet ah12 pb45a 5 bdq42 t af14 pb45b 5 bdq42 c aj13 pb46a 5 bdq42 t gnd gndio5 - ak13 pb46b 5 bdq42 c ab15 pb47a 5 bdq51 t ad15 pb47b 5 bdq51 c ae15 pb48a 5 bdq51 t af15 pb48b 5 bdq51 c ag15 pb49a 5 bdq51 t ag14 pb49b 5 bdq51 c vccio vccio5 5 ah15 pb50a 5 bdq51 t ah14 pb50b 5 bdq51 c gnd gndio5 - aj14 pb51a 5 bdqs51 t ak14 pb51b 5 bdq51 c ad16 pb52a 5 bdq51 t af16 pb52b 5 bdq51 c aj15 pb53a 5 pclkt5_0/bdq51 t ak15 pb53b 5 pclkc5_0/bdq51 c vccio vccio5 5 gnd gndio5 - ae16 pb58a 4 pclkt4_0/bdq60 t vccio vccio4 4 ac15 pb58b 4 pclkc4_0/bdq60 c aj16 pb59a 4 bdq60 t ak16 pb59b 4 bdq60 c ac16 pb60a 4 bdqs60 t gnd gndio4 - ab16 pb60b 4 bdq60 c ah17 pb61a 4 bdq60 t ag17 pb61b 4 bdq60 c af17 pb62a 4 bdq60 t vccio vccio4 4 ad17 pb62b 4 bdq60 c ae17 pb63a 4 bdq60 t ac17 pb63b 4 bdq60 c aj17 pb64a 4 bdq60 t gnd gndio4 - ak17 pb64b 4 bdq60 c ak18 pb65a 4 bdq69 t aj18 pb65b 4 bdq69 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-116 pinout information lattice semiconductor latticeecp2 /m family data sheet ad18 pb66a 4 bdq69 t af18 pb66b 4 bdq69 c ac18 pb67a 4 bdq69 t ae18 pb67b 4 bdq69 c vccio vccio4 4 ag19 pb68a 4 bdq69 t ah19 pb68b 4 bdq69 c gnd gndio4 - ae19 pb69a 4 bdqs69 t af19 pb69b 4 bdq69 c ac19 pb70a 4 bdq69 t ad19 pb70b 4 bdq69 c aj19 pb71a 4 bdq69 t ak19 pb71b 4 bdq69 c vccio vccio4 4 af20 pb72a 4 bdq69 t ah20 pb72b 4 bdq69 c ae20 pb73a 4 bdq69 t ag20 pb73b 4 bdq69 c gnd gndio4 - ad20 pb74a 4 bdq78 t ac20 pb74b 4 bdq78 c ah21 pb75a 4 bdq78 t af21 pb75b 4 bdq78 c aj20 pb76a 4 bdq78 t vccio vccio4 4 ak20 pb76b 4 bdq78 c ag21 pb77a 4 bdq78 t ae21 pb77b 4 bdq78 c ad21 pb78a 4 bdqs78 t gnd gndio4 - ac21 pb78b 4 bdq78 c ad22 pb79a 4 bdq78 t ab21 pb79b 4 bdq78 c aj21 pb80a 4 bdq78 t vccio vccio4 4 ak21 pb80b 4 bdq78 c gnd gndio4 - vccio vccio4 4 aj25 pb87a 4 bdqs87*** t ak24 pb87b 4 bdq87 c aj24 pb88a 4 bdq87 t ak25 pb88b 4 bdq87 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-117 pinout information lattice semiconductor latticeecp2 /m family data sheet ah24 pb89a 4 bdq87 t ah25 pb89b 4 bdq87 c vccio vccio4 4 aj26 pb90a 4 bdq87 t ak26 pb90b 4 bdq87 c af25 pb91a 4 bdq87 t ag25 pb91b 4 bdq87 c gnd gndio4 - ak22 pb92a 4 bdq96 t aj22 pb92b 4 bdq96 c ae22 pb93a 4 bdq96 t af22 pb93b 4 bdq96 c ag22 pb94a 4 bdq96 t vccio vccio4 4 ah22 pb94b 4 bdq96 c ag24 pb95a 4 bdq96 t ag23 pb95b 4 bdq96 c ae23 pb96a 4 bdqs96 gnd gndio4 - ac22 pb97a 4 bdq96 aj23 pb98a 4 bdq96 t vccio vccio4 4 ak23 pb98b 4 bdq96 c ad24 pb99a 4 bdq96 t af24 pb99b 4 bdq96 c ac23 pb100a 4 vref2_4/bdq96 t gnd gndio4 - ae24 pb100b 4 vref1_4/bdq96 c ae25 cfg2 8 ab22 cfg1 8 ae26 cfg0 8 aa22 programn 8 ad25 cclk 8 ad26 initn 8 ac24 done 8 gnd gndio4 - ac25 pr90b 8 writen c ae27 pr90a 8 cs1n t ac26 pr89b 8 csn c ae28 pr89a 8 d0/spifastn t vccio vccio8 8 ad27 pr88b 8 d1 c ad28 pr88a 8 d2 t lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-118 pinout information lattice semiconductor latticeecp2 /m family data sheet ab24 pr87b 8 d3 c gnd gndio4 - ab23 pr87a 8 d4 t ab25 pr86b 8 d5 c ab26 pr86a 8 d6 t ac27 pr85b 8 d7/spid0 c vccio vccio8 8 ab27 pr85a 8 di/csspi0n t ad29 pr84b 8 dout/cson c ad30 pr84a 8 busy/sispi t aa25 pr83b 3 rdq80 c gnd gndio3 - aa23 pr83a 3 rdq80 t ac29 pr82b 3 rdq80 c (lvds)* ac30 pr82a 3 rdq80 t (lvds)* aa26 pr81b 3 rdq80 c vccio vccio3 3 aa24 pr81a 3 rdq80 t ab29 pr80b 3 rdq80 c (lvds)* ab30 pr80a 3 rdqs80 t (lvds)* gnd gndio3 - y23 pr79b 3 rdq80 c y25 pr79a 3 rdq80 t aa27 pr78b 3 rdq80 c (lvds)* aa28 pr78a 3 rdq80 t (lvds)* vccio vccio3 3 y24 pr77b 3 rlm0_gpllc_fb_a/rdq80 c y26 pr77a 3 rlm0_gpllt_fb_a/rdq80 t aa29 pr76b 3 rlm0_gpllc_in_a**/rdq80 c (lvds)* aa30 pr76a 3 rlm0_gpllt_in_a**/rdq80 t (lvds)* r22 rlm0_pllcap 3 w23 pr74b 3 rlm0_gdllc_fb_a/rdq71 c w25 pr74a 3 rlm0_gdllt_fb_a/rdq71 t gnd gndio3 - y27 pr73b 3 rlm0_gdllc_in_a**/rdq71 c (lvds)* y28 pr73a 3 rlm0_gdllt_in_a**/rdq71 t (lvds)* w24 pr72b 3 rdq71 c w26 pr72a 3 rdq71 t vccio vccio3 3 y29 pr71b 3 rdq71 c (lvds)* y30 pr71a 3 rdqs71 t (lvds)* v25 pr70b 3 rdq71 c gnd gndio3 - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-119 pinout information lattice semiconductor latticeecp2 /m family data sheet v23 pr70a 3 rdq71 t w27 pr69b 3 rdq71 c (lvds)* w28 pr69a 3 rdq71 t (lvds)* v26 pr68b 3 rdq71 c vccio vccio3 3 v24 pr68a 3 rdq71 t w29 pr67b 3 rdq71 c (lvds)* w30 pr67a 3 rdq71 t (lvds)* u25 pr66b 3 rdq63 c gnd gndio3 - u23 pr66a 3 rdq63 t v29 pr65b 3 rdq63 c (lvds)* v30 pr65a 3 rdq63 t (lvds)* u26 pr64b 3 rdq63 c vccio vccio3 3 u24 pr64a 3 rdq63 t u27 pr63b 3 rdq63 c (lvds)* u28 pr63a 3 rdqs63 t (lvds)* gnd gndio3 - t23 pr62b 3 rdq63 c t25 pr62a 3 rdq63 t u29 pr61b 3 rdq63 c (lvds)* u30 pr61a 3 rdq63 t (lvds)* vccio vccio3 3 t24 pr60b 3 vref2_3/rdq63 c t26 pr60a 3 vref1_3/rdq63 t t27 pr59b 3 pclkc3_0/rdq63 c (lvds)* t28 pr59a 3 pclkt3_0/rdq63 t (lvds)* r24 pr57b 2 pclkc2_0/rdq54 c r26 pr57a 2 pclkt2_0/rdq54 t gnd gndio2 - t29 pr56b 2 rdq54 c (lvds)* t30 pr56a 2 rdq54 t (lvds)* r23 pr55b 2 rdq54 c r25 pr55a 2 rdq54 t vccio vccio2 2 r27 pr54b 2 rdq54 c (lvds)* r28 pr54a 2 rdqs54 t (lvds)* p26 pr53b 2 rdq54 c gnd gndio2 - p24 pr53a 2 rdq54 t r29 pr52b 2 rdq54 c (lvds)* r30 pr52a 2 rdq54 t (lvds)* lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-120 pinout information lattice semiconductor latticeecp2 /m family data sheet p25 pr51b 2 rdq54 c vccio vccio2 2 p23 pr51a 2 rdq54 t p27 pr50b 2 rdq54 c (lvds)* p28 pr50a 2 rdq54 t (lvds)* gnd gndio2 - vccio vccio2 2 n24 pr39b 2 rum0_spllc_fb_a/rdq37 c n26 pr39a 2 rum0_spllt_fb_a/rdq37 t n23 pr38b 2 rum0_spllc_in_a/rdq37 c n25 pr38a 2 rum0_spllt_in_a/rdq37 t vccio vccio2 2 p29 pr37b 2 rdq37 c (lvds)* p30 pr37a 2 rdqs37 t (lvds)* m26 pr36b 2 rdq37 c gnd gndio2 - m24 pr36a 2 rdq37 t n29 pr35b 2 rdq37 c (lvds)* n30 pr35a 2 rdq37 t (lvds)* m25 pr34b 2 rdq37 c vccio vccio2 2 m23 pr34a 2 rdq37 t m27 pr33b 2 rdq37 c (lvds)* m28 pr33a 2 rdq37 t (lvds)* l26 pr32b 2 rdq29 c gnd gndio2 - l24 pr32a 2 rdq29 t m29 pr31b 2 rdq29 c (lvds)* m30 pr31a 2 rdq29 t (lvds)* l25 pr30b 2 rdq29 c vccio vccio2 2 l23 pr30a 2 rdq29 t l27 pr29b 2 rdq29 c (lvds)* l28 pr29a 2 rdqs29 t (lvds)* gnd gndio2 - k24 pr28b 2 rdq29 c k26 pr28a 2 rdq29 t l29 pr27b 2 rdq29 c (lvds)* l30 pr27a 2 rdq29 t (lvds)* vccio vccio2 2 k23 pr26b 2 rdq29 c k25 pr26a 2 rdq29 t k27 pr25b 2 rdq29 c (lvds)* lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-121 pinout information lattice semiconductor latticeecp2 /m family data sheet k28 pr25a 2 rdq29 t (lvds)* j24 pr24b 2 rdq21 c j26 pr24a 2 rdq21 t gnd gndio2 - k29 pr23b 2 rdq21 c (lvds)* k30 pr23a 2 rdq21 t (lvds)* j23 pr22b 2 rdq21 c j25 pr22a 2 rdq21 t vccio vccio2 99 j27 pr21b 2 rdq21 c (lvds)* j28 pr21a 2 rdqs21 t (lvds)* h26 pr20b 2 rdq21 c gnd gndio2 - h24 pr20a 2 rdq21 t j29 pr19b 2 rdq21 c (lvds)* j30 pr19a 2 rdq21 t (lvds)* h25 pr18b 2 rdq21 c vccio vccio2 2 h23 pr18a 2 rdq21 t g27 pr15b 2 rum1_spllc_fb_a/rdq12 c gnd gndio2 - h27 pr15a 2 rum1_spllt_fb_a/rdq12 t g29 pr14b 2 rum1_spllc_in_a/rdq12 c (lvds)* g28 pr14a 2 rum1_spllt_i n_a/rdq12 t (lvds)* vccio vccio2 2 gnd gndio2 - g26 pr6b 2 c (lvds)* g25 pr6a 2 t (lvds)* g30 pr5b 2 c f30 pr5a 2 t vccio vccio2 2 f26 pr4b 2 c (lvds)* f27 pr4a 2 t (lvds)* f29 pr3b 2 c gnd gndio2 - f28 pr3a 2 t h29 pr2b 2 vref2_2 c (lvds)* h30 pr2a 2 vref1_2 t (lvds)* vccio vccio2 2 b26 pt100b 1 vref2_1 c a26 pt100a 1 vref1_1 t gnd gndio1 - c25 pt99b 1 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-122 pinout information lattice semiconductor latticeecp2 /m family data sheet d25 pt99a 1 t j22 pt98b 1 c j21 pt98a 1 t vccio vccio1 1 b25 pt97b 1 c a25 pt97a 1 t e24 pt96b 1 c f24 pt96a 1 t gnd gndio1 - f23 pt95b 1 c h22 pt95a 1 t d24 pt94b 1 c c24 pt94a 1 t vccio vccio1 1 e23 pt93b 1 c g23 pt93a 1 t b24 pt92b 1 c a24 pt92a 1 t c27 pt91b 1 c gnd gndio1 - d27 pt91a 1 t c26 pt90b 1 c d26 pt90a 1 t a27 pt89b 1 c vccio vccio1 1 b27 pt89a 1 t a28 pt88b 1 c b28 pt88a 1 t a29 pt87b 1 c b29 pt87a 1 t gnd gndio1 - vccio vccio1 1 h21 pt80b 1 c f22 pt80a 1 t vccio vccio1 1 b23 pt79b 1 c a23 pt79a 1 t g24 pt78b 1 c e22 pt78a 1 t gnd gndio1 - d22 pt77b 1 c c22 pt77a 1 t g22 pt76b 1 c lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-123 pinout information lattice semiconductor latticeecp2 /m family data sheet e21 pt76a 1 t vccio vccio1 1 b22 pt75b 1 c a22 pt75a 1 t h20 pt74b 1 c f21 pt74a 1 t f20 pt73b 1 c gnd gndio1 - h19 pt73a 1 t d21 pt72b 1 c c21 pt72a 1 t e20 pt71b 1 c vccio vccio1 1 g21 pt71a 1 t b21 pt70b 1 c a21 pt70a 1 t f19 pt69b 1 c g20 pt69a 1 t e19 pt68b 1 c gnd gndio1 - g19 pt68a 1 t d20 pt67b 1 c vccio vccio1 1 c20 pt67a 1 t b20 pt66b 1 c a20 pt66a 1 t f18 pt65b 1 c h18 pt65a 1 t d19 pt64b 1 c c19 pt64a 1 t gnd gndio1 - g18 pt63b 1 c e18 pt63a 1 t h17 pt62b 1 c f17 pt62a 1 t vccio vccio1 1 g17 pt61b 1 c e17 pt61a 1 t b19 pt60b 1 c a19 pt60a 1 t gnd gndio1 - d17 pt59b 1 c b18 pt59a 1 t lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-124 pinout information lattice semiconductor latticeecp2 /m family data sheet c17 pt58b 1 c a18 pt58a 1 t vccio vccio1 1 h16 pt57b 1 pclkc1_0 c f16 pt57a 1 pclkt1_0 t k16 xres 1 e16 pt55b 0 pclkc0_0 c gnd gndio0 - g16 pt55a 0 pclkt0_0 t b17 pt54b 0 c a17 pt54a 0 t j15 pt53b 0 c vccio vccio0 0 j16 pt53a 0 t c16 pt52b 0 c d16 pt52a 0 t f15 pt51b 0 c h15 pt51a 0 t e15 pt50b 0 c gnd gndio0 - g15 pt50a 0 t c15 pt49b 0 c vccio vccio0 0 d15 pt49a 0 t b16 pt48b 0 c a16 pt48a 0 t e14 pt47b 0 c g14 pt47a 0 t b15 pt46b 0 c a15 pt46a 0 t gnd gndio0 - h14 pt45b 0 c f14 pt45a 0 t d14 pt44b 0 c c14 pt44a 0 t vccio vccio0 0 g13 pt43b 0 c e13 pt43a 0 t b14 pt42b 0 c a14 pt42a 0 t gnd gndio0 - h13 pt41b 0 c f13 pt41a 0 t lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-125 pinout information lattice semiconductor latticeecp2 /m family data sheet g12 pt40b 0 c e12 pt40a 0 t vccio vccio0 0 b13 pt39b 0 c a13 pt39a 0 t h12 pt38b 0 c f12 pt38a 0 t c12 pt37b 0 c gnd gndio0 - d12 pt37a 0 t b12 pt36b 0 c a12 pt36a 0 t e11 pt35b 0 c vccio vccio0 0 g11 pt35a 0 t f11 pt34b 0 c h11 pt34a 0 t c11 pt33b 0 c d11 pt33a 0 t b11 pt32b 0 c gnd gndio0 - a11 pt32a 0 t e10 pt31b 0 c vccio vccio0 0 g10 pt31a 0 t f10 pt30b 0 c h10 pt30a 0 t d10 pt29b 0 c c10 pt29a 0 t gnd gndio0 - vccio vccio0 0 a7 pt16b 0 c b7 pt16a 0 t a6 pt15b 0 c b6 pt15a 0 t c7 pt14b 0 c gnd gndio0 - d7 pt14a 0 t d8 pt13b 0 c vccio vccio0 0 e7 pt13a 0 t c6 pt12b 0 c d6 pt12a 0 t lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-126 pinout information lattice semiconductor latticeecp2 /m family data sheet c5 pt11b 0 c d5 pt11a 0 t e9 pt10b 0 c g9 pt10a 0 t gnd gndio0 - b10 pt9b 0 c a10 pt9a 0 t d9 pt8b 0 c c9 pt8a 0 t vccio vccio0 0 f9 pt7b 0 c h9 pt7a 0 t b9 pt6b 0 c a9 pt6a 0 t gnd gndio0 - e8 pt5b 0 c g8 pt5a 0 t a8 pt4b 0 c b8 pt4a 0 t vccio vccio0 0 f8 pt3b 0 c f7 pt3a 0 t j10 pt2b 0 vref2_0 c j9 pt2a 0 vref1_0 t aa11 vcc - aa20 vcc - k11 vcc - k21 vcc - k22 vcc - l11 vcc - l12 vcc - l13 vcc - l18 vcc - l19 vcc - l20 vcc - m11 vcc - m20 vcc - n11 vcc - n20 vcc - v11 vcc - v20 vcc - w11 vcc - w20 vcc - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-127 pinout information lattice semiconductor latticeecp2 /m family data sheet y10 vcc - y11 vcc - y12 vcc - y13 vcc - y18 vcc - y19 vcc - y20 vcc - j13 vccio0 0 j14 vccio0 0 k12 vccio0 0 k13 vccio0 0 k14 vccio0 0 k15 vccio0 0 j17 vccio1 1 j18 vccio1 1 j20 vccio1 1 k17 vccio1 1 k18 vccio1 1 k20 vccio1 1 l21 vccio2 2 m21 vccio2 2 m22 vccio2 2 n21 vccio2 2 n22 vccio2 2 r21 vccio2 2 u21 vccio3 3 u22 vccio3 3 v21 vccio3 3 v22 vccio3 3 w21 vccio3 3 y22 vccio3 3 aa16 vccio4 4 aa17 vccio4 4 aa18 vccio4 4 aa19 vccio4 4 ab17 vccio4 4 ab18 vccio4 4 aa12 vccio5 5 aa13 vccio5 5 aa14 vccio5 5 ab12 vccio5 5 ab13 vccio5 5 ab14 vccio5 5 lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-128 pinout information lattice semiconductor latticeecp2 /m family data sheet u10 vccio6 6 u9 vccio6 6 v10 vccio6 6 w10 vccio6 6 w9 vccio6 6 y9 vccio6 6 l10 vccio7 7 l9 vccio7 7 m10 vccio7 7 n10 vccio7 7 p10 vccio7 7 r10 vccio7 7 aa21 vccio8 8 y21 vccio8 8 aa15 vccaux - ab11 vccaux - ab19 vccaux - ab20 vccaux - j11 vccaux - j12 vccaux - j19 vccaux - k19 vccaux - l22 vccaux - m9 vccaux - n9 vccaux - p21 vccaux - p9 vccaux - t10 vccaux - t21 vccaux - v9 vccaux - w22 vccaux - a1 gnd - a30 gnd - ac28 gnd - ac3 gnd - ah13 gnd - ah18 gnd - ah23 gnd - ah28 gnd - ah3 gnd - ah8 gnd - ak1 gnd - ak30 gnd - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-129 pinout information lattice semiconductor latticeecp2 /m family data sheet c13 gnd - c18 gnd - c23 gnd - c28 gnd - c3 gnd - c8 gnd - h28 gnd - h3 gnd - l14 gnd - l15 gnd - l16 gnd - l17 gnd - m12 gnd - m13 gnd - m14 gnd - m15 gnd - m16 gnd - m17 gnd - m18 gnd - m19 gnd - n12 gnd - n13 gnd - n14 gnd - n15 gnd - n16 gnd - n17 gnd - n18 gnd - n19 gnd - n28 gnd - n3 gnd - p11 gnd - p12 gnd - p13 gnd - p14 gnd - p15 gnd - p16 gnd - p17 gnd - p18 gnd - p19 gnd - p20 gnd - r11 gnd - r12 gnd - r13 gnd - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-130 pinout information lattice semiconductor latticeecp2 /m family data sheet r14 gnd - r15 gnd - r16 gnd - r17 gnd - r18 gnd - r19 gnd - r20 gnd - t11 gnd - t12 gnd - t13 gnd - t14 gnd - t15 gnd - t16 gnd - t17 gnd - t18 gnd - t19 gnd - t20 gnd - u11 gnd - u12 gnd - u13 gnd - u14 gnd - u15 gnd - u16 gnd - u17 gnd - u18 gnd - u19 gnd - u20 gnd - v12 gnd - v13 gnd - v14 gnd - v15 gnd - v16 gnd - v17 gnd - v18 gnd - v19 gnd - v28 gnd - v3 gnd - w12 gnd - w13 gnd - w14 gnd - w15 gnd - w16 gnd - w17 gnd - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-131 pinout information lattice semiconductor latticeecp2 /m family data sheet w18 gnd - w19 gnd - y14 gnd - y15 gnd - y16 gnd - y17 gnd - a2 nc - a3 nc - a4 nc - a5 nc - ab28 nc - ac4 nc - ad23 nc - ae1 nc - ae2 nc - ae29 nc - ae3 nc - ae30 nc - ae4 nc - ae5 nc - ae6 nc - af1 nc - af2 nc - af23 nc - af26 nc - af27 nc - af28 nc - af29 nc - af3 nc - af30 nc - af4 nc - af5 nc - ag1 nc - ag13 nc - ag16 nc - ag18 nc - ag2 nc - ag26 nc - ag27 nc - ag28 nc - ag29 nc - ag3 nc - ag30 nc - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-132 pinout information lattice semiconductor latticeecp2 /m family data sheet ag4 nc - ag8 nc - ah1 nc - ah16 nc - ah2 nc - ah26 nc - ah27 nc - ah29 nc - ah30 nc - ah4 nc - aj1 nc - aj2 nc - aj27 nc - aj28 nc - aj29 nc - aj3 nc - aj30 nc - ak2 nc - ak27 nc - ak28 nc - ak29 nc - ak3 nc - b1 nc - b2 nc - b3 nc - b30 nc - b4 nc - b5 nc - c1 nc - c2 nc - c29 nc - c30 nc - c4 nc - d13 nc - d18 nc - d23 nc - d28 nc - d29 nc - d3 nc - d30 nc - d4 nc - e25 nc - e26 nc - lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-133 pinout information lattice semiconductor latticeecp2 /m family data sheet e27 nc - e28 nc - e29 nc - e3 nc - e30 nc - e4 nc - e5 nc - e6 nc - f25 nc - f5 nc - f6 nc - g6 nc - g7 nc - k10 nc - k9 nc - n27 nc - n4 nc - r1 nc - r2 nc - v27 nc - v4 nc - p22 vccpll - p8 vccpll - t22 vccpll - y7 vccpll - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. ***due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a pac kage ball or pin. lfe2-70e/se logic signal conn ections: 900 fpbga (cont.) lfe2-70e/se ball number ball/pad function bank dual function differential 4-134 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential a2 pl2a 7 ldq6 t (lvds)* pl2a 7 ldq6 t (lvds)* b2 pl2b 7 ldq6 c (lvds)* pl2b 7 ldq6 c(lvds)* d3 pl3a 7 ldq6 t pl3a 7 ldq6 t c2 pl3b 7 ldq6 c pl3b 7 ldq6 c e4 pl4a 7 ldq6 t (lvds)* pl4a 7 ldq6 t (lvds)* vccio vccio7 7 vccio7 7 e5 pl4b 7 ldq6 c (lvds)* pl4b 7 ldq6 c(lvds)* b1 pl5a 7 ldq6 t pl5a 7 ldq6 t c1 pl5b 7 ldq6 c pl5b 7 ldq6 c d2 pl6a 7 ldqs6 t (lvds)* pl6a 7 ldqs6 t (lvds)* gndio gndio7 - gndio7 - d1 pl6b 7 ldq6 c (lvds)* pl6b 7 ldq6 c(lvds)* e1 pl7a 7 ldq6 t pl7a 7 ldq6 t f1 pl7b 7 ldq6 c pl7b 7 ldq6 c vccio vccio7 7 vccio7 7 f3 pl8a 7 ldq6 t (lvds)* pl8a 7 ldq6 t (lvds)* f2 pl8b 7 ldq6 c (lvds)* pl8b 7 ldq6 c(lvds)* f6 pl9a 7 vref2_7/ldq6 t pl9a 7 vref2_7/ldq6 t f5 pl9b 7 vref1_7/ldq6 c pl9b 7 vref1_7/ldq6 c gndio gndio7 - gndio7 - g4 pl11a 7 lum0_spllt_in_a t (lvds)* pl11a 7 lum0_spllt_in_a/ldq15 t (lvds)* g3 pl11b 7 lum0_spllc_in_a c (lvds)* pl11b 7 lum0_spllc_in_a/ldq15 c(lvds)* g1 pl12a 7 lum0_spllt_fb_a t pl12a 7 lum0_spllt_fb_a/ldq15 t g2 pl12b 7 lum0_spllc_fb_a c pl12b 7 lum0_spllc_fb_a/ldq15 c h1 pl13a 7 t (lvds)* pl13a 7 ldq15 t (lvds)* vccio vccio7 7 vccio7 7 j1 pl13b 7 c (lvds)* pl13b 7 ldq15 c(lvds)* h2 pl14a 7 t pl14a 7 ldq15 t h3 pl14b 7 c pl14b 7 ldq15 c gndio gndio7 - gndio7 - vccio vccio7 7 vccio7 7 g6 pl24a 7 ldq22 t (lvds)* pl34a 7 ldq32 t (lvds)* h6 pl24b 7 ldq22 c (lvds)* pl34b 7 ldq32 c(lvds)* j2 pl25a 7 pclkt7_0/ldq22 t pl35a 7 pclkt7_0/ldq32 t gndio gndio7 - gndio7 - k1 pl25b 7 pclkc7_0/ldq22 c pl35b 7 pclkc7_0/ldq32 c h4 pl27a 6 pclkt6_0 t (lvds)* pl37a 6 pclkt6_0 t (lvds)* h5 pl27b 6 pclkc6_0 c (lvds)* pl37b 6 pclkc6_0 c(lvds)* j4 pl28a 6 vref2_6 t pl38a 6 vref2_6 t k4 pl28b 6 vref1_6 c pl38b 6 vref1_6 c vccio vccio6 6 vccio6 6 j6 pl31a 6 llm1_spllt_in_a t (lvds)* pl41a 6 llm2_spllt_in_a t (lvds)* gndio gndio6 - gndio6 - j5 pl31b 6 llm1_spllc_in_a c (lvds)* pl41b 6 llm2_spllc_in_a c(lvds)* k3 pl32a 6 llm1_spllt_fb_a t pl42a 6 llm2_spllt_fb_a t k2 pl32b 6 llm1_spllc_fb_a c pl42b 6 llm2_spllc_fb_a c vccio vccio6 6 vccio6 6 gndio gndio6 - gndio6 - l1 pl42a 6 llm0_gpllt_in_a t (lvds)* pl57a 6 llm0_gpllt_in_a**/ldqs57*** t (lvds)* 4-135 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio6 - gndio6 - l2 pl42b 6 llm0_gpllc_in_a c (lvds)* pl57b 6 llm0_gpllc_in_a**/ldq57 c(lvds)* l3 pl43a 6 llm0_gpllt_fb_a t pl58a 6 llm0_gpllt_fb_a/ldq57 t l4 pl43b 6 llm0_gpllc_fb_a c pl58b 6 llm0_gpllc_fb_a/ldq57 c vccio vccio6 6 vccio6 6 m1 pl44a 6 llm0_gdllt_in_a t (lvds)* pl59a 6 llm0_gdllt_in_a**/ldq57 t (lvds)* n1 pl44b 6 llm0_gdllc_in_a c (lvds)* pl59b 6 llm0_gdllc_in_a**/ldq57 c(lvds)* n2 pl45a 6 llm0_gdllt_fb_a t pl60a 6 llm0_gdllt_fb_a/ldq57 t n3 pl45b 6 llm0_gdllc_fb_a c pl60b 6 llm0_gdllc_fb_a/ldq57 c gndio gndio6 - gndio6 - m4 llm0_pllcap 6 llm0_pllcap 6 vccio vccio6 6 vccio6 6 gndio gndio6 - gndio6 - k6 tck - tck - l5 tdi- tdi- n4 tms- tms- n6 tdo- tdo- k7 vccj - vccj - m5 pb2a 5 bdq6 t pb2a 5 bdq6 t n5 pb2b 5 bdq6 c pb2b 5 bdq6 c l6 pb3a 5 bdq6 t pb3a 5 bdq6 t m6 pb3b 5 bdq6 c pb3b 5 bdq6 c p3 pb4a 5 bdq6 t pb4a 5 bdq6 t vccio vccio5 5 vccio5 5 p4 pb4b 5 bdq6 c pb4b 5 bdq6 c p2 pb5a 5 bdq6 t pb5a 5 bdq6 t p1 pb5b 5 bdq6 c pb5b 5 bdq6 c r1 pb6a 5 bdqs6 t pb6a 5 bdqs6 t gndio gndio5 - gndio5 - r2 pb6b 5 bdq6 c pb6b 5 bdq6 c r3 pb7a 5 bdq6 t pb7a 5 bdq6 t t2 pb7b 5 bdq6 c pb7b 5 bdq6 c r4 pb8a 5 bdq6 t pb8a 5 bdq6 t vccio vccio5 5 vccio5 5 t3 pb8b 5 bdq6 c pb8b 5 bdq6 c t4 pb10a 5 bdq6 t pb10a 5 bdq6 t gndio gndio5 - gndio5 - t5 pb10b 5 bdq6 c pb10b 5 bdq6 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - t6 pb16a 5 vref2_5/bdq15 t pb34a 5 vref2_5/bdq33 t r6 pb16b 5 vref1_5/bdq15 c pb34b 5 vref1_5/bdq33 c p6 pb17a 5 pclkt5_0/bdq15 t pb35a 5 pclkt5_0/bdq33 t p7 pb17b 5 pclkc5_0/bdq15 c pb35b 5 pclkc5_0/bdq33 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - t7 pb22a 4 pclkt4_0/bdq24 t pb40a 4 pclkt4_0/bdq42 t vccio vccio4 4 vccio4 4 t8 pb22b 4 pclkc4_0/bdq24 c pb40b 4 pclkc4_0/bdq42 c lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-136 pinout information lattice semiconductor latticeecp2 /m family data sheet l7 pb23a 4 vref2_4/bdq24 t pb41a 4 vref2_4/bdq42 t l8 pb23b 4 vref1_4/bdq24 c pb41b 4 vref1_4/bdq42 c gndio gndio4 - gndio4 - vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - p8 pb29a 4 bdq33 t pb47a 4 bdq51 t n8 pb29b 4 bdq33 c pb47b 4 bdq51 c r7 pb30a 4 bdq33 t pb48a 4 bdq51 t r8 pb30b 4 bdq33 c pb48b 4 bdq51 c n7 pb31a 4 bdq33 t pb49a 4 bdq51 t m8 pb31b 4 bdq33 c pb49b 4 bdq51 c vccio vccio4 4 vccio4 4 r9 pb32a 4 bdq33 t pb50a 4 bdq51 t t9 pb32b 4 bdq33 c pb50b 4 bdq51 c gndio gndio4 - gndio4 - t10 pb33a 4 bdqs33 t pb51a 4 bdqs51 t r10 pb33b 4 bdq33 c pb51b 4 bdq51 c n9 pb34a 4 bdq33 t pb52a 4 bdq51 t p10 pb34b 4 bdq33 c pb52b 4 bdq51 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - l9 pb47a 4 bdq51 t pb65a 4 bdq69 t m9 pb47b 4 bdq51 c pb65b 4 bdq69 c t11 pb49a 4 bdq51 t pb67a 4 bdq69 t r11 pb49b 4 bdq51 c pb67b 4 bdq69 c vccio vccio4 4 vccio4 4 t12 pb50a 4 bdq51 t pb68a 4 bdq69 t t13 pb50b 4 bdq51 c pb68b 4 bdq69 c gndio gndio4 - gndio4 - p11 pb51a 4 bdqs51 t pb69a 4 bdqs69 t n10 pb51b 4 bdq51 c pb69b 4 bdq69 c t14 pb52a 4 bdq51 t pb70a 4 bdq69 t r13 pb52b 4 bdq51 c pb70b 4 bdq69 c r15 pb53a 4 bdq51 t pb71a 4 bdq69 t r16 pb53b 4 bdq51 c pb71b 4 bdq69 c vccio vccio4 4 vccio4 4 r14 pb54a 4 bdq51 t pb72a 4 bdq69 t p15 pb54b 4 bdq51 c pb72b 4 bdq69 c p16 pb55a 4 bdq51 t pb73a 4 bdq69 t p14 pb55b 4 bdq51 c pb73b 4 bdq69 c gndio gndio4 - gndio4 - l11 cfg2 8 cfg2 8 l10 cfg1 8 cfg1 8 p13 cfg0 8 cfg0 8 n12 programn 8 programn 8 n11 cclk 8 cclk 8 m11 initn 8 initn 8 n13 done 8 done 8 gndio gndio8 - gndio8 - lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-137 pinout information lattice semiconductor latticeecp2 /m family data sheet m12 pr53b 8 writen c pr68b 8 writen c m13 pr53a 8 cs1n t pr68a 8 cs1n t n14 pr52b 8 csn c pr67b 8 csn c n15 pr52a 8 d0/spifastn t pr67a 8 d0/spifastn t vccio vccio8 8 vccio8 8 n16 pr51b 8 d1 c pr66b 8 d1 c m16 pr51a 8 d2 t pr66a 8 d2 t l12 pr50b 8 d3 c pr65b 8 d3 c gndio gndio8 - gndio8 - l13 pr50a 8 d4 t pr65a 8 d4 t l16 pr49b 8 d5 c pr64b 8 d5 c k16 pr49a 8 d6 t pr64a 8 d6 t l14 pr48b 8 d7/spid0 c pr63b 8 d7/spid0 c vccio vccio8 8 vccio8 8 l15 pr48a 8 di/csspi0n t pr63a 8 di/csspi0n t k13 pr47b 8 dout/cson/csspi1n c pr62b 8 dout/cson/csspi1n c k14 pr47a 8 busy/sispi t pr62a 8 busy/sispi t k11 rlm0_pllcap 3 rlm0_pllcap 3 k15 pr45b 3 rlm0_gdllc_fb_a c pr60b 3 rlm0_gdllc_fb_a/rdq57 c gndio gndio3 - gndio3 - j16 pr45a 3 rlm0_gdllt_fb_a t pr60a 3 rlm0_gdllt_fb_a/rdq57 t h16 pr44b 3 rlm0_gdllc_in_a c (lvds)* pr59b 3 rlm0_gdllc_in_a**/rdq57 c(lvds)* j15 pr44a 3 rlm0_gdllt_in_a t (lvds)* pr59a 3 rlm0_gdllt_in_a**/rdq57 t (lvds)* j14 pr43b 3 rlm0_gpllc_in_a c pr58b 3 rlm0_gpllc_in_a**/rdq57 c vccio vccio3 3 vccio3 3 j13 pr43a 3 rlm0_gpllt_in_a t pr58a 3 rlm0_gpllt_in_a**/rdq57 t h13 pr42b 3 rlm0_gpllc_fb_a c (lvds)* pr57b 3 rlm0_gpllc_fb_a/rdq57 c(lvds)* h12 pr42a 3 rlm0_gpllt_fb_a t (lvds)* pr57a 3 rlm0_gpllt_fb_a/rdqs57*** t (lvds)* gndio gndio3 - gndio3 - vccio vccio3 3 vccio3 3 g16 pr32b 3 rlm1_spllc_fb_a c pr42b 3 rlm2_spllc_fb_a c vccio vccio3 3 vccio3 3 h15 pr32a 3 rlm1_spllt_fb_a t pr42a 3 rlm2_spllt_fb_a t e16 pr31b 3 rlm1_spllc_in_a c (lvds)* pr41b 3 rlm2_spllc_in_a c(lvds)* f15 pr31a 3 rlm1_spllt_in_a t (lvds)* pr41a 3 rlm2_spllt_in_a t (lvds)* gndio gndio3 - gndio3 - vccio vccio3 3 vccio3 3 f16 pr28b 3 vref2_3 c pr38b 3 vref2_3 c g15 pr28a 3 vref1_3 t pr38a 3 vref1_3 t j11 pr27b 3 pclkc3_0 c (lvds)* pr37b 3 pclkc3_0 c(lvds)* j12 pr27a 3 pclkt3_0 t (lvds)* pr37a 3 pclkt3_0 t (lvds)* g14 pr25b 2 pclkc2_0/rdq22 c pr35b 2 pclkc2_0/rdq32 c g13 pr25a 2 pclkt2_0/rdq22 t pr35a 2 pclkt2_0/rdq32 t gndio gndio2 - gndio2 - f14 pr24b 2 rdq22 c (lvds)* pr34b 2 rdq32 c(lvds)* f13 pr24a 2 rdq22 t (lvds)* pr34a 2 rdq32 t (lvds)* vccio vccio2 2 vccio2 2 gndio gndio2 - gndio2 - h11 pr14b 2 c pr14b 2 rdq15 c lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-138 pinout information lattice semiconductor latticeecp2 /m family data sheet g11 pr14a 2 t pr14a 2 rdq15 t e13 pr13b 2 c (lvds)* pr13b 2 rdq15 c(lvds)* f12 pr13a 2 t (lvds)* pr13a 2 rdq15 t (lvds)* vccio vccio2 2 vccio2 2 f11 pr12b 2 rum0_spllc_fb_a c pr12b 2 rum0_spllc_fb_a/rdq15 c e12 pr12a 2 rum0_spllt_fb_a t pr12a 2 rum0_spllt_fb_a/rdq15 t d16 pr11b 2 rum0_spllc_in_a c (lvds)* pr11b 2 rum0_spllc_in_a/rdq15 c(lvds)* d15 pr11a 2 rum0_spllt_in_a t (lvds)* pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* c16 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 - gndio2 - b16 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 vccio2 2 f4 xres - xres - c15 urc_sq_vccrx0 12 urc_sq_vccrx0 12 a14 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b15 urc_sq_vccib0 12 urc_sq_vccib0 12 b14 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c12 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a11 urc_sq_hdoutp0 12 t urc_sq_hdoutp0 12 t a12 urc_sq_vccob0 12 urc_sq_vccob0 12 b11 urc_sq_hdoutn0 12 c urc_sq_hdoutn0 12 c c11 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b10 urc_sq_hdoutn1 12 c urc_sq_hdoutn1 12 c c10 urc_sq_vccob1 12 urc_sq_vccob1 12 a10 urc_sq_hdoutp1 12 t urc_sq_hdoutp1 12 t c14 urc_sq_vccrx1 12 urc_sq_vccrx1 12 b13 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c13 urc_sq_vccib1 12 urc_sq_vccib1 12 a13 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b9 urc_sq_vccaux33 12 urc_sq_vccaux33 12 d8 urc_sq_refclkn 12 c urc_sq_refclkn 12 c d9 urc_sq_refclkp 12 t urc_sq_refclkp 12 t c9 urc_sq_vccp 12 urc_sq_vccp 12 a5 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c5 urc_sq_vccib2 12 urc_sq_vccib2 12 b5 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c4 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a8 urc_sq_hdoutp2 12 t urc_sq_hdoutp2 12 t c8 urc_sq_vccob2 12 urc_sq_vccob2 12 b8 urc_sq_hdoutn2 12 c urc_sq_hdoutn2 12 c c7 urc_sq_vcctx2 12 urc_sq_vcctx2 12 b7 urc_sq_hdoutn3 12 c urc_sq_hdoutn3 12 c a6 urc_sq_vccob3 12 urc_sq_vccob3 12 a7 urc_sq_hdoutp3 12 t urc_sq_hdoutp3 12 t c6 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b4 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b3 urc_sq_vccib3 12 urc_sq_vccib3 12 a4 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c3 urc_sq_vccrx3 12 urc_sq_vccrx3 12 lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-139 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio1 - gndio1 - vccio vccio1 1 vccio1 1 gndio gndio0 - gndio0 - vccio vccio0 0 vccio0 0 g10 vccpll - vccpll - g7 vcc - vcc - g9 vcc - vcc - h7 vcc - vcc - j10 vcc - vcc - k10 vcc - vcc - k8 vcc - vcc - e7 vccio0 0 vccio0 0 vccio vccio0 0 vccio0 0 e10 vccio1 1 vccio1 1 vccio vccio1 1 vccio1 1 e14 vccio2 2 vccio2 2 g12 vccio2 2 vccio2 2 vccio vccio2 2 vccio2 2 k12 vccio3 3 vccio3 3 m14 vccio3 3 vccio3 3 vccio vccio3 3 vccio3 3 m10 vccio4 4 vccio4 4 p12 vccio4 4 vccio4 4 vccio vccio4 4 vccio4 4 m7 vccio5 5 vccio5 5 p5 vccio5 5 vccio5 5 vccio vccio5 5 vccio5 5 k5 vccio6 6 vccio6 6 m3 vccio6 6 vccio6 6 vccio vccio6 6 vccio6 6 e3 vccio7 7 vccio7 7 g5 vccio7 7 vccio7 7 vccio vccio7 7 vccio7 7 t15 vccio8 8 vccio8 8 vccio vccio8 8 vccio8 8 g8 vccaux - vccaux - h10 vccaux - vccaux - j7 vccaux - vccaux - k9 vccaux - vccaux - a1 gnd- gnd- a15 gnd - gnd - a16 gnd - gnd - a3 gnd- gnd- a9 gnd- gnd- b12 gnd - gnd - b6 gnd- gnd- e15 gnd - gnd - e2 gnd- gnd- h14 gnd - gnd - lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-140 pinout information lattice semiconductor latticeecp2 /m family data sheet h8 gnd- gnd- h9 gnd- gnd- j3 gnd- gnd- j8 gnd- gnd- j9 gnd- gnd- m15 gnd - gnd - m2 gnd- gnd- p9 gnd- gnd- r12 gnd - gnd - r5 gnd- gnd- t1 gnd- gnd- t16 gnd - gnd - d10 nc - nc - d11 nc - nc - d12 nc - nc - d13 nc - nc - d14 nc - nc - d4 nc - nc - d5 nc - nc - d6 nc - nc - d7 nc - nc - e11 nc - nc - e6 nc - nc - e8 nc - nc - e9 nc - nc - f10 nc - nc - f7 nc - nc - f8 nc - nc - f9 nc - nc - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. ***due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc current drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a pac kage ball or pin. lfe2m-20e/se and lfe2m-35e/se logi c signal connect ions: 256 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-141 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential d1 pl2a 7 ldq6 t (lvds)* pl2a 7 ldq6 t (lvds)* e1 pl2b 7 ldq6 c (lvds)* pl2b 7 ldq6 c (lvds)* f1 pl3a 7 ldq6 t pl3a 7 ldq6 t f2 pl3b 7 ldq6 c pl3b 7 ldq6 c f5 pl4a 7 ldq6 t (lvds)* pl4a 7 ldq6 t (lvds)* vccio vccio7 7 vccio7 7 g6 pl4b 7 ldq6 c (lvds)* pl4b 7 ldq6 c (lvds)* f4 pl5a 7 ldq6 t pl5a 7 ldq6 t f3 pl5b 7 ldq6 c pl5b 7 ldq6 c g1 pl6a 7 ldqs6 t (lvds)* pl6a 7 ldqs6 t (lvds)* gndio gndio7 - gndio7 - g2 pl6b 7 ldq6 c (lvds)* pl6b 7 ldq6 c (lvds)* h1 pl7a 7 ldq6 t pl7a 7 ldq6 t h2 pl7b 7 ldq6 c pl7b 7 ldq6 c vccio vccio7 7 vccio7 7 h7 pl8a 7 ldq6 t (lvds)* pl8a 7 ldq6 t (lvds)* h6 pl8b 7 ldq6 c (lvds)* pl8b 7 ldq6 c (lvds)* g3 pl9a 7 vref2_7/ldq6 t pl9a 7 vref2_7/ldq6 t h3 pl9b 7 vref1_7/ldq6 c pl9b 7 vref1_7/ldq6 c gndio gndio7 - gndio7 - h5 pl11a 7 lum0_spllt_in_a t (lvds)* pl11a 7 lum0_spllt_in_a/ldq15 t (lvds)* h4 pl11b 7 lum0_spllc_in_a c (lvds)* pl11b 7 lum0_spllc_in_a/ldq15 c (lvds)* j1 pl12a 7 lum0_spllt_fb_a t pl12a 7 lum0_spllt_fb_a/ldq15 t j2 pl12b 7 lum0_spllc_fb_a c pl12b 7 lum0_spllc_fb_a/ldq15 c j3 pl13a 7 t (lvds)* pl13a 7 ldq15 t (lvds)* vccio vccio7 7 vccio7 7 j4 pl13b 7 c (lvds)* pl13b 7 ldq15 c (lvds)* j7 pl14a 7 t pl14a 7 ldq15 t j6 pl14b 7 c pl14b 7 ldq15 c gndio gndio7 - gndio7 - vccio vccio7 7 vccio7 7 k1 pl18a 7 lum1_spllt_in_a/ldq22 t (lvds)* pl28a 7 lum1_spllt_in_a/ldq32 t (lvds)* k2 pl18b 7 lum1_spllc_in_a/ldq22 c (lvds)* pl28b 7 lum1_spllc_in_a/ldq32 c (lvds)* j5 pl19a 7 lum1_spllt_fb_a/ldq22 t pl29a 7 lum1_spllt_fb_a/ldq32 t k5 pl19b 7 lum1_spllc_fb_a/ldq22 c pl29b 7 lum1_spllc_fb_a/ldq32 c vccio vccio7 7 vccio7 7 k7 pl20a 7 ldq22 t (lvds)* pl30a 7 ldq32 t (lvds)* k6 pl20b 7 ldq22 c (lvds)* pl30b 7 ldq32 c (lvds)* l6 pl21a 7 ldq22 t pl31a 7 ldq32 t l7 pl21b 7 ldq22 c pl31b 7 ldq32 c gndio gndio7 - gndio7 - l1 pl22a 7 ldqs22 t (lvds)* pl32a 7 ldqs32 t (lvds)* l2 pl22b 7 ldq22 c (lvds)* pl32b 7 ldq32 c (lvds)* m7 pl23a 7 ldq22 t pl33a 7 ldq32 t vccio vccio7 7 vccio7 7 l5 pl23b 7 ldq22 c pl33b 7 ldq32 c l3 pl24a 7 ldq22 t (lvds)* pl34a 7 ldq32 t (lvds)* l4 pl24b 7 ldq22 c (lvds)* pl34b 7 ldq32 c (lvds)* m1 pl25a 7 pclkt7_0/ldq22 t pl35a 7 pclkt7_0/ldq32 t 4-142 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio7 - gndio7 - m2 pl25b 7 pclkc7_0/ldq22 c pl35b 7 pclkc7_0/ldq32 c m6 pl27a 6 pclkt6_0 t (lvds)* pl37a 6 pclkt6_0 t (lvds)* m5 pl27b 6 pclkc6_0 c (lvds)* pl37b 6 pclkc6_0 c (lvds)* m3 pl28a 6 vref2_6 t pl38a 6 vref2_6 t m4 pl28b 6 vref1_6 c pl38b 6 vref1_6 c vccio vccio6 6 vccio6 6 n7 pl31a 6 llm1_spllt_in_a t (lvds)* pl41a 6 llm2_spllt_in_a t (lvds)* gndio gndio6 - gndio6 - n6 pl31b 6 llm1_spllc_in_a c (lvds)* pl41b 6 llm2_spllc_in_a c (lvds)* n1 pl32a 6 llm1_spllt_fb_a t pl42a 6 llm2_spllt_fb_a t n2 pl32b 6 llm1_spllc_fb_a c pl42b 6 llm2_spllc_fb_a c vccio vccio6 6 vccio6 6 gndio gndio6 - gndio6 - p6 pl38a 6 ldqs38**** t (lvds)* pl48a 6 ldqs48**** t (lvds)* n5 pl38b 6 ldq38 c (lvds)* pl48b 6 ldq48 c (lvds)* p1 pl39a 6 ldq38 t pl49a 6 ldq48 t vccio vccio6 6 vccio6 6 p2 pl39b 6 ldq38 c pl49b 6 ldq48 c p3 pl40a 6 ldq38 t (lvds)* pl50a 6 ldq48 t (lvds)* p4 pl40b 6 ldq38 c (lvds)* pl50b 6 ldq48 c (lvds)* p5 pl41a 6 ldq38 t pl51a 6 ldq48 t gndio gndio6 - gndio6 - p7 pl41b 6 ldq38 c pl51b 6 ldq48 c r1 pl42a 6 llm0_gpllt_in_a** t (lvds)* pl57a 6 llm0_gpllt_in_a**/ldqs57**** t (lvds)* gndio gndio6 - gndio6 - r2 pl42b 6 llm0_gpllc_in_a** c (lvds)* pl57b 6 llm0_gpllc_in_a**/ldq57 c (lvds)* r3 pl43a 6 llm0_gpllt_fb_a t pl58a 6 llm0_gpllt_fb_a/ldq57 t r4 pl43b 6 llm0_gpllc_fb_a c pl58b 6 llm0_gpllc_fb_a/ldq57 c vccio vccio6 6 vccio6 6 r6 pl44a 6 llm0_gdllt_in_a** t (lvds)* pl59a 6 llm0_gdllt_in_a**/ldq57 t (lvds)* r5 pl44b 6 llm0_gdllc_in_a** c (lvds)* pl59b 6 llm0_gdllc_in_a**/ldq57 c (lvds)* t1 pl45a 6 llm0_gdllt_fb_a t pl60a 6 llm0_gdllt_fb_a/ldq57 t t2 pl45b 6 llm0_gdllc_fb_a c pl60b 6 llm0_gdllc_fb_a/ldq57 c gndio gndio6 - gndio6 - r7 llm0_pllcap 6 llm0_pllcap 6 t6 pl47a 6 ldq51 t (lvds)* pl62a 6 ldq66 t (lvds)* t7 pl47b 6 ldq51 c (lvds)* pl62b 6 ldq66 c (lvds)* u1 pl48a 6 ldq51 t pl63a 6 ldq66 t u2 pl48b 6 ldq51 c pl63b 6 ldq66 c vccio vccio6 6 vccio6 6 t3 pl49a 6 ldq51 t (lvds)* pl64a 6 ldq66 t (lvds)* u3 pl49b 6 ldq51 c (lvds)* pl64b 6 ldq66 c (lvds)* u6 pl50a 6 ldq51 t nc - u5 pl50b 6 ldq51 c pl65b 6 ldq66 c gndio gndio6 - gndio6 - v5 pl51a 6 ldqs51 t (lvds)* pl66a 6 ldqs66 t (lvds)* u4 pl51b 6 ldq51 c (lvds)* pl66b 6 ldq66 c (lvds)* v1 pl52a 6 ldq51 t pl67a 6 ldq66 t lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-143 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio6 6 vccio6 6 v3 pl52b 6 ldq51 c pl67b 6 ldq66 c w1 pl53a 6 ldq51 t (lvds)* pl68a 6 ldq66 t (lvds)* y1 pl53b 6 ldq51 c (lvds)* pl68b 6 ldq66 c (lvds)* aa1 pl54a 6 ldq51 t pl69a 6 ldq66 t gndio gndio6 - gndio6 - aa2 pl54b 6 ldq51 c pl69b 6 ldq66 c v4 tck - tck - y2 tdi- tdi- y3 tms- tms- w3tdo- tdo- w4 vccj - vccj - w5 pb2a 5 bdq6 t pb2a 5 bdq6 t y4 pb2b 5 bdq6 c pb2b 5 bdq6 c w6 pb3a 5 bdq6 t pb3a 5 bdq6 t v6 pb3b 5 bdq6 c pb3b 5 bdq6 c aa3 pb4a 5 bdq6 t pb4a 5 bdq6 t vccio vccio5 5 vccio5 5 ab2 pb4b 5 bdq6 c pb4b 5 bdq6 c t8 pb5a 5 bdq6 t pb5a 5 bdq6 t u7 pb5b 5 bdq6 c pb5b 5 bdq6 c u8 pb6a 5 bdqs6 t pb6a 5 bdqs6 t gndio gndio5 - gndio5 - t9 pb6b 5 bdq6 c pb6b 5 bdq6 c v8 pb7a 5 bdq6 t pb7a 5 bdq6 t w8 pb7b 5 bdq6 c pb7b 5 bdq6 c y6 pb8a 5 bdq6 t pb8a 5 bdq6 t vccio vccio5 5 vccio5 5 y5 pb8b 5 bdq6 c pb8b 5 bdq6 c ab3 pb9a 5 bdq6 t pb9a 5 bdq6 t ab4 pb9b 5 bdq6 c pb9b 5 bdq6 c ab5 pb10a 5 bdq6 t pb10a 5 bdq6 t gndio gndio5 - gndio5 - aa6 pb10b 5 bdq6 c pb10b 5 bdq6 c v9 pb13a 5 bdq15 t pb31a 5 bdq33 t u9 pb13b 5 bdq15 c pb31b 5 bdq33 c vccio vccio5 5 vccio5 5 - - - gndio5 - u10 pb14a 5 bdq15 t pb32a 5 bdq33 t t10 pb14b 5 bdq15 c pb32b 5 bdq33 c gndio gndio5 - gndio5 - w9 pb15a 5 bdqs15**** t pb33a 5 bdqs33**** t y8 pb15b 5 bdq15 c pb33b 5 bdq33 c aa7 pb16a 5 vref2_5/bdq15 t pb34a 5 vref2_5/bdq33 t y7 pb16b 5 vref1_5/bdq15 c pb34b 5 vref1_5/bdq33 c ab6 pb17a 5 pclkt5_0/bdq15 t pb35a 5 pclkt5_0/bdq33 t ab7 pb17b 5 pclkc5_0/bdq15 c pb35b 5 pclkc5_0/bdq33 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-144 pinout information lattice semiconductor latticeecp2 /m family data sheet aa8 pb22a 4 pclkt4_0/bdq24 t pb40a 4 pclkt4_0/bdq42 t vccio vccio4 4 vccio4 4 ab8 pb22b 4 pclkc4_0/bdq24 c pb40b 4 pclkc4_0/bdq42 c aa9 pb23a 4 vref2_4/bdq24 t pb41a 4 vref2_4/bdq42 t y9 pb23b 4 vref1_4/bdq24 c pb41b 4 vref1_4/bdq42 c ab9 pb24a 4 bdqs24**** t pb42a 4 bdqs42**** t gndio gndio4 - gndio4 - ab10 pb24b 4 bdq24 c pb42b 4 bdq42 c aa10 pb25a 4 bdq24 t pb43a 4 bdq42 t y11 pb25b 4 bdq24 c pb43b 4 bdq42 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - v10 pb29a 4 bdq33 t pb47a 4 bdq51 t u11 pb29b 4 bdq33 c pb47b 4 bdq51 c v11 pb30a 4 bdq33 t pb48a 4 bdq51 t w11 pb30b 4 bdq33 c pb48b 4 bdq51 c aa11 pb31a 4 bdq33 t pb49a 4 bdq51 t ab11 pb31b 4 bdq33 c pb49b 4 bdq51 c vccio vccio4 4 vccio4 4 t11 pb32a 4 bdq33 t pb50a 4 bdq51 t u12 pb32b 4 bdq33 c pb50b 4 bdq51 c gndio gndio4 - gndio4 - aa12 pb33a 4 bdqs33 t pb51a 4 bdqs51 t y12 pb33b 4 bdq33 c pb51b 4 bdq51 c v12 pb34a 4 bdq33 t pb52a 4 bdq51 t w12 pb34b 4 bdq33 c pb52b 4 bdq51 c ab12 pb35a 4 bdq33 t pb53a 4 bdq51 t aa13 pb35b 4 bdq33 c pb53b 4 bdq51 c vccio vccio4 4 vccio4 4 t12 pb36a 4 bdq33 t pb54a 4 bdq51 t u13 pb36b 4 bdq33 c pb54b 4 bdq51 c v13 pb37a 4 bdq33 t pb55a 4 bdq51 t t13 pb37b 4 bdq33 c pb55b 4 bdq51 c gndio gndio4 - gndio4 - ab13 pb38a 4 bdq42 t pb56a 4 bdq60 t ab14 pb38b 4 bdq42 c pb56b 4 bdq60 c u14 pb39a 4 bdq42 t pb57a 4 bdq60 t t14 pb39b 4 bdq42 c pb57b 4 bdq60 c aa14 pb40a 4 bdq42 t pb58a 4 bdq60 t vccio vccio4 4 vccio4 4 y14 pb40b 4 bdq42 c pb58b 4 bdq60 c w14 pb41a 4 bdq42 t pb59a 4 bdq60 t v14 pb41b 4 bdq42 c pb59b 4 bdq60 c ab15 pb42a 4 bdqs42 t pb60a 4 bdqs60 t gndio gndio4 - gndio4 - aa15 pb42b 4 bdq42 c pb60b 4 bdq60 c v15 pb43a 4 bdq42 t pb61a 4 bdq60 t u15 pb43b 4 bdq42 c pb61b 4 bdq60 c ab16 pb44a 4 bdq42 t pb62a 4 bdq60 t lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-145 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio4 4 vccio4 4 aa16 pb44b 4 bdq42 c pb62b 4 bdq60 c ab17 pb45a 4 bdq42 t pb63a 4 bdq60 t aa17 pb45b 4 bdq42 c pb63b 4 bdq60 c y15 pb46a 4 bdq42 t pb64a 4 bdq60 t gndio gndio4 - gndio4 - w15 pb46b 4 bdq42 c pb64b 4 bdq60 c ab20 pb47a 4 bdq51 t pb65a 4 bdq69 t ab21 pb47b 4 bdq51 c pb65b 4 bdq69 c aa21 pb48a 4 bdq51 t pb66a 4 bdq69 t aa20 pb48b 4 bdq51 c pb66b 4 bdq69 c ab19 pb49a 4 bdq51 t pb67a 4 bdq69 t ab18 pb49b 4 bdq51 c pb67b 4 bdq69 c vccio vccio4 4 vccio4 4 y22 pb50a 4 bdq51 t pb68a 4 bdq69 t y21 pb50b 4 bdq51 c pb68b 4 bdq69 c gndio gndio4 - gndio4 - y17 pb51a 4 bdqs51 t pb69a 4 bdqs69 t y18 pb51b 4 bdq51 c pb69b 4 bdq69 c y16 pb52a 4 bdq51 t pb70a 4 bdq69 t w17 pb52b 4 bdq51 c pb70b 4 bdq69 c y19 pb53a 4 bdq51 t pb71a 4 bdq69 t y20 pb53b 4 bdq51 c pb71b 4 bdq69 c vccio vccio4 4 vccio4 4 w19 pb54a 4 bdq51 t pb72a 4 bdq69 t w18 pb54b 4 bdq51 c pb72b 4 bdq69 c v17 pb55a 4 bdq51 t pb73a 4 bdq69 t v18 pb55b 4 bdq51 c pb73b 4 bdq69 c gndio gndio4 - gndio4 - w20 cfg2 8 cfg2 8 v20 cfg1 8 cfg1 8 v19 cfg0 8 cfg0 8 v22 programn 8 programn 8 w22 cclk 8 cclk 8 u18 initn 8 initn 8 u22 done 8 done 8 gndio gndio8 - gndio8 - u20 pr53b 8 writen*** c pr68b 8 writen*** c u21 pr53a 8 cs1n*** t pr68a 8 cs1n*** t u17 pr52b 8 csn*** c pr67b 8 csn*** c u16 pr52a 8 d0/spifastn*** t pr67a 8 d0/spifastn*** t vccio vccio8 8 vccio8 8 t16 pr51b 8 d1*** c pr66b 8 d1*** c t17 pr51a 8 d2*** t pr66a 8 d2*** t t22 pr50b 8 d3*** c pr65b 8 d3*** c gndio gndio8 - gndio8 - r22 pr50a 8 d4*** t pr65a 8 d4*** t t15 pr49b 8 d5*** c pr64b 8 d5*** c r17 pr49a 8 d6*** t pr64a 8 d6*** t lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-146 pinout information lattice semiconductor latticeecp2 /m family data sheet t20 pr48b 8 d7*** c pr63b 8 d7*** c vccio vccio8 8 vccio8 8 t21 pr48a 8 di/csspi0n*** t pr63a 8 di/csspi0n*** t r21 pr47b 8 dout/cson/csspi1n*** c pr62b 8 dout/cson/csspi1n*** c r20 pr47a 8 busy/sispi*** t pr62a 8 busy/sispi*** t r16 rlm0_pllcap 3 rlm0_pllcap 3 r18 pr45b 3 rlm0_gdllc_fb_a c pr60b 3 rlm0_gdllc_fb_a/rdq57 c gndio gndio3 - gndio3 - r19 pr45a 3 rlm0_gdllt_fb_a t pr60a 3 rlm0_gdllt_fb_a/rdq57 t p22 pr44b 3 rlm0_gdllc_in_a** c (lvds)* pr59b 3 rlm0_gdllc_in_a**/rdq57 c (lvds)* p21 pr44a 3 rlm0_gdllt_in_a** t (lvds)* pr59a 3 rlm0_gdllt_in_a**/rdq57 t (lvds)* p16 pr43b 3 rlm0_gpllc_in_a** c pr58b 3 rlm0_gpllc_in_a**/rdq57 c vccio vccio3 3 vccio3 3 p17 pr43a 3 rlm0_gpllt_in_a** t pr58a 3 rlm0_gpllt_in_a**/rdq57 t p20 pr42b 3 rlm0_gpllc_fb_a c (lvds)* pr57b 3 rlm0_gpllc_fb_a/rdq57 c (lvds)* p19 pr42a 3 rlm0_gpllt_fb_a t (lvds)* pr57a 3 rlm0_gpllt_fb_a/rdqs57**** t (lvds)* gndio gndio3 - gndio3 - --- vccio33 p18 pr41b 3 rdq38 c pr51b 3 rdq48 c n16 pr41a 3 rdq38 t pr51a 3 rdq48 t gndio gndio3 - gndio3 - n22 pr40b 3 rdq38 c (lvds)* pr50b 3 rdq48 c (lvds)* n21 pr40a 3 rdq38 t (lvds)* pr50a 3 rdq48 t (lvds)* n17 pr39b 3 rdq38 c pr49b 3 rdq48 c n18 pr39a 3 rdq38 t pr49a 3 rdq48 t vccio vccio3 3 vccio3 3 m22 pr38b 3 rdq38 c (lvds)* pr48b 3 rdq48 c (lvds)* m21 pr38a 3 rdqs38 t (lvds)* pr48a 3 rdqs48 t (lvds)* m16 pr37b 3 rdq38 c pr47b 3 rdq48 c gndio gndio3 - gndio3 - m17 pr37a 3 rdq38 t pr47a 3 rdq48 t m20 pr36b 3 rdq38 c (lvds)* pr46b 3 rdq48 c (lvds)* m19 pr36a 3 rdq38 t (lvds)* pr46a 3 rdq48 t (lvds)* m18 pr35b 3 rdq38 c pr45b 3 rdq48 c vccio vccio3 3 vccio3 3 l16 pr35a 3 rdq38 t pr45a 3 rdq48 t l22 pr34b 3 rdq38 c (lvds)* pr44b 3 rdq48 c (lvds)* l21 pr34a 3 rdq38 t (lvds)* pr44a 3 rdq48 t (lvds)* k22 pr32b 3 rlm1_spllc_fb_a c pr42b 3 rlm2_spllc_fb_a c vccio vccio3 3 vccio3 3 k21 pr32a 3 rlm1_spllt_fb_a t pr42a 3 rlm2_spllt_fb_a t l17 pr31b 3 rlm1_spllc_in_a c (lvds)* pr41b 3 rlm2_spllc_in_a c (lvds)* l18 pr31a 3 rlm1_spllt_in_a t (lvds)* pr41a 3 rlm2_spllt_in_a t (lvds)* gndio gndio3 - gndio3 - l20 pr30b 3 c pr40b 3 c l19 pr30a 3 t pr40a 3 t k16 pr29b 3 c (lvds)* pr39b 3 c (lvds)* k17 pr29a 3 t (lvds)* pr39a 3 t (lvds)* vccio vccio3 3 vccio3 3 lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-147 pinout information lattice semiconductor latticeecp2 /m family data sheet j16 pr28b 3 vref2_3 c pr38b 3 vref2_3 c k18 pr28a 3 vref1_3 t pr38a 3 vref1_3 t j22 pr27b 3 pclkc3_0 c (lvds)* pr37b 3 pclkc3_0 c (lvds)* j21 pr27a 3 pclkt3_0 t (lvds)* pr37a 3 pclkt3_0 t (lvds)* h22 pr25b 2 pclkc2_0/rdq22 c pr35b 2 pclkc2_0/rdq32 c h21 pr25a 2 pclkt2_0/rdq22 t pr35a 2 pclkt2_0/rdq32 t gndio gndio2 - gndio2 - j17 pr24b 2 rdq22 c (lvds)* pr34b 2 rdq32 c (lvds)* j18 pr24a 2 rdq22 t (lvds)* pr34a 2 rdq32 t (lvds)* j20 pr23b 2 rdq22 c pr33b 2 rdq32 c j19 pr23a 2 rdq22 t pr33a 2 rdq32 t vccio vccio2 2 vccio2 2 h16 pr22b 2 rdq22 c (lvds)* pr32b 2 rdq32 c (lvds)* h17 pr22a 2 rdqs22 t (lvds)* pr32a 2 rdqs32 t (lvds)* g22 pr21b 2 rdq22 c pr31b 2 rdq32 c gndio gndio2 - gndio2 - g21 pr21a 2 rdq22 t pr31a 2 rdq32 t h20 pr20b 2 rdq22 c (lvds)* pr30b 2 rdq32 c (lvds)* h19 pr20a 2 rdq22 t (lvds)* pr30a 2 rdq32 t (lvds)* g16 pr19b 2 rum1_spllc_fb_a/rdq22 c pr29b 2 rum1_spllc_fb_a/rdq32 c vccio vccio2 2 vccio2 2 h18 pr19a 2 rum1_spllt_fb_a/rdq22 t pr29a 2 rum1_spllt_fb_a/rdq32 t f22 pr18b 2 rum1_spllc_in_a/rdq22 c (lvds) * pr28b 2 rum1_spllc_in_a/rdq32 c (lvds)* f21 pr18a 2 rum1_spllt_in_a/rdq22 t (lvds)* pr28a 2 rum1_spllt_in_a/rdq32 t (lvds)* gndio gndio2 - - - g20 pr16b 2 c pr26b 2 rdq23 c vccio vccio2 2 - - f20 pr16a 2 t pr26a 2 rdq23 t - - - gndio2 - g17 pr15b 2 c (lvds)* pr25b 2 rdq23 c (lvds)* f17 pr15a 2 t (lvds)* pr25a 2 rdq23 t (lvds)* --- vccio22 gndio gndio2 - gndio2 - e22 pr14b 2 c pr14b 2 rdq15 c d22 pr14a 2 t pr14a 2 rdq15 t e20 pr13b 2 c (lvds)* pr13b 2 rdq15 c (lvds)* d20 pr13a 2 t (lvds)* pr13a 2 rdq15 t (lvds)* vccio vccio2 2 vccio2 2 d19 pr12b 2 rum0_spllc_fb_a c pr12b 2 rum0_spllc_fb_a/rdq15 c e19 pr12a 2 rum0_spllt_fb_a t pr12a 2 rum0_spllt_fb_a/rdq15 t f18 pr11b 2 rum0_spllc_in_a c (lvds)* pr11b 2 rum0_spllc_in_a/rdq15 c (lvds)* f19 pr11a 2 rum0_spllt_in_a t (lvds)* pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* e18 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 - gndio2 - d18 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 - - f16 xres - xres - c22 urc_sq_vccrx0 12 urc_sq_vccrx0 12 a21 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-148 pinout information lattice semiconductor latticeecp2 /m family data sheet b22 urc_sq_vccib0 12 urc_sq_vccib0 12 b21 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c19 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a18 urc_sq_hdoutp 0 12 t urc_sq_hdoutp 0 12 t a19 urc_sq_vccob0 12 urc_sq_vccob0 12 b18 urc_sq_hdoutn 0 12 c urc_sq_hdoutn 0 12 c c18 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b17 urc_sq_hdoutn 1 12 c urc_sq_hdoutn 1 12 c c17 urc_sq_vccob1 12 urc_sq_vccob1 12 a17 urc_sq_hdoutp 1 12 t urc_sq_hdoutp 1 12 t c21 urc_sq_vccrx1 12 urc_sq_vccrx1 12 b20 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c20 urc_sq_vccib1 12 urc_sq_vccib1 12 a20 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b16 urc_sq_vccaux 33 12 urc_sq_vccaux 33 12 e17 urc_sq_refclk n 12 c urc_sq_refclk n 12 c d17 urc_sq_refclk p 12 t urc_sq_refclk p 12 t c16 urc_sq_vccp 12 urc_sq_vccp 12 a12 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c12 urc_sq_vccib2 12 urc_sq_vccib2 12 b12 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c11 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a15 urc_sq_hdoutp 2 12 t urc_sq_hdoutp 2 12 t c15 urc_sq_vccob2 12 urc_sq_vccob2 12 b15 urc_sq_hdoutn 2 12 c urc_sq_hdoutn 2 12 c c14 urc_sq_vcctx2 12 urc_sq_vcctx2 12 b14 urc_sq_hdoutn 3 12 c urc_sq_hdoutn 3 12 c a13 urc_sq_vccob3 12 urc_sq_vccob3 12 a14 urc_sq_hdoutp 3 12 t urc_sq_hdoutp 3 12 t c13 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b11 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b10 urc_sq_vccib3 12 urc_sq_vccib3 12 a11 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c10 urc_sq_vccrx3 12 urc_sq_vccrx3 12 e13 pt28b 1 c pt46b 1 c d12 pt28a 1 t pt46a 1 t gndio gndio1 - gndio1 - a9 pt27b 1 c pt45b 1 c a8 pt27a 1 t pt45a 1 t a7 pt26b 1 c pt44b 1 c a6 pt26a 1 t pt44a 1 t vccio vccio1 1 vccio1 1 e12 pt25b 1 c pt43b 1 c lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-149 pinout information lattice semiconductor latticeecp2 /m family data sheet f12 pt25a 1 t pt43a 1 t a5 pt24b 1 c pt42b 1 c a4 pt24a 1 t pt42a 1 t gndio gndio1 - gndio1 - b7 pt23b 1 c pt41b 1 c b8 pt23a 1 t pt41a 1 t g11 pt22b 1 c pt40b 1 c e11 pt22a 1 t pt40a 1 t vccio vccio1 1 vccio1 1 d11 pt21b 1 vref2_1 c pt39b 1 vref2_1 c d10 pt21a 1 vref1_1 t pt39a 1 vref1_1 t f11 pt20a 1 pclkt1_0 t pt38a 1 pclkt1_0 t g10 pt20b 1 pclkc1_0 c pt38b 1 pclkc1_0 c g9 pt19b 0 pclkc0_0 c pt37b 0 pclkc0_0 c gndio gndio0 - gndio0 - f9 pt19a 0 pclkt0_0 t pt37a 0 pclkt0_0 t c9 pt18b 0 vref2_0 c pt36b 0 vref2_0 c d9 pt18a 0 vref1_0 t pt36a 0 vref1_0 t a2 pt17b 0 c pt35b 0 c vccio vccio0 0 vccio0 0 a3 pt17a 0 t pt35a 0 t b3 pt16b 0 c pt34b 0 c c4 pt16a 0 t pt34a 0 t e10 pt15b 0 c pt33b 0 c f10 pt15a 0 t pt33a 0 t c7 pt14b 0 c pt32b 0 c gndio gndio0 - gndio0 - b6 pt14a 0 t pt32a 0 t c6 pt13b 0 c pt31b 0 c vccio vccio0 0 vccio0 0 c5 pt13a 0 t pt31a 0 t c8 pt12b 0 c pt30b 0 c d8 pt12a 0 t pt30a 0 t e8 pt11b 0 c pt29b 0 c e9 pt11a 0 t pt29a 0 t - - - gndio0 - --- vccio00 f8 pt10b 0 c pt10b 0 c g8 pt10a 0 t pt10a 0 t gndio gndio0 - gndio0 - f7 pt9b 0 c pt9b 0 c g7 pt9a 0 t pt9a 0 t c3 pt8b 0 c pt8b 0 c d4 pt8a 0 t pt8a 0 t vccio vccio0 0 vccio0 0 f6 pt7b 0 c pt7b 0 c e6 pt7a 0 t pt7a 0 t e5 pt6b 0 c pt6b 0 c d6 pt6a 0 t pt6a 0 t lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-150 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio0 - gndio0 - d3 pt5b 0 c pt5b 0 c e3 pt5a 0 t pt5a 0 t d5 pt4b 0 c pt4b 0 c e4 pt4a 0 t pt4a 0 t vccio vccio0 0 vccio0 0 c2 pt3b 0 c pt3b 0 c b2 pt3a 0 t pt3a 0 t b1 pt2b 0 c pt2b 0 c c1 pt2a 0 t pt2a 0 t r8 vccpll - vccpll - h15 vccpll - vccpll - h8 vccpll - vccpll - r15 vccpll - vccpll - j10 vcc - vcc - j11 vcc - vcc - j12 vcc - vcc - j13 vcc - vcc - k14 vcc - vcc - k9 vcc - vcc - l14 vcc - vcc - l9 vcc- vcc- m14 vcc - vcc - m9 vcc- vcc- n14 vcc - vcc - n9 vcc- vcc- p10 vcc - vcc - p11 vcc - vcc - p12 vcc - vcc - p13 vcc - vcc - b5 vccio0 0 vccio0 0 b9 vccio0 0 vccio0 0 e7 vccio0 0 vccio0 0 h9 vccio0 0 vccio0 0 d13 vccio1 1 vccio1 1 e16 vccio1 1 vccio1 1 h14 vccio1 1 vccio1 1 e21 vccio2 2 vccio2 2 g18 vccio2 2 vccio2 2 j15 vccio2 2 vccio2 2 k19 vccio2 2 vccio2 2 n19 vccio3 3 vccio3 3 p15 vccio3 3 vccio3 3 t18 vccio3 3 vccio3 3 v21 vccio3 3 vccio3 3 aa18 vccio4 4 vccio4 4 r14 vccio4 4 vccio4 4 v16 vccio4 4 vccio4 4 w13 vccio4 4 vccio4 4 lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-151 pinout information lattice semiconductor latticeecp2 /m family data sheet aa5 vccio5 5 vccio5 5 r9 vccio5 5 vccio5 5 v7 vccio5 5 vccio5 5 w10 vccio5 5 vccio5 5 n4 vccio6 6 vccio6 6 p8 vccio6 6 vccio6 6 t5 vccio6 6 vccio6 6 v2 vccio6 6 vccio6 6 e2 vccio7 7 vccio7 7 g5 vccio7 7 vccio7 7 j8 vccio7 7 vccio7 7 k4 vccio7 7 vccio7 7 aa22 vccio8 8 vccio8 8 u19 vccio8 8 vccio8 8 h11 vccaux - vccaux - h12 vccaux - vccaux - l15 vccaux - vccaux - l8 vccaux - vccaux - m15 vccaux - vccaux - m8 vccaux - vccaux - r11 vccaux - vccaux - r12 vccaux - vccaux - a1 gnd- gnd- a10 gnd - gnd - a16 gnd - gnd - a22 gnd - gnd - aa19 gnd - gnd - aa4 gnd - gnd - ab1 gnd - gnd - ab22 gnd - gnd - b13 gnd - gnd - b19 gnd - gnd - b4 gnd- gnd- d16 gnd - gnd - d2 gnd- gnd- d21 gnd - gnd - d7 gnd- gnd- g19 gnd - gnd - g4 gnd - gnd - h10 gnd - gnd - h13 gnd - gnd - j14 gnd - gnd - j9 gnd- gnd- k10 gnd - gnd - k11 gnd - gnd - k12 gnd - gnd - k13 gnd - gnd - k15 gnd - gnd - k20 gnd - gnd - lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-152 pinout information lattice semiconductor latticeecp2 /m family data sheet k3 gnd- gnd- k8 gnd- gnd- l10 gnd - gnd - l11 gnd - gnd - l12 gnd - gnd - l13 gnd - gnd - m10 gnd - gnd - m11 gnd - gnd - m12 gnd - gnd - m13 gnd - gnd - n10 gnd - gnd - n11 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n15 gnd - gnd - n20 gnd - gnd - n3 gnd- gnd- n8 gnd- gnd- p14 gnd - gnd - p9 gnd- gnd- r10 gnd - gnd - r13 gnd - gnd - t19 gnd - gnd - t4 gnd- gnd- w16gnd- gnd- w2gnd- gnd- w21gnd- gnd- w7gnd- gnd- y10 gnd - gnd - y13 gnd - gnd - d15 nc - nc - g14 nc - nc - g15 nc - nc - d14 nc - nc - e15 nc - nc - e14 nc - nc - f15 nc - nc - f14 nc - nc - f13 nc - nc - g12 nc - nc - g13 nc - nc - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. ***for density migration, board design must take into account t hat these sysconfig pins are dual function for the lower density devices (ecp2m20 and ecp2m35). they can be either sy sconfig pins or general purpose i/os. these pins are dedicated sys config pins for t he higher density devices (ecp2m50, ecp2m70 and ecp2m100). ****due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between g nd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2m20e/se and lfe2m 35e/se logic signal co nnections: 484 fpbga lfe2m20e/se lfe2m35e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-153 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m50e/se logic signal connections: 484 fpbga lfe2m50e/se ball number ball/pad function bank dual function differential d1 pl2a 7 ldq6 t (lvds)* e1 pl2b 7 ldq6 c (lvds)* f1 pl3a 7 ldq6 t f2 pl3b 7 ldq6 c f5 pl4a 7 ldq6 t (lvds)* vccio vccio7 7 g6 pl4b 7 ldq6 c (lvds)* f4 pl5a 7 ldq6 t f3 pl5b 7 ldq6 c g1 pl6a 7 ldqs6 t (lvds)* gndio gndio7 - g2 pl6b 7 ldq6 c (lvds)* h1 pl7a 7 ldq6 t h2 pl7b 7 ldq6 c vccio vccio7 7 h7 pl8a 7 ldq6 t (lvds)* h6 pl8b 7 ldq6 c (lvds)* g3 pl9a 7 vref2_7/ldq6 t h3 pl9b 7 vref1_7/ldq6 c gndio gndio7 - vccio vccio7 7 h5 pl11a 7 lum0_spllt_in_a t (lvds)* h4 pl11b 7 lum0_spllc_in_a c (lvds)* j1 pl12a 7 lum0_spllt_fb_a t j2 pl12b 7 lum0_spllc_fb_a c gndio gndio7 - j3 pl13a 7 t (lvds)* j4 pl13b 7 c (lvds)* j7 pl14a 7 t vccio vccio7 7 j6 pl14b 7 c gndio gndio7 - vccio vccio7 7 k1 pl32a 7 lum3_spllt_in_a/ldq36 t (lvds)* k2 pl32b 7 lum3_spllc_in_a/ldq36 c (lvds)* j5 pl33a 7 lum3_spllt_fb_a/ldq36 t k5 pl33b 7 lum3_spllc_fb_a/ldq36 c vccio vccio7 7 k7 pl34a 7 ldq36 t (lvds)* k6 pl34b 7 ldq36 c (lvds)* l6 pl35a 7 ldq36 t l7 pl35b 7 ldq36 c 4-154 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio7 - l1 pl36a 7 ldqs36 t (lvds)* l2 pl36b 7 ldq36 c (lvds)* m7 pl37a 7 ldq36 t vccio vccio7 7 l5 pl37b 7 ldq36 c l3 pl38a 7 ldq36 t (lvds)* l4 pl38b 7 ldq36 c (lvds)* m1 pl39a 7 pclkt7_0/ldq36 t gndio gndio7 - m2 pl39b 7 pclkc7_0/ldq36 c m6 pl41a 6 pclkt6_0 t (lvds)* m5 pl41b 6 pclkc6_0 c (lvds)* m3 pl42a 6 vref2_6 t m4 pl42b 6 vref1_6 c vccio vccio6 6 n7 pl45a 6 llm3_spllt_in_a t (lvds)* gndio gndio6 - n6 pl45b 6 llm3_spllc_in_a c (lvds)* n1 pl46a 6 llm3_spllt_fb_a t n2 pl46b 6 llm3_spllc_fb_a c vccio vccio6 6 gndio gndio6 - p6 pl52a 6 ldqs52**** t (lvds)* n5 pl52b 6 ldq52 c (lvds)* p1 pl53a 6 ldq52 t vccio vccio6 6 p2 pl53b 6 ldq52 c p3 pl54a 6 ldq52 t (lvds)* p4 pl54b 6 ldq52 c (lvds)* p5 pl55a 6 ldq52 t gndio gndio6 - p7 pl55b 6 ldq52 c vccio vccio6 6 gndio gndio6 - r1 pl62a 6 llm0_gpllt_in_a** t (lvds)* gndio gndio6 - r2 pl62b 6 llm0_gpllc_in_a** c (lvds)* r3 pl63a 6 llm0_gpllt_fb_a t r4 pl63b 6 llm0_gpllc_fb_a c vccio vccio6 6 r6 pl64a 6 llm0_gdllt_in_a** t (lvds)* r5 pl64b 6 llm0_gdllc_in_a** c (lvds)* lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-155 pinout information lattice semiconductor latticeecp2 /m family data sheet t1 pl65a 6 llm0_gdllt_fb_a t t2 pl65b 6 llm0_gdllc_fb_a c gndio gndio6 - r7 llm0_pllcap 6 t6 pl67a 6 ldq71 t (lvds)* t7 pl67b 6 ldq71 c (lvds)* u1 pl68a 6 ldq71 t u2 pl68b 6 ldq71 c vccio vccio6 6 t3 pl69a 6 ldq71 t (lvds)* u3 pl69b 6 ldq71 c (lvds)* u6 pl70a 6 ldq71 t u5 pl70b 6 ldq71 c gndio gndio6 - v5 pl71a 6 ldqs71 t (lvds)* u4 pl71b 6 ldq71 c (lvds)* v1 pl72a 6 ldq71 t vccio vccio6 6 v3 pl72b 6 ldq71 c w1 pl73a 6 ldq71 t (lvds)* y1 pl73b 6 ldq71 c (lvds)* aa1 pl74a 6 ldq71 t gndio gndio6 - aa2 pl74b 6 ldq71 c v4 tck - y2 tdi - y3 tms - w3 tdo - w4 vccj - w5 pb2a 5 bdq6 t y4 pb2b 5 bdq6 c w6 pb3a 5 bdq6 t v6 pb3b 5 bdq6 c aa3 pb4a 5 bdq6 t ab2 pb4b 5 bdq6 c vccio vccio5 5 t8 pb5a 5 bdq6 t u7 pb5b 5 bdq6 c gndio gndio5 - u8 pb6a 5 bdqs6 t t9 pb6b 5 bdq6 c v8 pb7a 5 bdq6 t w8 pb7b 5 bdq6 c lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-156 pinout information lattice semiconductor latticeecp2 /m family data sheet y6 pb8a 5 bdq6 t y5 pb8b 5 bdq6 c vccio vccio5 5 ab3 pb9a 5 bdq6 t ab4 pb9b 5 bdq6 c ab5 pb10a 5 bdq6 t aa6 pb10b 5 bdq6 c gndio gndio5 - vccio vccio5 5 v9 pb40a 5 bdq42 t u9 pb40b 5 bdq42 c vccio vccio5 5 u10 pb41a 5 bdq42 t t10 pb41b 5 bdq42 c gndio gndio5 - w9 pb42a 5 bdqs42**** t y8 pb42b 5 bdq42 c aa7 pb43a 5 vref2_5/bdq42 t y7 pb43b 5 vref1_5/bdq42 c ab6 pb44a 5 pclkt5_0/bdq42 t ab7 pb44b 5 pclkc5_0/bdq42 c vccio vccio5 5 gndio gndio5 - aa8 pb49a 4 pclkt4_0/bdq51 t vccio vccio4 4 ab8 pb49b 4 pclkc4_0/bdq51 c aa9 pb50a 4 vref2_4/bdq51 t y9 pb50b 4 vref1_4/bdq51 c ab9 pb51a 4 bdqs51**** t gndio gndio4 - ab10 pb51b 4 bdq51 c aa10 pb52a 4 bdq51 t y11 pb52b 4 bdq51 c vccio vccio4 4 gndio gndio4 - v10 pb56a 4 bdq60 t u11 pb56b 4 bdq60 c v11 pb57a 4 bdq60 t w11 pb57b 4 bdq60 c aa11 pb58a 4 bdq60 t ab11 pb58b 4 bdq60 c vccio vccio4 4 t11 pb59a 4 bdq60 t lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-157 pinout information lattice semiconductor latticeecp2 /m family data sheet u12 pb59b 4 bdq60 c gndio gndio4 - aa12 pb60a 4 bdqs60 t y12 pb60b 4 bdq60 c v12 pb61a 4 bdq60 t w12 pb61b 4 bdq60 c ab12 pb62a 4 bdq60 t aa13 pb62b 4 bdq60 c vccio vccio4 4 t12 pb63a 4 bdq60 t u13 pb63b 4 bdq60 c v13 pb64a 4 bdq60 t t13 pb64b 4 bdq60 c gndio gndio4 - ab13 pb65a 4 bdq69 t ab14 pb65b 4 bdq69 c u14 pb66a 4 bdq69 t t14 pb66b 4 bdq69 c aa14 pb67a 4 bdq69 t vccio vccio4 4 y14 pb67b 4 bdq69 c w14 pb68a 4 bdq69 t v14 pb68b 4 bdq69 c ab15 pb69a 4 bdqs69 t gndio gndio4 - aa15 pb69b 4 bdq69 c v15 pb70a 4 bdq69 t u15 pb70b 4 bdq69 c ab16 pb71a 4 bdq69 t vccio vccio4 4 aa16 pb71b 4 bdq69 c ab17 pb72a 4 bdq69 t aa17 pb72b 4 bdq69 c gndio gndio4 - w20 cfg2 8 v20 cfg1 8 v19 cfg0 8 v22 programn 8 w22 cclk 8 u18 initn 8 u22 done 8 gndio gndio8 - u20 writen*** 8 lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-158 pinout information lattice semiconductor latticeecp2 /m family data sheet u21 cs1n*** 8 u17 csn*** 8 u16 d0/spifastn*** 8 vccio vccio8 8 t16 d1*** 8 t17 d2*** 8 t22 d3*** 8 gndio gndio8 - r22 d4*** 8 t15 d5*** 8 r17 d6*** 8 t20 d7*** 8 vccio vccio8 8 t21 di/csspi0n*** 8 r21 dout/cson/csspi1n*** 8 r20 busy/sispi*** 8 r16 rlm0_pllcap 3 r18 pr65b 3 rlm0_gdllc_fb_a c gndio gndio3 - r19 pr65a 3 rlm0_gdllt_fb_a t p22 pr64b 3 rlm0_gdllc_in_a** c (lvds)* p21 pr64a 3 rlm0_gdllt_in_a** t (lvds)* p16 pr63b 3 rlm0_gpllc_in_a** c vccio vccio3 3 p17 pr63a 3 rlm0_gpllt_in_a** t p20 pr62b 3 rlm0_gpllc_fb_a c (lvds)* p19 pr62a 3 rlm0_gpllt_fb_a t (lvds)* gndio gndio3 - vccio vccio3 3 p18 pr55b 3 rdq52 c n16 pr55a 3 rdq52 t gndio gndio3 - n22 pr54b 3 rdq52 c (lvds)* n21 pr54a 3 rdq52 t (lvds)* n17 pr53b 3 rdq52 c n18 pr53a 3 rdq52 t vccio vccio3 3 m22 pr52b 3 rdq52 c (lvds)* m21 pr52a 3 rdqs52 t (lvds)* m16 pr51b 3 rdq52 c gndio gndio3 - m17 pr51a 3 rdq52 t m20 pr50b 3 rdq52 c (lvds)* lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-159 pinout information lattice semiconductor latticeecp2 /m family data sheet m19 pr50a 3 rdq52 t (lvds)* m18 pr49b 3 rdq52 c vccio vccio3 3 l16 pr49a 3 rdq52 t l22 pr48b 3 rdq52 c (lvds)* l21 pr48a 3 rdq52 t (lvds)* gndio gndio3 - k22 pr46b 3 rlm3_spllc_fb_a c vccio vccio3 3 k21 pr46a 3 rlm3_spllt_fb_a t l17 pr45b 3 rlm3_spllc_in_a c (lvds)* l18 pr45a 3 rlm3_spllt_in_a t (lvds)* gndio gndio3 - l20 pr44b 3 c l19 pr44a 3 t k16 pr43b 3 c (lvds)* k17 pr43a 3 t (lvds)* vccio vccio3 3 j16 pr42b 3 vref2_3 c k18 pr42a 3 vref1_3 t j22 pr41b 3 pclkc3_0 c (lvds)* j21 pr41a 3 pclkt3_0 t (lvds)* h22 pr39b 2 pclkc2_0/rdq36 c h21 pr39a 2 pclkt2_0/rdq36 t gndio gndio2 - j17 pr38b 2 rdq36 c (lvds)* j18 pr38a 2 rdq36 t (lvds)* j20 pr37b 2 rdq36 c j19 pr37a 2 rdq36 t vccio vccio2 2 h16 pr36b 2 rdq36 c (lvds)* h17 pr36a 2 rdqs36 t (lvds)* g22 pr35b 2 rdq36 c gndio gndio2 - g21 pr35a 2 rdq36 t h20 pr34b 2 rdq36 c (lvds)* h19 pr34a 2 rdq36 t (lvds)* g16 pr33b 2 rum3_spllc_fb_a/rdq36 c vccio vccio2 2 h18 pr33a 2 rum3_spllt_fb_a/rdq36 t f22 pr32b 2 rum3_spllc_in_a/rdq36 c (lvds)* f21 pr32a 2 rum3_spllt_in_a/rdq36 t (lvds)* g20 pr30b 2 rdq27 c lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-160 pinout information lattice semiconductor latticeecp2 /m family data sheet f20 pr30a 2 rdq27 t gndio gndio2 - g17 pr29b 2 rdq27 c (lvds)* f17 pr29a 2 rdq27 t (lvds)* vccio vccio2 2 gndio gndio2 - e22 pr14b 2 c d22 pr14a 2 t vccio vccio2 - e20 pr13b 2 c (lvds)* d20 pr13a 2 t (lvds)* d19 pr12b 2 rum0_spllc_fb_a c gndio gndio2 - e19 pr12a 2 rum0_spllt_fb_a t f18 pr11b 2 rum0_spllc_in_a c (lvds)* f19 pr11a 2 rum0_spllt_in_a t (lvds)* vccio vccio2 - e18 pr9b 2 vref2_2 c gndio gndio2 - d18 pr9a 2 vref1_2 t vccio vccio2 2 f16 xres - c22 urc_sq_vccrx0 12 a21 urc_sq_hdinp0 12 t b22 urc_sq_vccib0 12 b21 urc_sq_hdinn0 12 c c19 urc_sq_vcctx0 12 a18 urc_sq_hdoutp0 12 t a19 urc_sq_vccob0 12 b18 urc_sq_hdoutn0 12 c c18 urc_sq_vcctx1 12 b17 urc_sq_hdoutn1 12 c c17 urc_sq_vccob1 12 a17 urc_sq_hdoutp1 12 t c21 urc_sq_vccrx1 12 b20 urc_sq_hdinn1 12 c c20 urc_sq_vccib1 12 a20 urc_sq_hdinp1 12 t b16 urc_sq_vccaux33 12 e17 urc_sq_refclkn 12 c d17 urc_sq_refclkp 12 t c16 urc_sq_vccp 12 a12 urc_sq_hdinp2 12 t lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-161 pinout information lattice semiconductor latticeecp2 /m family data sheet c12 urc_sq_vccib2 12 b12 urc_sq_hdinn2 12 c c11 urc_sq_vccrx2 12 a15 urc_sq_hdoutp2 12 t c15 urc_sq_vccob2 12 b15 urc_sq_hdoutn2 12 c c14 urc_sq_vcctx2 12 b14 urc_sq_hdoutn3 12 c a13 urc_sq_vccob3 12 a14 urc_sq_hdoutp3 12 t c13 urc_sq_vcctx3 12 b11 urc_sq_hdinn3 12 c b10 urc_sq_vccib3 12 a11 urc_sq_hdinp3 12 t c10 urc_sq_vccrx3 12 gndio gndio1 - vccio vccio1 1 e13 pt55b 1 c d12 pt55a 1 t gndio gndio1 - a9 pt54b 1 c a8 pt54a 1 t a7 pt53b 1 c a6 pt53a 1 t vccio vccio1 1 e12 pt52b 1 c f12 pt52a 1 t a5 pt51b 1 c a4 pt51a 1 t gndio gndio1 - b7 pt50b 1 c b8 pt50a 1 t g11 pt49b 1 c e11 pt49a 1 t vccio vccio1 1 d11 pt48b 1 vref2_1 c d10 pt48a 1 vref1_1 t g10 pt47b 1 pclkc1_0 c f11 pt47a 1 pclkt1_0 t g9 pt46b 0 pclkc0_0 c gndio gndio0 - f9 pt46a 0 pclkt0_0 t c9 pt45b 0 vref2_0 c lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-162 pinout information lattice semiconductor latticeecp2 /m family data sheet d9 pt45a 0 vref1_0 t a2 pt44b 0 c vccio vccio0 0 a3 pt44a 0 t b3 pt43b 0 c c4 pt43a 0 t e10 pt42b 0 c f10 pt42a 0 t c7 pt41b 0 c gndio gndio0 - b6 pt41a 0 t c6 pt40b 0 c vccio vccio0 0 c5 pt40a 0 t c8 pt39b 0 c d8 pt39a 0 t e8 pt38b 0 c e9 pt38a 0 t gndio gndio0 - vccio vccio0 0 f8 pt10b 0 c gndio gndio0 - g8 pt10a 0 t f7 pt9b 0 c g7 pt9a 0 t c3 pt8b 0 c vccio vccio0 0 d4 pt8a 0 t f6 pt7b 0 c e6 pt7a 0 t e5 pt6b 0 c d6 pt6a 0 t d3 pt5b 0 c gndio gndio0 - e3 pt5a 0 t d5 pt4b 0 c vccio vccio0 0 e4 pt4a 0 t c2 pt3b 0 c b2 pt3a 0 t b1 pt2b 0 c c1 pt2a 0 t j10 vcc - lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-163 pinout information lattice semiconductor latticeecp2 /m family data sheet j11 vcc - j12 vcc - j13 vcc - k14 vcc - k9 vcc - l14 vcc - l9 vcc - m14 vcc - m9 vcc - n14 vcc - n9 vcc - p10 vcc - p11 vcc - p12 vcc - p13 vcc - b5 vccio0 0 b9 vccio0 0 e7 vccio0 0 h9 vccio0 0 d13 vccio1 1 e16 vccio1 1 h14 vccio1 1 e21 vccio2 2 g18 vccio2 2 j15 vccio2 2 k19 vccio2 2 n19 vccio3 3 p15 vccio3 3 t18 vccio3 3 v21 vccio3 3 aa18 vccio4 4 r14 vccio4 4 v16 vccio4 4 w13 vccio4 4 aa5 vccio5 5 r9 vccio5 5 v7 vccio5 5 w10 vccio5 5 n4 vccio6 6 p8 vccio6 6 t5 vccio6 6 v2 vccio6 6 e2 vccio7 7 lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-164 pinout information lattice semiconductor latticeecp2 /m family data sheet g5 vccio7 7 j8 vccio7 7 k4 vccio7 7 aa22 vccio8 8 u19 vccio8 8 h11 vccaux - h12 vccaux - l15 vccaux - l8 vccaux - m15 vccaux - m8 vccaux - r11 vccaux - r12 vccaux - a1 gnd - a10 gnd - a16 gnd - a22 gnd - aa19 gnd - aa4 gnd - ab1 gnd - ab22 gnd - b13 gnd - b19 gnd - b4 gnd - d16 gnd - d2 gnd - d21 gnd - d7 gnd - g19 gnd - g4 gnd - h10 gnd - h13 gnd - j14 gnd - j9 gnd - k10 gnd - k11 gnd - k12 gnd - k13 gnd - k15 gnd - k20 gnd - k3 gnd - k8 gnd - l10 gnd - lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-165 pinout information lattice semiconductor latticeecp2 /m family data sheet l11 gnd - l12 gnd - l13 gnd - m10 gnd - m11 gnd - m12 gnd - m13 gnd - n10 gnd - n11 gnd - n12 gnd - n13 gnd - n15 gnd - n20 gnd - n3 gnd - n8 gnd - p14 gnd - p9 gnd - r10 gnd - r13 gnd - t19 gnd - t4 gnd - w16 gnd - w2 gnd - w21 gnd - w7 gnd - y10 gnd - y13 gnd - y15 nc - w15 nc - ab20 nc - ab21 nc - aa21 nc - aa20 nc - ab19 nc - ab18 nc - y22 nc - y21 nc - y17 nc - y18 nc - y16 nc - w17 nc - y19 nc - y20 nc - lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-166 pinout information lattice semiconductor latticeecp2 /m family data sheet w19 nc - w18 nc - v17 nc - v18 nc - d15 nc - g14 nc - g15 nc - d14 nc - e15 nc - e14 nc - f15 nc - f14 nc - f13 nc - g12 nc - g13 nc - h8 vccpll - h15 vccpll - r8 vccpll - r15 vccpll - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. ***for density migration, board design must ta ke into account that these sysconfig pins are dual function for the lower density devices (ecp2m20 and ecp2m35) and are dedicated pins for the hi gher density devices (ecp2m50, ecp2m70 and ecp2m100). ****due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc current drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a pac kage ball or pin. lfe2m50e/se logic signal co nnections: 484 fpbga (cont.) lfe2m50e/se ball number ball/pad function bank dual function differential 4-167 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential c2 pl2a 7 ldq6 t (lvds)* pl2a 7 ldq6 t* c1 pl2b 7 ldq6 c (lvds)* pl2b 7 ldq6 c* f6 pl3a 7 ldq6 t pl3a 7 ldq6 t h9 pl3b 7 ldq6 c pl3b 7 ldq6 c d3 pl4a 7 ldq6 t (lvds)* pl4a 7 ldq6 t* vccio vccio7 7 vccio7 7 d2 pl4b 7 ldq6 c (lvds)* pl4b 7 ldq6 c* f5 pl5a 7 ldq6 t pl5a 7 ldq6 t h8 pl5b 7 ldq6 c pl5b 7 ldq6 c e3 pl6a 7 ldqs6 t (lvds)* pl6a 7 ldqs6 t* gndio gndio7 - gndio7 - e2 pl6b 7 ldq6 c (lvds)* pl6b 7 ldq6 c* j9 pl7a 7 ldq6 t pl7a 7 ldq6 t e4 pl7b 7 ldq6 c pl7b 7 ldq6 c vccio vccio7 7 vccio7 7 e1 pl8a 7 ldq6 t (lvds)* pl8a 7 ldq6 t* d1 pl8b 7 ldq6 c (lvds)* pl8b 7 ldq6 c* j8 pl9a 7 vref2_7/ldq6 t pl9a 7 vref2_7/ldq6 t f4 pl9b 7 vref1_7/ldq6 c pl9b 7 vref1_7/ldq6 c gndio gndio7 - gndio7 - - - - vccio7 7 f3 pl11a 7 lum0_spllt_in_a/ldq15 t (lvds)* pl11a 7 lum0_spllt_in_a t* f1 pl11b 7 lum0_spllc_in_a/ldq15 c (lvds)* pl11b 7 lum0_spllc_in_a c* g6 pl12a 7 lum0_spllt_fb_a/ldq15 t pl12a 7 lum0_spllt_fb_a t k9 pl12b 7 lum0_spllc_fb_a/ldq15 c pl12b 7 lum0_spllc_fb_a c - - - gndio7 - g5 pl13a 7 ldq15 t (lvds)* pl13a 7 t* vccio vccio7 7 - - g4 pl13b 7 ldq15 c (lvds)* pl13b 7 c* h5 pl14a 7 ldq15 t pl14a 7 t - - - vccio7 7 h6 pl14b 7 ldq15 c pl14b 7 c gndio gndio7 - gndio7 - j7 pl16a 7 ldq15 t pl19a 7 t h4 pl16b 7 ldq15 c pl19b 7 c h3 pl17a 7 ldq15 t (lvds)* pl20a 7 t* vccio vccio7 7 vccio7 7 g3 pl17b 7 ldq15 c (lvds)* pl20b 7 c* gndio gndio7 - gndio7 - g1 pl19a 7 ldq23 t (lvds)* pl23a 7 ldq27 t* h1 pl19b 7 ldq23 c (lvds)* pl23b 7 ldq27 c* j3 pl20a 7 ldq23 t pl24a 7 ldq27 t j4 pl20b 7 ldq23 c pl24b 7 ldq27 c vccio vccio7 7 vccio7 7 h2 pl21a 7 ldq23 t (lvds)* pl25a 7 ldq27 t* j2 pl21b 7 ldq23 c (lvds)* pl25b 7 ldq27 c* k7 pl22a 7 ldq23 t pl26a 7 ldq27 t j6 pl22b 7 ldq23 c pl26b 7 ldq27 c gndio gndio7 - gndio7 - 4-168 pinout information lattice semiconductor latticeecp2 /m family data sheet k5 pl23a 7 ldqs23 t (lvds)* pl27a 7 ldqs27 t* l5 pl23b 7 ldq23 c (lvds)* pl27b 7 ldq27 c* k4 pl24a 7 ldq23 t pl28a 7 ldq27 t vccio vccio7 7 vccio7 7 l4 pl24b 7 ldq23 c pl28b 7 ldq27 c k3 pl25a 7 ldq23 t (lvds)* pl29a 7 ldq27 t* l3 pl25b 7 ldq23 c (lvds)* pl29b 7 ldq27 c* j1 pl26a 7 ldq23 t pl30a 7 ldq27 t gndio gndio7 - gndio7 - k2 pl26b 7 ldq23 c pl30b 7 ldq27 c k1 pl28a 7 lum1_spllt_in_a/ldq32 t (lvds)* pl32a 7 lum3_spllt_in_a/ldq36 t* l1 pl28b 7 lum1_spllc_in_a/ldq32 c (lvds)* pl32b 7 lum3_spllc_in_a/ldq36 c* k8 pl29a 7 lum1_spllt_fb_a/ldq32 t pl33a 7 lum3_spllt_fb_a/ldq36 t m5 pl29b 7 lum1_spllc_fb_a/ldq32 c pl33b 7 lum3_spllc_fb_a/ldq36 c vccio vccio7 7 vccio7 7 m4 pl30a 7 ldq32 t (lvds)* pl34a 7 ldq36 t* m3 pl30b 7 ldq32 c (lvds)* pl34b 7 ldq36 c* l8 pl31a 7 ldq32 t pl35a 7 ldq36 t m6 pl31b 7 ldq32 c pl35b 7 ldq36 c gndio gndio7 - gndio7 - m1 pl32a 7 ldqs32 t (lvds)* pl36a 7 ldqs36 t* n1 pl32b 7 ldq32 c (lvds)* pl36b 7 ldq36 c* n3 pl33a 7 ldq32 t pl37a 7 ldq36 t vccio vccio7 7 vccio7 7 n2 pl33b 7 ldq32 c pl37b 7 ldq36 c n5 pl34a 7 ldq32 t (lvds)* pl38a 7 ldq36 t* n4 pl34b 7 ldq32 c (lvds)* pl38b 7 ldq36 c* m7 pl35a 7 pclkt7_0/ldq32 t pl39a 7 pclkt7_0/ldq36 t gndio gndio7 - gndio7 - m8 pl35b 7 pclkc7_0/ldq32 c pl39b 7 pclkc7_0/ldq36 c p3 pl37a 6 pclkt6_0 t (lvds)* pl41a 6 pclkt6_0 t* p2 pl37b 6 pclkc6_0 c (lvds)* pl41b 6 pclkc6_0 c* p5 pl38a 6 vref2_6 t pl42a 6 vref2_6 t n6 pl38b 6 vref1_6 c pl42b 6 vref1_6 c p4 pl39a 6 t (lvds)* pl43a 6 t* vccio vccio6 6 vccio6 6 r3 pl39b 6 c (lvds)* pl43b 6 c* p6 pl40a 6 t pl44a 6 t n7 nc - pl44b 6 c p1 pl41a 6 llm2_spllt_in_a t (lvds)* pl45a 6 llm3_spllt_in_a t* gndio gndio6 - gndio6 - r1 pl41b 6 llm2_spllc_in_a c (lvds)* pl45b 6 llm3_spllc_in_a c* n8 pl42a 6 llm2_spllt_fb_a t pl46a 6 llm3_spllt_fb_a t r5 pl42b 6 llm2_spllc_fb_a c pl46b 6 llm3_spllc_fb_a c vccio vccio6 6 vccio6 6 t3 pl44a 6 ldq48 t (lvds)* pl48a 6 ldq52 t* t4 pl44b 6 ldq48 c (lvds)* pl48b 6 ldq52 c* p8 pl45a 6 ldq48 t pl49a 6 ldq52 t r6 pl45b 6 ldq48 c pl49b 6 ldq52 c lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-169 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio6 6 vccio6 6 t1 pl46a 6 ldq48 t (lvds)* pl50a 6 ldq52 t* u1 pl46b 6 ldq48 c (lvds)* pl50b 6 ldq52 c* r7 pl47a 6 ldq48 t pl51a 6 ldq52 t t5 pl47b 6 ldq48 c pl51b 6 ldq52 c gndio gndio6 - gndio6 - u3 pl48a 6 ldqs48 t (lvds)* pl52a 6 ldqs52 t* u4 pl48b 6 ldq48 c (lvds)* pl52b 6 ldq52 c* u5 pl49a 6 ldq48 t pl53a 6 ldq52 t vccio vccio6 6 vccio6 6 u6 pl49b 6 ldq48 c pl53b 6 ldq52 c u2 pl50a 6 ldq48 t (lvds)* pl54a 6 ldq52 t* v1 pl50b 6 ldq48 c (lvds)* pl54b 6 ldq52 c* w2 pl51a 6 ldq48 t pl55a 6 ldq52 t gndio gndio6 - gndio6 - v2 pl51b 6 ldq48 c pl55b 6 ldq52 c v4 pl55a 6 ldq57 t (lvds)* pl59a 6 t* vccio vccio6 6 vccio6 6 v3 pl55b 6 ldq57 c (lvds)* pl59b 6 c* - - - gndio6 - w4 pl57a 6 llm0_gpllt_in_a**/ldqs57**** t (lvds)* pl62a 6 llm0_gpllt_in_a t* gndio gndio6 - gndio6 - w3 pl57b 6 llm0_gpllc_in_a**/ldq57 c (lvds)* pl62b 6 llm0_gpllc_in_a c* w1 pl58a 6 llm0_gpllt_fb_a/ldq57 t pl63a 6 llm0_gpllt_fb_a t y1 pl58b 6 llm0_gpllc_fb_a/ldq57 c pl63b 6 llm0_gpllc_fb_a c vccio vccio6 6 vccio6 6 aa1 pl59a 6 llm0_gdllt_in_a**/ldq57 t (lvds)* pl64a 6 llm0_gdllt_in_a t* ab1 pl59b 6 llm0_gdllc_in_a**/ldq57 c (lvds)* pl64b 6 llm0_gdllc_in_a c* u7 pl60a 6 llm0_gdllt_fb_a/ldq57 t pl65a 6 llm0_gdllt_fb_a t v6 pl60b 6 llm0_gdllc_fb_a/ldq57 c pl65b 6 llm0_gdllc_fb_a c gndio gndio6 - gndio6 - t8 llm0_pllcap 6 llm0_pllcap 6 w5 pl62a 6 ldq66 t (lvds)* pl67a 6 ldq71 t* y4 pl62b 6 ldq66 c (lvds)* pl67b 6 ldq71 c* u8 pl63a 6 ldq66 t pl68a 6 ldq71 t w6 pl63b 6 ldq66 c pl68b 6 ldq71 c vccio vccio6 6 vccio6 6 y3 pl64a 6 ldq66 t (lvds)* pl69a 6 ldq71 t* aa3 pl64b 6 ldq66 c (lvds)* pl69b 6 ldq71 c* v7 nc - pl70a 6 ldq71 t y5 pl65b 6 ldq66 c pl70b 6 ldq71 c gndio gndio6 - gndio6 - ab2 pl66a 6 ldqs66 t (lvds)* pl71a 6 ldqs71 t* aa4 pl66b 6 ldq66 c (lvds)* pl71b 6 ldq71 c* y6 pl67a 6 ldq66 t pl72a 6 ldq71 t vccio vccio6 6 vccio6 6 u9 pl67b 6 ldq66 c pl72b 6 ldq71 c aa5 pl68a 6 ldq66 t (lvds)* pl73a 6 ldq71 t* aa6 pl68b 6 ldq66 c (lvds)* pl73b 6 ldq71 c* lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-170 pinout information lattice semiconductor latticeecp2 /m family data sheet y7 pl69a 6 ldq66 t pl74a 6 ldq71 t gndio gndio6 - gndio6 - v9 pl69b 6 ldq66 c pl74b 6 ldq71 c ac3 tck - tck - w8 tdi - tdi - ac4 tms - tms - v8 tdo - tdo - aa7 vccj - vccj - ab6 pb2a 5 bdq6 t pb2a 5 bdq6 t y8 pb2b 5 bdq6 c pb2b 5 bdq6 c ad1 pb3a 5 bdq6 t pb3a 5 bdq6 t ad2 pb3b 5 bdq6 c pb3b 5 bdq6 c ac5 pb4a 5 bdq6 t pb4a 5 bdq6 t aa8 pb4b 5 bdq6 c pb4b 5 bdq6 c vccio vccio5 5 vccio5 5 ac6 pb5a 5 bdq6 t pb5a 5 bdq6 t w9 pb5b 5 bdq6 c pb5b 5 bdq6 c ab7 pb6a 5 bdqs6 t pb6a 5 bdqs6 t gndio gndio5 - gndio5 - y9 pb6b 5 bdq6 c pb6b 5 bdq6 c ad3 pb7a 5 bdq6 t pb7a 5 bdq6 t ad4 pb7b 5 bdq6 c pb7b 5 bdq6 c aa9 pb8a 5 bdq6 t pb8a 5 bdq6 t w10 pb8b 5 bdq6 c pb8b 5 bdq6 c vccio vccio5 5 vccio5 5 ac7 pb9a 5 bdq6 t pb9a 5 bdq6 t y10 pb9b 5 bdq6 c pb9b 5 bdq6 c ae2 pb10a 5 bdq6 t pb10a 5 bdq6 t ad5 pb10b 5 bdq6 c pb10b 5 bdq6 c gndio gndio5 - gndio5 - ae4 pb11a 5 bdq15 t pb11a 5 bdq15 t ae3 pb11b 5 bdq15 c pb11b 5 bdq15 c w11 pb12a 5 bdq15 t pb12a 5 bdq15 t ab8 pb12b 5 bdq15 c pb12b 5 bdq15 c ae5 pb13a 5 bdq15 t pb13a 5 bdq15 t ad6 pb13b 5 bdq15 c pb13b 5 bdq15 c vccio vccio5 5 vccio5 5 aa10 pb14a 5 bdq15 t pb14a 5 bdq15 t ac8 pb14b 5 bdq15 c pb14b 5 bdq15 c w12 pb15a 5 bdqs15 t pb15a 5 bdqs15 t gndio gndio5 - gndio5 - ac9 pb15b 5 bdq15 c pb15b 5 bdq15 c w13 pb16a 5 bdq15 t pb16a 5 bdq15 t ab10 pb16b 5 bdq15 c pb16b 5 bdq15 c af3 pb17a 5 bdq15 t pb17a 5 bdq15 t af4 pb17b 5 bdq15 c pb17b 5 bdq15 c vccio vccio5 5 vccio5 5 af5 pb18a 5 bdq15 t pb18a 5 bdq15 t af6 pb18b 5 bdq15 c pb18b 5 bdq15 c lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-171 pinout information lattice semiconductor latticeecp2 /m family data sheet y12 pb19a 5 bdq15 t pb19a 5 bdq15 t gndio gndio5 - gndio5 - ab11 pb19b 5 bdq15 c pb19b 5 bdq15 c - - - vccio5 5 - - - gndio5 - ad7 pb20a 5 bdq24 t pb29a 5 bdq33 t af7 pb20b 5 bdq24 c pb29b 5 bdq33 c ad8 pb21a 5 bdq24 t pb30a 5 bdq33 t aa12 pb21b 5 bdq24 c pb30b 5 bdq33 c ae8 pb22a 5 bdq24 t pb31a 5 bdq33 t vccio vccio5 5 vccio5 5 af8 pb22b 5 bdq24 c pb31b 5 bdq33 c ad9 pb23a 5 bdq24 t pb32a 5 bdq33 t ac10 pb23b 5 bdq24 c pb32b 5 bdq33 c ac11 pb24a 5 bdqs24 t pb33a 5 bdqs33 t gndio gndio5 - gndio5 - ab12 pb24b 5 bdq24 c pb33b 5 bdq33 c ad10 pb25a 5 bdq24 t pb34a 5 bdq33 t y13 pb25b 5 bdq24 c pb34b 5 bdq33 c af9 pb26a 5 bdq24 t pb35a 5 bdq33 t vccio vccio5 5 vccio5 5 ae9 pb26b 5 bdq24 c pb35b 5 bdq33 c af10 pb27a 5 bdq24 t pb36a 5 bdq33 t ae10 pb27b 5 bdq24 c pb36b 5 bdq33 c ad11 pb28a 5 bdq24 t pb37a 5 bdq33 t gndio gndio5 - gndio5 - af11 pb28b 5 bdq24 c pb37b 5 bdq33 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - aa13 pb33a 5 bdqs33**** t pb42a 5 bdqs42**** t ab13 pb33b 5 bdq33 c pb42b 5 bdq42 c w14 pb34a 5 vref2_5/bdq33 t pb43a 5 vref2_5/bdq42 t ac12 pb34b 5 vref1_5/bdq33 c pb43b 5 vref1_5/bdq42 c af12 pb35a 5 pclkt5_0/bdq33 t pb44a 5 pclkt5_0/bdq42 t ad12 pb35b 5 pclkc5_0/bdq33 c pb44b 5 pclkc5_0/bdq42 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - ac13 pb40a 4 pclkt4_0/bdq42 t pb49a 4 pclkt4_0/bdq51 t vccio vccio4 4 vccio4 4 y14 pb40b 4 pclkc4_0/bdq42 c pb49b 4 pclkc4_0/bdq51 c ab20 pb57a 4 bdq60 t pb50a 4 vref2_4/bdq51 t ac14 pb41b 4 vref1_4/bdq42 c pb50b 4 vref1_4/bdq51 c ab14 pb42a 4 bdqs42**** t pb51a 4 bdqs51**** t gndio gndio4 - gndio4 - aa14 pb42b 4 bdq42 c pb51b 4 bdq51 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - w17 pb65a 4 bdq69 t pb56a 4 bdq60 t aa19 pb65b 4 bdq69 c pb56b 4 bdq60 c lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-172 pinout information lattice semiconductor latticeecp2 /m family data sheet ac15 pb48a 4 bdq51 t pb57a 4 bdq60 t y18 pb68b 4 bdq69 c pb57b 4 bdq60 c ab15 pb49a 4 bdq51 t pb58a 4 bdq60 t ac16 pb49b 4 bdq51 c pb58b 4 bdq60 c vccio vccio4 4 vccio4 4 aa17 pb60a 4 bdqs60**** t pb59a 4 bdq60 t ab16 pb50b 4 bdq51 c pb59b 4 bdq60 c gndio gndio4 - gndio4 - aa15 pb51a 4 bdqs51**** t pb60a 4 bdqs60 t w16 pb59b 4 bdq60 c pb60b 4 bdq60 c y15 pb52a 4 bdq51 t pb61a 4 bdq60 t ac17 pb52b 4 bdq51 c pb61b 4 bdq60 c aa18 pb61a 4 bdq60 t pb62a 4 bdq60 t y17 pb61b 4 bdq60 c pb62b 4 bdq60 c - - - vccio4 4 gndio gndio4 - - - w15 pb54a 4 bdq51 t pb63a 4 bdq60 t ab17 pb54b 4 bdq51 c pb63b 4 bdq60 c gndio gndio4 - gndio4 - vccio vccio4 4 vccio4 4 v17 pb73a 4 bdq69 t pb72a 4 bdq69 t aa20 pb73b 4 bdq69 c pb72b 4 bdq69 c gndio gndio4 - gndio4 - ad13 vcc - lrc_sq_vccrx3 13 af14 pb47a 4 bdq51 t lrc_sq_hdinp3 13 t ae13 nc - lrc_sq_vccib3 13 ae14 pb41a 4 vref2_4/bdq42 t lrc_sq_hdinn3 13 c ad16 vcc - lrc_sq_vcctx3 13 af17 pb51b 4 bdq51 c lrc_sq_hdoutp3 13 t af16 nc - lrc_sq_vccob3 13 ae17 pb50a 4 bdq51 t lrc_sq_hdoutn3 13 c ad17 vcc - lrc_sq_vcctx2 13 ae18 pb53b 4 bdq51 c lrc_sq_hdoutn2 13 c ad18 nc - lrc_sq_vccob2 13 af18 pb53a 4 bdq51 t lrc_sq_hdoutp2 13 t ad14 vcc - lrc_sq_vccrx2 13 ae15 pb48b 4 bdq51 c lrc_sq_hdinn2 13 c ad15 nc - lrc_sq_vccib2 13 af15 pb47b 4 bdq51 c lrc_sq_hdinp2 13 t ad19 vcc - lrc_sq_vccp 13 ac19 pb57b 4 bdq60 c lrc_sq_refclkp 13 t ab19 pb59a 4 bdq60 t lrc_sq_refclkn 13 c ae19 vccaux - lrc_sq_vccaux33 13 af23 pb64a 4 bdq60 t lrc_sq_hdinp1 13 t ad23 nc - lrc_sq_vccib1 13 ae23 pb66b 4 bdq69 c lrc_sq_hdinn1 13 c ad24 vcc - lrc_sq_vccrx1 13 af20 pb55a 4 bdq51 t lrc_sq_hdoutp1 13 t ad20 nc - lrc_sq_vccob1 13 lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-173 pinout information lattice semiconductor latticeecp2 /m family data sheet ae20 pb55b 4 bdq51 c lrc_sq_hdoutn1 13 c ad21 vcc - lrc_sq_vcctx1 13 ae21 pb63b 4 bdq60 c lrc_sq_hdoutn0 13 c af22 nc - lrc_sq_vccob0 13 af21 pb62a 4 bdq60 t lrc_sq_hdoutp0 13 t ad22 vcc - lrc_sq_vcctx0 13 ae24 pb67b 4 bdq69 c lrc_sq_hdinn0 13 c ae25 nc - lrc_sq_vccib0 13 af24 pb67a 4 bdq69 t lrc_sq_hdinp0 13 t ad25 vcc - lrc_sq_vccrx0 13 aa21 cfg2 8 cfg2 8 aa22 cfg1 8 cfg1 8 ab23 cfg0 8 cfg0 8 ac26 programn 8 programn 8 ab24 cclk 8 cclk 8 aa23 initn 8 initn 8 ab25 done 8 done 8 gndio gndio8 - gndio8 - y19 pr68b 8 writen*** c writen*** 8 y21 pr68a 8 cs1n*** t cs1n*** 8 ab26 pr67b 8 csn*** c csn*** 8 y22 pr67a 8 d0/spifastn*** t d0/spifastn*** 8 vccio vccio8 8 8 w19 pr66b 8 d1*** c d1*** 8 y20 pr66a 8 d2*** t d2*** 8 w22 pr65b 8 d3*** c d3*** 8 gndio gndio8 - - w18 pr65a 8 d4*** t d4*** 8 y23 pr64b 8 d5*** c d5*** 8 aa24 pr64a 8 d6*** t d6*** 8 w21 pr63b 8 d7*** c d7*** 8 vccio vccio8 8 vccio8 8 v20 pr63a 8 di/csspi0n*** t di/csspi0n*** 8 w23 pr62b 8 dout/cson/csspi1n*** c dout/cson/ csspi1n*** 8 y24 pr62a 8 busy/sispi*** t busy/sispi*** 8 v19 rlm0_pllcap 3 rlm0_pllcap 3 v21 pr60b 3 rlm0_gdllc_fb_a c pr65b 3 rlm0_gdllc_fb_a c gndio gndio3 - gndio3 - u19 pr60a 3 rlm0_gdllt_fb_a/rdq57 t pr65a 3 rlm0_gdllt_fb_a t aa26 pr59b 3 rlm0_gdllc_in_a**/rdq57 c (lvds)* pr64b 3 rlm0_gdllc_in_a c* y26 pr59a 3 rlm0_gdllt_in_a**/rdq57 t (lvds)* pr64a 3 rlm0_gdllt_in_a t* v23 pr58b 3 rlm0_gpllc_in_a**/rdq57 c pr63b 3 rlm0_gpllc_in_a c vccio vccio3 3 vccio3 3 u20 pr58a 3 rlm0_gpllt_in_a**/rdq57 t pr63a 3 rlm0_gpllt_in_a t w24 pr57b 3 rlm0_gpllc_fb_a/rdq57 c (lvds)* pr62b 3 rlm0_gpllc_fb_a c* v24 pr57a 3 rlm0_gpllt_fb_a/rdqs57 t (lvds)* pr62a 3 rlm0_gpllt_fb_a t* gndio gndio3 - gndio3 - u21 pr56a 3 rdq57 t pr60a 3 t w25 pr55b 3 rdq57 c (lvds)* pr59b 3 c* lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-174 pinout information lattice semiconductor latticeecp2 /m family data sheet w26 pr55a 3 rdq57 t (lvds)* pr59a 3 t* vccio vccio3 3 vccio3 3 u18 pr54b 3 rdq57 c pr58b 3 c u22 pr54a 3 rdq57 t pr58a 3 t v25 pr53b 3 rdq57 c (lvds)* pr57b 3 c* v26 pr53a 3 rdq57 t (lvds)* pr57a 3 t* u24 pr51b 3 rdq48 c pr55b 3 rdq52 c t24 pr51a 3 rdq48 t pr55a 3 rdq52 t gndio gndio3 - gndio3 - t22 pr50b 3 rdq48 c (lvds)* pr54b 3 rdq52 c* t23 pr50a 3 rdq48 t (lvds)* pr54a 3 rdq52 t* u25 pr49b 3 rdq48 c pr53b 3 rdq52 c u26 pr49a 3 rdq48 t pr53a 3 rdq52 t vccio vccio3 3 vccio3 3 t19 pr48b 3 rdq48 c (lvds)* pr52b 3 rdq52 c* r19 pr48a 3 rdqs48 t (lvds)* pr52a 3 rdqs52 t* r21 pr47b 3 rdq48 c pr51b 3 rdq52 c gndio gndio3 - gndio3 - r20 pr47a 3 rdq48 t pr51a 3 rdq52 t t26 pr46b 3 rdq48 c (lvds)* pr50b 3 rdq52 c* r26 pr46a 3 rdq48 t (lvds)* pr50a 3 rdq52 t* p21 pr45b 3 rdq48 c pr49b 3 rdq52 c vccio vccio3 3 vccio3 3 p19 pr45a 3 rdq48 t pr49a 3 rdq52 t r23 pr44b 3 rdq48 c (lvds)* pr48b 3 rdq52 c* r24 pr44a 3 rdq48 t (lvds)* pr48a 3 rdq52 t* - - - gndio3 - r22 pr42b 3 rlm2_spllc_fb_a c pr46b 3 rlm3_spllc_fb_a c vccio vccio3 3 vccio3 3 n19 pr42a 3 rlm2_spllt_fb_a t pr46a 3 rlm3_spllt_fb_a t p23 pr41b 3 rlm2_spllc_in_a c (lvds)* pr45b 3 rlm3_spllc_in_a c* p24 pr41a 3 rlm2_spllt_in_a t (lvds)* pr45a 3 rlm3_spllt_in_a t* gndio gndio3 - gndio3 - n21 pr40b 3 c pr44b 3 c p22 pr40a 3 t pr44a 3 t n20 pr39b 3 c (lvds)* pr43b 3 c* n22 pr39a 3 t (lvds)* pr43a 3 t* vccio vccio3 3 vccio3 3 p25 pr38b 3 vref2_3 c pr42b 3 vref2_3 c p26 pr38a 3 vref1_3 t pr42a 3 vref1_3 t m21 pr37b 3 pclkc3_0 c (lvds)* pr41b 3 pclkc3_0 c* n23 pr37a 3 pclkt3_0 t (lvds)* pr41a 3 pclkt3_0 t* n24 pr35b 2 pclkc2_0/rdq32 c pr39b 2 pclkc2_0/rdq36 c n25 pr35a 2 pclkt2_0/rdq32 t pr39a 2 pclkt2_0/rdq36 t gndio gndio2 - gndio2 - m22 pr34b 2 rdq32 c (lvds)* pr38b 2 rdq36 c* m24 pr34a 2 rdq32 t (lvds)* pr38a 2 rdq36 t* m23 pr33b 2 rdq32 c pr37b 2 rdq36 c n26 pr33a 2 rdq32 t pr37a 2 rdq36 t lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-175 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio2 2 vccio2 2 l22 pr32b 2 rdq32 c (lvds)* pr36b 2 rdq36 c* l24 pr32a 2 rdqs32 t (lvds)* pr36a 2 rdqs36 t* l23 pr31b 2 rdq32 c pr35b 2 rdq36 c gndio gndio2 - gndio2 - m20 pr31a 2 rdq32 t pr35a 2 rdq36 t m26 pr30b 2 rdq32 c (lvds)* pr34b 2 rdq36 c* l26 pr30a 2 rdq32 t (lvds)* pr34a 2 rdq36 t* k22 pr29b 2 rum1_spllc_fb_a/rdq32 c pr33b 2 rum3_spllc_fb_a/rdq36 c vccio vccio2 2 vccio2 2 m19 pr29a 2 rum1_spllt_fb_a/rdq32 t pr33a 2 rum3_spllt_fb_a/rdq36 t k25 pr28b 2 rum1_spllc_in_a/rdq32 c (l vds)* pr32b 2 rum3_spllc_in_a/rdq36 c* k26 pr28a 2 rum1_spllt_in_a/rdq32 t (lvds)* pr32a 2 rum3_spllt_in_a/rdq36 t* k24 pr26b 2 rdq23 c pr30b 2 rdq27 c k23 pr26a 2 rdq23 t pr30a 2 rdq27 t gndio gndio2 - gndio2 - l19 pr25b 2 rdq23 c (lvds)* pr29b 2 rdq27 c* k21 pr25a 2 rdq23 t (lvds)* pr29a 2 rdq27 t* j23 pr24b 2 rdq23 c pr28b 2 rdq27 c j24 pr24a 2 rdq23 t pr28a 2 rdq27 t vccio vccio2 2 vccio2 2 k20 pr23b 2 rdq23 c (lvds)* pr27b 2 rdq27 c* j21 pr23a 2 rdqs23 t (lvds)* pr27a 2 rdqs27 t* h21 pr22b 2 rdq23 c pr26b 2 rdq27 c gndio gndio2 - gndio2 - k18 pr22a 2 rdq23 t pr26a 2 rdq27 t h22 pr21b 2 rdq23 c (lvds)* pr25b 2 rdq27 c* j20 pr21a 2 rdq23 t (lvds)* pr25a 2 rdq27 t* j25 pr20b 2 rdq23 c pr24b 2 rdq27 c vccio vccio2 2 vccio2 2 j26 pr20a 2 rdq23 t pr24a 2 rdq27 t g21 pr19b 2 rdq23 c (lvds)* pr23b 2 rdq27 c* j19 pr19a 2 rdq23 t (lvds)* pr23a 2 rdq27 t* gndio gndio2 - gndio2 - h23 pr18b 2 rdq15 c pr21b 2 c h24 pr18a 2 rdq15 t pr21a 2 t h25 pr17b 2 rdq15 c (lvds)* pr20b 2 c* h26 pr17a 2 rdq15 t (lvds)* pr20a 2 t* vccio vccio2 2 vccio2 2 g22 pr16b 2 rdq15 c pr19b 2 c k19 pr16a 2 rdq15 t pr19a 2 t g24 pr15b 2 rdq15 c (lvds)* pr18b 2 c* g23 pr15a 2 rdqs15 t (lvds)* pr18a 2 t* gndio gndio2 - gndio2 - j18 pr14b 2 rdq15 c pr14b 2 c f22 pr14a 2 rdq15 t pr14a 2 t - - - vccio2 2 f23 pr13b 2 rdq15 c (lvds)* pr13b 2 c* f24 pr13a 2 rdq15 t (lvds)* pr13a 2 t* lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-176 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio2 2 - - h20 pr12b 2 rum0_spllc_fb_a/rdq15 c pr12b 2 rum0_spllc_fb_a c - - - gndio2 - f21 pr12a 2 rum0_spllt_fb_a/rdq15 t pr12a 2 rum0_spllt_fb_a t g26 pr11b 2 rum0_spllc_in_a/rdq15 c (lvds)* pr11b 2 rum0_spllc_in_a c* f26 pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* pr11a 2 rum0_spllt_in_a t* - - - vccio2 2 e24 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 - gndio2 - e23 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio4 4 vccio2 2 h19 xres - xres - c25 urc_sq_vccrx 0 12 urc_sq_vccrx0 12 a24 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b25 urc_sq_vccib0 12 urc_sq_vccib0 12 b24 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c22 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a21 urc_sq_hdout p0 12 t urc_sq_hdoutp0 12 t a22 urc_sq_vccob 0 12 urc_sq_vccob0 12 b21 urc_sq_hdout n0 12 c urc_sq_hdoutn0 12 c c21 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b20 urc_sq_hdout n1 12 c urc_sq_hdoutn1 12 c c20 urc_sq_vccob 1 12 urc_sq_vccob1 12 a20 urc_sq_hdout p1 12 t urc_sq_hdoutp1 12 t c24 urc_sq_vccrx 1 12 urc_sq_vccrx1 12 b23 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c23 urc_sq_vccib1 12 urc_sq_vccib1 12 a23 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b19 urc_sq_vccau x33 12 urc_sq_vccaux33 12 e19 urc_sq_refclk n 12 c urc_sq_refclkn 12 c d19 urc_sq_refclk p 12 t urc_sq_refclkp 12 t c19 urc_sq_vccp 12 urc_sq_vccp 12 a15 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c15 urc_sq_vccib2 12 urc_sq_vccib2 12 b15 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c14 urc_sq_vccrx 2 12 urc_sq_vccrx2 12 a18 urc_sq_hdout p2 12 t urc_sq_hdoutp2 12 t c18 urc_sq_vccob 2 12 urc_sq_vccob2 12 b18 urc_sq_hdout n2 12 c urc_sq_hdoutn2 12 c c17 urc_sq_vcctx2 12 urc_sq_vcctx2 12 lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-177 pinout information lattice semiconductor latticeecp2 /m family data sheet b17 urc_sq_hdout n3 12 c urc_sq_hdoutn3 12 c a16 urc_sq_vccob 3 12 urc_sq_vccob3 12 a17 urc_sq_hdout p3 12 t urc_sq_hdoutp3 12 t c16 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b14 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b13 urc_sq_vccib3 12 urc_sq_vccib3 12 a14 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c13 urc_sq_vccrx 3 12 urc_sq_vccrx3 12 - - - gndio1 - - - - vccio1 1 e17 pt46b 1 c pt55b 1 c d17 pt46a 1 t pt55a 1 t gndio gndio1 - gndio1 - f17 pt45b 1 c pt54b 1 c d16 pt45a 1 t pt54a 1 t f19 pt44b 1 c pt53b 1 c f18 pt44a 1 t pt53a 1 t vccio vccio1 1 vccio1 1 e16 pt43b 1 c pt52b 1 c d15 pt43a 1 t pt52a 1 t g18 pt42b 1 c pt51b 1 c e15 pt42a 1 t pt51a 1 t gndio gndio1 - gndio1 - g17 pt41b 1 c pt50b 1 c e14 pt41a 1 t pt50a 1 t d14 pt40b 1 c pt49b 1 c d13 pt40a 1 t pt49a 1 t vccio vccio1 1 vccio1 1 f15 pt39b 1 vref2_1 c pt48b 1 vref2_1 c e12 pt39a 1 vref1_1 t pt48a 1 vref1_1 t h17 pt38b 1 pclkc1_0 c pt47b 1 pclkc1_0 c e13 pt38a 1 pclkt1_0 t pt47a 1 pclkt1_0 t c12 pt37b 0 pclkc0_0 c pt46b 0 pclkc0_0 c gndio gndio0 - gndio0 - g15 pt37a 0 pclkt0_0 t pt46a 0 pclkt0_0 t c11 pt36b 0 vref2_0 c pt45b 0 vref2_0 c f14 pt36a 0 vref1_0 t pt45a 0 vref1_0 t a12 pt35b 0 c pt44b 0 c vccio vccio0 0 vccio0 0 a11 pt35a 0 t pt44a 0 t d12 pt34b 0 c pt43b 0 c h16 pt34a 0 t pt43a 0 t h18 pt33b 0 c pt42b 0 c h15 pt33a 0 t pt42a 0 t a10 pt32b 0 c pt41b 0 c gndio gndio0 - gndio0 - b10 pt32a 0 t pt41a 0 t lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-178 pinout information lattice semiconductor latticeecp2 /m family data sheet d11 pt31b 0 c pt40b 0 c vccio vccio0 0 vccio0 0 g14 pt31a 0 t pt40a 0 t e11 pt30b 0 c pt39b 0 c f13 pt30a 0 t pt39a 0 t d10 pt29b 0 c pt38b 0 c h14 pt29a 0 t pt38a 0 t gndio gndio0 - gndio0 - vccio vccio0 0 vccio0 0 a9 pt24b 0 c pt24b 0 c c10 pt23b 0 c pt23b 0 c gndio gndio0 - gndio0 - e8 pt23a 0 t pt23a 0 t b9 pt22b 0 c pt22b 0 c a8 pt22a 0 t pt22a 0 t vccio vccio0 0 vccio0 0 f12 pt21b 0 c pt21b 0 c e10 pt21a 0 t pt21a 0 t g13 pt20b 0 c pt20b 0 c c9 pt20a 0 t pt20a 0 t b8 pt19b 0 c pt19b 0 c gndio gndio0 - gndio0 - a7 pt19a 0 t pt19a 0 t d9 pt18b 0 c pt18b 0 c h13 pt18a 0 t pt18a 0 t d6 pt17b 0 c pt17b 0 c c7 pt17a 0 t pt17a 0 t vccio vccio0 0 vccio0 0 c8 pt16b 0 c pt16b 0 c g12 pt16a 0 t pt16a 0 t d8 pt15b 0 c pt15b 0 c h12 pt15a 0 t pt15a 0 t gndio gndio0 - gndio0 - a6 pt14b 0 c pt14b 0 c a5 pt14a 0 t pt14a 0 t a4 pt13b 0 c pt13b 0 c a3 pt13a 0 t pt13a 0 t vccio vccio0 0 vccio0 0 c6 pt12b 0 c pt12b 0 c f10 pt12a 0 t pt12a 0 t d7 pt11b 0 c pt11b 0 c h11 pt11a 0 t pt11a 0 t d5 pt10b 0 c pt10b 0 c gndio gndio0 - gndio0 - e6 pt10a 0 t pt10a 0 t g10 pt9b 0 c pt9b 0 c f9 pt9a 0 t pt9a 0 t h10 pt8b 0 c pt8b 0 c vccio vccio0 0 vccio0 0 lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-179 pinout information lattice semiconductor latticeecp2 /m family data sheet e7 pt8a 0 t pt8a 0 t b3 pt7b 0 c pt7b 0 c c5 pt7a 0 t pt7a 0 t b2 pt6b 0 c pt6b 0 c c4 pt6a 0 t pt6a 0 t g9 pt5b 0 c pt5b 0 c gndio gndio0 - gndio0 - f7 pt5a 0 t pt5a 0 t c3 pt4b 0 c pt4b 0 c vccio vccio0 0 vccio0 0 d4 pt4a 0 t pt4a 0 t j10 pt3b 0 c pt3b 0 c f8 pt3a 0 t pt3a 0 t g8 pt2b 0 c pt2b 0 c g7 pt2a 0 t pt2a 0 t l12 vcc - vcc - l13 vcc - vcc - l14 vcc - vcc - l15 vcc - vcc - m11 vcc - vcc - m12 vcc - vcc - m15 vcc - vcc - m16 vcc - vcc - n11 vcc - vcc - n16 vcc - vcc - p11 vcc - vcc - p16 vcc - vcc - r11 vcc - vcc - r12 vcc - vcc - r15 vcc - vcc - r16 vcc - vcc - t12 vcc - vcc - t13 vcc - vcc - t14 vcc - vcc - t15 vcc - vcc - b12 vccio0 0 vccio0 0 b7 vccio0 0 vccio0 0 f11 vccio0 0 vccio0 0 j13 vccio0 0 vccio0 0 k12 vccio0 0 vccio0 1 d18 vccio1 1 vccio1 1 f16 vccio1 1 vccio1 1 j14 vccio1 1 vccio1 1 k15 vccio1 1 vccio1 1 g25 vccio2 2 vccio2 2 l21 vccio2 2 vccio2 2 m17 vccio2 2 vccio2 2 m25 vccio2 2 vccio2 2 n18 vccio2 2 vccio2 2 lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-180 pinout information lattice semiconductor latticeecp2 /m family data sheet p18 vccio3 3 vccio3 3 r17 vccio3 3 vccio3 3 r25 vccio3 3 vccio3 3 t21 vccio3 3 vccio3 3 y25 vccio3 3 vccio3 3 aa16 vccio4 4 vccio4 4 ac18 vccio4 4 vccio4 4 u15 vccio4 4 vccio4 4 v14 vccio4 4 vccio4 4 aa11 vccio5 5 vccio5 5 v13 vccio5 5 vccio5 5 ae12 vccio5 5 vccio5 5 ae7 vccio5 5 vccio5 5 u12 vccio5 5 vccio5 5 p9 vccio6 6 vccio6 6 r10 vccio6 6 vccio6 6 r2 vccio6 6 vccio6 6 t6 vccio6 6 vccio6 6 y2 vccio6 6 vccio6 6 g2 vccio7 7 vccio7 7 l6 vccio7 7 vccio7 7 m10 vccio7 7 vccio7 7 m2 vccio7 7 vccio7 7 n9 vccio7 7 vccio7 7 ac24 vccio8 8 vccio8 8 u17 vccio8 8 vccio8 8 j11 vccaux - vccaux - j12 vccaux - vccaux - j15 vccaux - vccaux - j16 vccaux - vccaux - l18 vccaux - vccaux - l9 vccaux - vccaux - m18 vccaux - vccaux - m9 vccaux - vccaux - r18 vccaux - vccaux - r9 vccaux - vccaux - t18 vccaux - vccaux - t9 vccaux - vccaux - v11 vccaux - vccaux - v12 vccaux - vccaux - v15 vccaux - vccaux - v16 vccaux - vccaux - a13 gnd - gnd - a19 gnd - gnd - a2 gnd - gnd - a25 gnd - gnd - aa2 gnd - gnd - aa25 gnd - gnd - ab18 gnd - gnd - lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-181 pinout information lattice semiconductor latticeecp2 /m family data sheet ab22 gnd - gnd - ab5 gnd - gnd - ab9 gnd - gnd - ae1 gnd - gnd - ae11 gnd - gnd - ae16 gnd - gnd - ae22 gnd - gnd - ae26 gnd - gnd - ae6 gnd - gnd - af13 gnd - gnd - af19 gnd - gnd - af2 gnd - gnd - af25 gnd - gnd - b1 gnd - gnd - b11 gnd - gnd - b16 gnd - gnd - b22 gnd - gnd - b26 gnd - gnd - b6 gnd - gnd - e18 gnd - gnd - e22 gnd - gnd - e5 gnd - gnd - e9 gnd - gnd - f2 gnd - gnd - f25 gnd - gnd - g11 gnd - gnd - g16 gnd - gnd - j22 gnd - gnd - j5 gnd - gnd - k11 gnd - gnd - k13 gnd - gnd - k14 gnd - gnd - k16 gnd - gnd - l10 gnd - gnd - l11 gnd - gnd - l16 gnd - gnd - l17 gnd - gnd - l2 gnd - gnd - l20 gnd - gnd - l25 gnd - gnd - l7 gnd - gnd - m13 gnd - gnd - m14 gnd - gnd - n10 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n14 gnd - gnd - n15 gnd - gnd - n17 gnd - gnd - lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-182 pinout information lattice semiconductor latticeecp2 /m family data sheet p10 gnd - gnd - p12 gnd - gnd - p13 gnd - gnd - p14 gnd - gnd - p15 gnd - gnd - p17 gnd - gnd - r13 gnd - gnd - r14 gnd - gnd - t10 gnd - gnd - t11 gnd - gnd - t16 gnd - gnd - t17 gnd - gnd - t2 gnd - gnd - t20 gnd - gnd - t25 gnd - gnd - t7 gnd - gnd - u11 gnd - gnd - u13 gnd - gnd - u14 gnd - gnd - u16 gnd - gnd - v22 gnd - gnd - v5 gnd - gnd - y11 gnd - gnd - y16 gnd - gnd - ab3 nc - nc - ab4 nc - nc - ac1 nc - nc - ac2 nc - nc - b4 nc - nc - b5 nc - nc - c26 nc - nc - d20 nc - nc - d21 nc - nc - d22 nc - nc - d23 nc - nc - d24 nc - nc - d25 nc - nc - d26 nc - nc - e20 nc - nc - e21 nc - nc - e25 nc - nc - e26 nc - nc - f20 nc - nc - g20 nc - nc - k10 nc - nc - k17 nc - nc - r4 nc - nc - u10 nc - nc - u23 nc - nc - lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-183 pinout information lattice semiconductor latticeecp2 /m family data sheet v10 nc - nc - w7 nc - nc - ab21 pb69b 4 bdq69 c nc - ac20 pb58a 4 bdq60 t nc - ac21 pb63a 4 bdq60 t nc - ac22 pb69a 4 bdqs69**** t nc - ac23 pb71a 4 bdq69 t nc - ac25 pb71b 4 bdq69 c nc - ad26 pb70b 4 bdq69 c nc - w20 pb72b 4 bdq69 c nc - h7 l_vccpll - l_vccpll - k6 l_vccpll - l_vccpll - p7 l_vccpll - l_vccpll - r8 l_vccpll - l_vccpll - v18 r_vccpll - r_vccpll - p20 r_vccpll - r_vccpll - j17 r_vccpll - r_vccpll - g19 r_vccpll - r_vccpll - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. *** for density migration, board design must take into account t hat these sysconfig pins are du al function for the lower densit y devices (ecp2m20 and ecp2m35) and are dedicated pins for th e higher density devices (ecp2m50, ecp2m70 and ecp2m100). ****due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2m35e/se and lfe2m 50e/se logic signal co nnections: 672 fpbga lfe2m35e/se lfe2m50e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-184 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential d2 pl9a 7 vref2_7/ldq6 t pl9a 7 vref2_7 t d3 pl9b 7 vref1_7/ldq6 c pl9b 7 vref1_7 c gndio gndio7 - gndio7 - j8 pl11a 7 lum0_spllt_in_a t (lvds)* pl11a 7 lum0_spllt_in_a/ldq15 t (lvds)* h7 pl11b 7 lum0_spllc_in_a c (lvds)* pl11b 7 lum0_spllc_in_a/ldq15 c (lvds)* e3 pl12a 7 lum0_spllt_fb_a t pl12a 7 lum0_spllt_fb_a/ldq15 t e4 pl12b 7 lum0_spllc_fb_a c pl12b 7 lum0_spllc_fb_a/ldq15 c gndio gndio7 - - - g6 pl13a 7 t (lvds)* pl13a 7 ldq15 t (lvds)* f5 pl13b 7 c (lvds)* pl13b 7 ldq15 c (lvds)* e2 pl14a 7 t pl14a 7 ldq15 t d1 pl14b 7 c pl14b 7 ldq15 c - - - gndio7 - g5 nc - pl15a 7 ldqs15 t (lvds)* g4 nc - pl15b 7 ldq15 c (lvds)* k7 nc - pl16a 7 ldq15 t k8 nc - pl16b 7 ldq15 c e1 nc - pl17a 7 ldq15 t (lvds)* f2 nc - pl17b 7 ldq15 c (lvds)* f1 nc - pl18a 7 ldq15 t - - - gndio7 - g3 nc - pl18b 7 ldq15 c h5 pl15a 7 t (lvds)* pl21a 7 t (lvds)* h4 pl15b 7 c (lvds)* pl21b 7 c (lvds)* j5 pl16a 7 t pl22a 7 t j4 pl16b 7 c pl22b 7 c gndio gndio7 - gndio7 - g2 nc - pl24a 7 ldq28 t (lvds)* g1 nc - pl24b 7 ldq28 c (lvds)* l9 nc - pl25a 7 ldq28 t l7 nc - pl25b 7 ldq28 c k6 nc - pl26a 7 ldq28 t (lvds)* k5 nc - pl26b 7 ldq28 c (lvds)* l8 nc - pl27a 7 ldq28 t l6 nc - pl27b 7 ldq28 c - - - gndio7 - h3 pl18a 7 t (lvds)* pl28a 7 ldqs28 t (lvds)* h2 pl18b 7 c (lvds)* pl28b 7 ldq28 c (lvds)* n8 pl19a 7 t pl29a 7 ldq28 t m9 pl19b 7 c pl29b 7 ldq28 c j3 pl20a 7 t (lvds)* pl30a 7 ldq28 t (lvds)* vccio vccio7 7 - - j2 pl20b 7 c (lvds)* pl30b 7 ldq28 c (lvds)* h1 pl21a 7 t pl31a 7 ldq28 t gndio gndio7 - gndio7 - j1 pl21b 7 c pl31b 7 ldq28 c --- -- --- -- l5 pl23a 7 ldq27 t (lvds)* pl33a 7 ldq37 t (lvds)* 4-185 pinout information lattice semiconductor latticeecp2 /m family data sheet l4 pl23b 7 ldq27 c (lvds)* pl33b 7 ldq37 c (lvds)* n9 pl24a 7 ldq27 t pl34a 7 ldq37 t n7 pl24b 7 ldq27 c pl34b 7 ldq37 c k2 pl25a 7 ldq27 t (lvds)* pl35a 7 ldq37 t (lvds)* k1 pl25b 7 ldq27 c (lvds)* pl35b 7 ldq37 c (lvds)* p9 pl26a 7 ldq27 t pl36a 7 ldq37 t p7 pl26b 7 ldq27 c pl36b 7 ldq37 c gndio gndio7 - gndio7 - m6 pl27a 7 ldqs27 t (lvds)* pl37a 7 ldqs37 t (lvds)* m5 pl27b 7 ldq27 c (lvds)* pl37b 7 ldq37 c (lvds)* n5 pl28a 7 ldq27 t pl38a 7 ldq37 t n6 pl28b 7 ldq27 c pl38b 7 ldq37 c m4 pl29a 7 ldq27 t (lvds)* pl39a 7 ldq37 t (lvds)* m3 pl29b 7 ldq27 c (lvds)* pl39b 7 ldq37 c (lvds)* p6 pl30a 7 ldq27 t pl40a 7 ldq37 t gndio gndio7 - gndio7 - p8 pl30b 7 ldq27 c pl40b 7 ldq37 c l3 pl32a 7 lum3_spllt_in_a/ldq36 t (lvds)* pl42a 7 lum3_spllt_in_a/ldq46 t (lvds)* l2 pl32b 7 lum3_spllc_in_a/ldq36 c (lvds)* pl42b 7 lum3_spllc_in_a/ldq46 c (lvds)* p5 pl33a 7 lum3_spllt_fb_a/ldq36 t pl43a 7 lum3_spllt_fb_a/ldq46 t p4 pl33b 7 lum3_spllc_fb_a/ldq36 c pl43b 7 lum3_spllc_fb_a/ldq46 c l1 pl34a 7 ldq36 t (lvds)* pl44a 7 ldq46 t (lvds)* m2 pl34b 7 ldq36 c (lvds)* pl44b 7 ldq46 c (lvds)* r5 pl35a 7 ldq36 t pl45a 7 ldq46 t r4 pl35b 7 ldq36 c pl45b 7 ldq46 c gndio gndio7 - gndio7 - m1 pl36a 7 ldqs36 t (lvds)* pl46a 7 ldqs46 t (lvds)* n2 pl36b 7 ldq36 c (lvds)* pl46b 7 ldq46 c (lvds)* r8 pl37a 7 ldq36 t pl47a 7 ldq46 t t9 pl37b 7 ldq36 c pl47b 7 ldq46 c p3 pl38a 7 ldq36 t (lvds)* pl48a 7 ldq46 t (lvds)* p2 pl38b 7 ldq36 c (lvds)* pl48b 7 ldq46 c (lvds)* n1 pl39a 7 pclkt7_0/ldq36 t pl49a 7 pclkt7_0/ldq46 t gndio gndio7 - gndio7 - p1 pl39b 7 pclkc7_0/ldq36 c pl49b 7 pclkc7_0/ldq46 c t5 pl41a 6 pclkt6_0 t (lvds)* pl51a 6 pclkt6_0/ldq55 t (lvds)* t4 pl41b 6 pclkc6_0 c (lvds)* pl51b 6 pclkc6_0/ldq55 c (lvds)* u7 pl42a 6 vref2_6 t pl52a 6 vref2_6/ldq55 t t8 pl42b 6 vref1_6 c pl52b 6 vref1_6/ldq55 c r3 pl43a 6 t (lvds)* pl53a 6 ldq55 t (lvds)* vccio vccio6 6 vccio6 6 r2 pl43b 6 c (lvds)* pl53b 6 ldq55 c (lvds)* r1 pl44a 6 t pl54a 6 ldq55 t t1 pl44b 6 c pl54b 6 ldq55 c gndio gndio6 - gndio6 - - - - vccio6 6 t3 pl45a 6 llm3_spllt_in_a t (lvds)* pl57a 6 llm3_spllt_in_a/ldq55 t (lvds)* t2 pl45b 6 llm3_spllc_in_a c (lvds)* pl57b 6 llm3_spllc_in_a/ldq55 c (lvds)* u9 pl46a 6 llm3_spllt_fb_a t pl58a 6 llm3_spllt_fb_a/ldq55 t lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-186 pinout information lattice semiconductor latticeecp2 /m family data sheet u8 pl46b 6 llm3_spllc_fb_a c pl58b 6 llm3_spllc_fb_a/ldq55 c vccio vccio6 6 gndio6 - u5 pl48a 6 ldq52 t (lvds)* pl60a 6 ldq64 t (lvds)* u4 pl48b 6 ldq52 c (lvds)* pl60b 6 ldq64 c (lvds)* v9 pl49a 6 ldq52 t pl61a 6 ldq64 t v7 pl49b 6 ldq52 c pl61b 6 ldq64 c vccio vccio6 6 vccio6 6 u3 pl50a 6 ldq52 t (lvds)* pl62a 6 ldq64 t (lvds)* u2 pl50b 6 ldq52 c (lvds)* pl62b 6 ldq64 c (lvds)* v8 pl51a 6 ldq52 t pl63a 6 ldq64 t u6 pl51b 6 ldq52 c pl63b 6 ldq64 c gndio gndio6 - gndio6 - u1 pl52a 6 ldqs52 t (lvds)* pl64a 6 ldqs64 t (lvds)* v2 pl52b 6 ldq52 c (lvds)* pl64b 6 ldq64 c (lvds)* v5 pl53a 6 ldq52 t pl65a 6 ldq64 t vccio vccio6 6 vccio6 6 v6 pl53b 6 ldq52 c pl65b 6 ldq64 c v1 pl54a 6 ldq52 t (lvds)* pl66a 6 ldq64 t (lvds)* w1 pl54b 6 ldq52 c (lvds)* pl66b 6 ldq64 c (lvds)* w5 pl55a 6 ldq52 t pl67a 6 ldq64 t gndio gndio6 - gndio6 - w6 pl55b 6 ldq52 c pl67b 6 ldq64 c w3 pl57a 6 t (lvds)* pl69a 6 ldq73 t (lvds)* w4 pl57b 6 c (lvds)* pl69b 6 ldq73 c (lvds)* w2 pl58a 6 t pl70a 6 ldq73 t y4 pl58b 6 c pl70b 6 ldq73 c y1 pl59a 6 t (lvds)* pl71a 6 ldq73 t (lvds)* vccio vccio6 6 vccio6 6 y2 pl59b 6 c (lvds)* pl71b 6 ldq73 c (lvds)* y5 pl60a 6 t pl72a 6 ldq73 t y6 pl60b 6 c pl72b 6 ldq73 c aa1 nc - pl73a 6 ldqs73 t (lvds)* gndio gndio6 - gndio6 - aa2 nc - pl73b 6 ldq73 c (lvds)* y3 nc - pl74a 6 ldq73 t ab1 nc - pl74b 6 ldq73 c - - - vccio6 6 y9 nc - pl75a 6 ldq73 t (lvds)* y8 nc - pl75b 6 ldq73 c (lvds)* y7 nc - pl76a 6 ldq73 t aa7 nc - pl76b 6 ldq73 c - - - gndio6 - --- -- ab2 nc - pl78a 6 ldq82 t (lvds)* ab3 nc - pl78b 6 ldq82 c (lvds)* aa5 nc - pl79a 6 ldq82 t aa6 nc - pl79b 6 ldq82 c ab4 nc - pl80a 6 ldq82 t (lvds)* - - - vccio6 6 lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-187 pinout information lattice semiconductor latticeecp2 /m family data sheet ab5 nc - pl80b 6 ldq82 c (lvds)* aa8 nc - pl81a 6 ldq82 t aa9 nc - pl81b 6 ldq82 c ac1 pl62a 6 llm0_gpllt_in_a** t (lvds)* pl82a 6 llm0_gpllt_in_a**/ldqs82 t (lvds)* gndio gndio6 - gndio6 - ac2 pl62b 6 llm0_gpllc_in_a** c (lvds)* pl82b 6 llm0_gpllc_in_a**/ldq82 c (lvds)* ac4 pl63a 6 llm0_gpllt_fb_a t pl83a 6 llm0_gpllt_fb_a/ldq82 t ac3 pl63b 6 llm0_gpllc_fb_a c pl83b 6 llm0_gpllc_fb_a/ldq82 c vccio vccio6 6 vccio6 6 ac7 pl64a 6 llm0_gdllt_in_a** t (lvds)* pl84a 6 llm0_gdllt_in_a**/ldq82 t (lvds)* ac6 pl64b 6 llm0_gdllc_in_a** c (lvds)* pl84b 6 llm0_gdllc_in_a**/ldq82 c (lvds)* ac5 pl65a 6 llm0_gdllt_fb_a t pl85a 6 llm0_gdllt_fb_a/ldq82 t ad3 pl65b 6 llm0_gdllc_fb_a c pl85b 6 llm0_gdllc_fb_a/ldq82 c gndio gndio6 - gndio6 - ab8 llm0_pllcap 6 llm0_pllcap 6 ad2 pl67a 6 ldq71 t (lvds)* pl87a 6 t ad1 pl67b 6 ldq71 c (lvds)* pl87b 6 c ae2 tck - tck - ae1 tdi - tdi - af2 tms - tms - af1 tdo - tdo - ag1 vccj - vccj - ah1 vcc - llc_sq_vccrx3 14 ak2 pb11a 5 bdq15 t llc_sq_hdinp3 14 t aj1 nc - llc_sq_vccib3 14 aj2 pb11b 5 bdq15 c llc_sq_hdinn3 14 c ah4 vcc - llc_sq_vcctx3 14 ak5 pb13a 5 bdq15 t llc_sq_hdoutp3 14 t ak4 nc - llc_sq_vccob3 14 aj5 pb13b 5 bdq15 c llc_sq_hdoutn3 14 c ah5 vcc - llc_sq_vcctx2 14 aj6 pb14b 5 bdq15 c llc_sq_hdoutn2 14 c ah6 nc - llc_sq_vccob2 14 ak6 pb14a 5 bdq15 t llc_sq_hdoutp2 14 t ah2 vcc - llc_sq_vccrx2 14 aj3 pb12b 5 bdq15 c llc_sq_hdinn2 14 c ah3 nc - llc_sq_vccib2 14 ak3 pb12a 5 bdq15 t llc_sq_hdinp2 14 t ah7 vcc - llc_sq_vccp 14 ag7 pb15a 5 bdqs15 t llc_sq_refclkp 14 t af7 pb15b 5 bdq15 c llc_sq_refclkn 14 c aj7 vccaux - llc_sq_vccaux33 14 ak11 pb18a 5 bdq15 t llc_sq_hdinp1 14 t ah11 nc - llc_sq_vccib1 14 aj11 pb18b 5 bdq15 c llc_sq_hdinn1 14 c ah12 vcc - llc_sq_vccrx1 14 ak8 pb16a 5 bdq15 t llc_sq_hdoutp1 14 t ah8 nc - llc_sq_vccob1 14 aj8 pb16b 5 bdq15 c llc_sq_hdoutn1 14 c lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-188 pinout information lattice semiconductor latticeecp2 /m family data sheet ah9 vcc - llc_sq_vcctx1 14 aj9 pb17b 5 bdq15 c llc_sq_hdoutn0 14 c ak10 nc - llc_sq_vccob0 14 ak9 pb17a 5 bdq15 t llc_sq_hdoutp0 14 t ah10 vcc - llc_sq_vcctx0 14 aj12 pb19b 5 bdq15 c llc_sq_hdinn0 14 c aj13 nc - llc_sq_vccib0 14 ak12 pb19a 5 bdq15 t llc_sq_hdinp0 14 t ah13 vcc - llc_sq_vccrx0 14 af10 pb3a 5 bdq6 t pb30a 5 bdq33 t ae8 pb3b 5 bdq6 c pb30b 5 bdq33 c ae11 pb4a 5 bdq6 t pb31a 5 bdq33 t vccio vccio5 5 vccio5 5 ad9 pb4b 5 bdq6 c pb31b 5 bdq33 c ae10 pb5a 5 bdq6 t pb32a 5 bdq33 t ad10 pb5b 5 bdq6 c pb32b 5 bdq33 c ae13 pb6a 5 bdqs6 t pb33a 5 bdqs33 t gndio gndio5 - gndio5 - ac12 pb6b 5 bdq6 c pb33b 5 bdq33 c ag2 pb7a 5 bdq6 t pb34a 5 bdq33 t ag3 pb7b 5 bdq6 c pb34b 5 bdq33 c ad13 pb8a 5 bdq6 t pb35a 5 bdq33 t vccio vccio5 5 vccio5 5 ac13 pb8b 5 bdq6 c pb35b 5 bdq33 c ae14 pb9a 5 bdq6 t pb36a 5 bdq33 t ac14 pb9b 5 bdq6 c pb36b 5 bdq33 c af3 pb10a 5 bdq6 t pb37a 5 bdq33 t gndio gndio5 - gndio5 - af4 pb10b 5 bdq6 c pb37b 5 bdq33 c vccio vccio5 5 - - ag4 pb20a 5 bdq24 t pb38a 5 bdq42 t ag5 pb20b 5 bdq24 c pb38b 5 bdq42 c gndio gndio5 - - - vccio vccio5 5 - - ad11 pb24a 5 bdqs24**** t pb39a 5 bdq42 t af13 pb24b 5 bdq24 c pb39b 5 bdq42 c af12 pb25a 5 bdq24 t pb40a 5 bdq42 t - - - vccio5 5 ad14 pb25b 5 bdq24 c pb40b 5 bdq42 c ag8 pb26a 5 bdq24 t pb41a 5 bdq42 t af8 pb26b 5 bdq24 c pb41b 5 bdq42 c ae15 pb27a 5 bdq24 t pb42a 5 bdqs42**** t - - - gndio5 - vccio vccio5 5 - - ac15 pb27b 5 bdq24 c pb42b 5 bdq42 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - ad15 pb38a 5 bdq42 t pb47a 5 bdq51 t af15 pb38b 5 bdq42 c pb47b 5 bdq51 c lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-189 pinout information lattice semiconductor latticeecp2 /m family data sheet ag10 pb39a 5 bdq42 t pb48a 5 bdq51 t ag9 pb39b 5 bdq42 c pb48b 5 bdq51 c ah14 pb40a 5 bdq42 t pb49a 5 bdq51 t ag12 pb40b 5 bdq42 c pb49b 5 bdq51 c vccio vccio5 5 vccio5 5 ag15 pb41a 5 bdq42 t pb50a 5 bdq51 t ag13 pb41b 5 bdq42 c pb50b 5 bdq51 c gndio gndio5 - gndio5 - af16 pb42a 5 bdqs42 t pb51a 5 bdqs51 t ah15 pb42b 5 bdq42 c pb51b 5 bdq51 c ac16 pb43a 5 vref2_5/bdq42 t pb52a 5 vref2_5/bdq51 t ae16 pb43b 5 vref1_5/bdq42 c pb52b 5 vref1_5/bdq51 c ag11 pb44a 5 pclkt5_0/bdq42 t pb53a 5 pclkt5_0/bdq51 t af11 pb44b 5 pclkc5_0/bdq42 c pb53b 5 pclkc5_0/bdq51 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - aj14 pb49a 4 pclkt4_0/bdq51 t pb58a 4 pclkt4_0/bdq60 t vccio vccio4 4 vccio4 4 ak14 pb49b 4 pclkc4_0/bdq51 c pb58b 4 pclkc4_0/bdq60 c ak15 pb50a 4 vref2_4/bdq51 t pb59a 4 vref2_4/bdq60 t ak16 pb50b 4 vref1_4/bdq51 c pb59b 4 vref1_4/bdq60 c af18 pb51a 4 bdqs51 t pb60a 4 bdqs60 t gndio gndio4 - gndio4 - ad16 pb51b 4 bdq51 c pb60b 4 bdq60 c aj15 pb52a 4 bdq51 t pb61a 4 bdq60 t ag16 pb52b 4 bdq51 c pb61b 4 bdq60 c ae17 pb53a 4 bdq51 t pb62a 4 bdq60 t vccio vccio4 4 vccio4 4 ac17 pb53b 4 bdq51 c pb62b 4 bdq60 c ah16 pb54a 4 bdq51 t pb63a 4 bdq60 t ak17 pb54b 4 bdq51 c pb63b 4 bdq60 c ag20 pb55a 4 bdq51 t pb64a 4 bdq60 t gndio gndio4 - gndio4 - ag21 pb55b 4 bdq51 c pb64b 4 bdq60 c ag18 pb56a 4 bdq60 t pb65a 4 bdq69 t aj16 pb56b 4 bdq60 c pb65b 4 bdq69 c af21 pb57a 4 bdq60 t pb66a 4 bdq69 t ag22 pb57b 4 bdq60 c pb66b 4 bdq69 c ad17 pb58a 4 bdq60 t pb67a 4 bdq69 t af19 pb58b 4 bdq60 c pb67b 4 bdq69 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - ah17 pb62a 4 bdq60 t pb71a 4 bdq69 t aj17 pb62b 4 bdq60 c pb71b 4 bdq69 c vccio vccio4 4 vccio4 4 af26 pb64a 4 bdq60 t pb73a 4 bdq69 t ae25 pb64b 4 bdq60 c pb73b 4 bdq69 c gndio gndio4 - gndio4 - ad24 pb65a 4 bdq69 t pb74a 4 bdq78 t lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-190 pinout information lattice semiconductor latticeecp2 /m family data sheet ae24 pb65b 4 bdq69 c pb74b 4 bdq78 c ad18 pb66a 4 bdq69 t pb75a 4 bdq78 t ac18 pb66b 4 bdq69 c pb75b 4 bdq78 c ae18 pb67a 4 bdq69 t pb76a 4 bdq78 t ag19 pb67b 4 bdq69 c pb76b 4 bdq78 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - ac19 pb69a 4 bdqs69 t pb78a 4 bdqs78 t ad20 pb69b 4 bdq69 c pb78b 4 bdq78 c ab18 pb70a 4 bdq69 t pb79a 4 bdq78 t ac20 pb70b 4 bdq69 c pb79b 4 bdq78 c ae20 pb71a 4 bdq69 t pb80a 4 bdq78 t ae21 pb71b 4 bdq69 c pb80b 4 bdq78 c vccio vccio4 4 vccio4 4 ac23 pb72a 4 bdq69 t pb81a 4 bdq78 t ad23 pb72b 4 bdq69 c pb81b 4 bdq78 c gndio gndio4 - gndio4 - ah18 lrc_sq_vccrx3 13 lrc_sq_vccrx3 13 ak19 lrc_sq_hdinp3 13 t lrc_sq_hdinp3 13 t aj18 lrc_sq_vccib3 13 lrc_sq_vccib3 13 aj19 lrc_sq_hdinn3 13 c lrc_sq_hdinn3 13 c ah21 lrc_sq_vcctx3 13 lrc_sq_vcctx3 13 ak22 lrc_sq_hdoutp3 13 t lrc_sq_hdoutp3 13 t ak21 lrc_sq_vccob3 13 lrc_sq_vccob3 13 aj22 lrc_sq_hdoutn3 13 c lrc_sq_hdoutn3 13 c ah22 lrc_sq_vcctx2 13 lrc_sq_vcctx2 13 aj23 lrc_sq_hdoutn2 13 c lrc_sq_hdoutn2 13 c ah23 lrc_sq_vccob2 13 lrc_sq_vccob2 13 ak23 lrc_sq_hdoutp2 13 t lrc_sq_hdoutp2 13 t ah19 lrc_sq_vccrx2 13 lrc_sq_vccrx2 13 aj20 lrc_sq_hdinn2 13 c lrc_sq_hdinn2 13 c ah20 lrc_sq_vccib2 13 lrc_sq_vccib2 13 ak20 lrc_sq_hdinp2 13 t lrc_sq_hdinp2 13 t ah24 lrc_sq_vccp 13 lrc_sq_vccp 13 ag24 lrc_sq_refclkp 13 t lrc_sq_refclkp 13 t af24 lrc_sq_refclkn 13 c lrc_sq_refclkn 13 c aj24 lrc_sq_vccaux33 13 lrc_sq_vccaux33 13 ak28 lrc_sq_hdinp1 13 t lrc_sq_hdinp1 13 t ah28 lrc_sq_vccib1 13 lrc_sq_vccib1 13 aj28 lrc_sq_hdinn1 13 c lrc_sq_hdinn1 13 c ah29 lrc_sq_vccrx1 13 lrc_sq_vccrx1 13 ak25 lrc_sq_hdoutp1 13 t lrc_sq_hdoutp1 13 t ah25 lrc_sq_vccob1 13 lrc_sq_vccob1 13 aj25 lrc_sq_hdoutn1 13 c lrc_sq_hdoutn1 13 c ah26 lrc_sq_vcctx1 13 lrc_sq_vcctx1 13 aj26 lrc_sq_hdoutn0 13 c lrc_sq_hdoutn0 13 c ak27 lrc_sq_vccob0 13 lrc_sq_vccob0 13 ak26 lrc_sq_hdoutp0 13 t lrc_sq_hdoutp0 13 t ah27 lrc_sq_vcctx0 13 lrc_sq_vcctx0 13 lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-191 pinout information lattice semiconductor latticeecp2 /m family data sheet aj29 lrc_sq_hdinn0 13 c lrc_sq_hdinn0 13 c aj30 lrc_sq_vccib0 13 lrc_sq_vccib0 13 ak29 lrc_sq_hdinp0 13 t lrc_sq_hdinp0 13 t ah30 lrc_sq_vccrx0 13 lrc_sq_vccrx0 13 ag27 cfg2 8 cfg2 8 ad25 cfg1 8 cfg1 8 ag28 cfg0 8 cfg0 8 ag30 programn 8 programn 8 ag29 cclk 8 cclk 8 ac24 initn 8 initn 8 af27 done 8 done 8 gndio gndio8 - gndio8 - af28 writen*** 8 writen*** 8 ae26 cs1n*** 8 cs1n*** 8 ab23 csn*** 8 csn*** 8 af29 d0/spifastn*** 8 d0/spifastn*** 8 vccio vccio8 8 vccio8 8 af30 d1*** 8 d1*** 8 ad26 d2*** 8 d2*** 8 ae29 d3*** 8 d3*** 8 gndio gndio8 - gndio8 - ae30 d4*** 8 d4*** 8 ad29 d5*** 8 d5*** 8 ac25 d6*** 8 d6*** 8 ad30 d7*** 8 d7*** 8 vccio vccio8 8 vccio8 8 aa22 di/csspi0n*** 8 di/csspi0n*** 8 ac26 dout/cson/ csspi1n*** 8 dout/cson/ csspi1n*** 8 aa23 busy/sispi*** 8 busy/sispi*** 8 ab22 rlm0_pllcap 3 rlm0_pllcap 3 ac27 pr65b 3 rlm0_gdllc_fb_a c pr85b 3 rlm0_gdllc_fb_a/rdq82 c gndio gndio3 - gndio3 - ac28 pr65a 3 rlm0_gdllt_fb_a t pr85a 3 rlm0_gdllt_fb_a/rdq82 t ac29 pr64b 3 rlm0_gdllc_in_a** c (lvds)* pr84b 3 rlm0_gdllc_in_a**/rdq82 c (lvds)* ac30 pr64a 3 rlm0_gdllt_in_a** t (lvds)* pr84a 3 rlm0_gdllt_in_a**/rdq82 t (lvds)* ab30 pr63b 3 rlm0_gpllc_in_a** c pr83b 3 rlm0_gpllc_in_a**/rdq82 c vccio vccio3 3 vccio3 3 aa30 pr63a 3 rlm0_gpllt_in_a** t pr83a 3 rlm0_gpllt_in_a**/rdq82 t ab29 pr62b 3 rlm0_gpllc_fb_a c (lvds)* pr82b 3 rlm0_gpllc_fb_a/rdq82 c (lvds)* ab28 pr62a 3 rlm0_gpllt_fb_a t (lvds)* pr82a 3 rlm0_gpllt_fb_a/rdqs82 t (lvds)* gndio gndio3 - gndio3 - y22 pr60b 3 c pr81b 3 rdq82 c y23 pr60a 3 t pr81a 3 rdq82 t ab26 nc - pr80b 3 rdq82 c (lvds)* ab27 nc - pr80a 3 rdq82 t (lvds)* - - - vccio3 3 y24 nc - pr79b 3 rdq82 c y25 nc - pr79a 3 rdq82 t aa29 nc - pr78b 3 rdq82 c (lvds)* lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-192 pinout information lattice semiconductor latticeecp2 /m family data sheet y28 nc - pr78a 3 rdq82 t (lvds)* y30 nc - pr76b 3 rdq73 c y29 nc - pr76a 3 rdq73 t - - - gndio3 - --- -- w22 nc - pr75b 3 rdq73 c (lvds)* v22 nc - pr75a 3 rdq73 t (lvds)* y27 nc - pr74b 3 rdq73 c - - - vccio3 3 y26 nc - pr74a 3 rdq73 t w30 nc - pr73b 3 rdq73 c (lvds)* w29 nc - pr73a 3 rdqs73 t (lvds)* - - - gndio3 - w25 nc - pr72b 3 rdq73 c w26 nc - pr72a 3 rdq73 t u29 pr59b 3 c (lvds)* pr71b 3 rdq73 c (lvds)* v29 pr59a 3 t (lvds)* pr71a 3 rdq73 t (lvds)* vccio vccio3 3 vccio3 3 v30 pr58b 3 c pr70b 3 rdq73 c u30 pr58a 3 t pr70a 3 rdq73 t w27 pr57b 3 c (lvds)* pr69b 3 rdq73 c (lvds)* w28 pr57a 3 t (lvds)* pr69a 3 rdq73 t (lvds)* v24 pr55b 3 rdq52 c pr67b 3 rdq64 c v25 pr55a 3 rdq52 t pr67a 3 rdq64 t gndio gndio3 - gndio3 - u28 pr54b 3 rdq52 c (lvds)* pr66b 3 rdq64 c (lvds)* u27 pr54a 3 rdq52 t (lvds)* pr66a 3 rdq64 t (lvds)* u23 pr53b 3 rdq52 c pr65b 3 rdq64 c v23 pr53a 3 rdq52 t pr65a 3 rdq64 t vccio vccio3 3 vccio3 3 v26 pr52b 3 rdq52 c (lvds)* pr64b 3 rdq64 c (lvds)* u26 pr52a 3 rdqs52 t (lvds)* pr64a 3 rdqs64 t (lvds)* u25 pr51b 3 rdq52 c pr63b 3 rdq64 c gndio gndio3 - gndio3 - u24 pr51a 3 rdq52 t pr63a 3 rdq64 t t30 pr50b 3 rdq52 c (lvds)* pr62b 3 rdq64 c (lvds)* r30 pr50a 3 rdq52 t (lvds)* pr62a 3 rdq64 t (lvds)* t23 pr49b 3 rdq52 c pr61b 3 rdq64 c vccio vccio3 3 vccio3 3 t22 pr49a 3 rdq52 t pr61a 3 rdq64 t t29 pr48b 3 rdq52 c (lvds)* pr60b 3 rdq64 c (lvds)* t28 pr48a 3 rdq52 t (lvds)* pr60a 3 rdq64 t (lvds)* r23 pr46b 3 rlm3_spllc_fb_a c pr58b 3 rlm3_spllc_fb_a/rdq55 c gndio gndio3 - gndio3 - vccio vccio3 3 - - r22 pr46a 3 rlm3_spllt_fb_a t pr58a 3 rlm3_spllt_fb_a/rdq55 t p30 pr45b 3 rlm3_spllc_in_a c (lvds)* pr57b 3 rlm3_spllc_in_a/rdq55 c (lvds)* r29 pr45a 3 rlm3_spllt_in_a t (lvds)* pr57a 3 rlm3_spllt_in_a/rdq55 t (lvds)* t27 pr44b 3 c pr56b 3 rdq55 c lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-193 pinout information lattice semiconductor latticeecp2 /m family data sheet - - - vccio3 3 t26 pr44a 3 t pr56a 3 rdq55 t gndio gndio3 - gndio3 - n30 pr43b 3 c (lvds)* pr53b 3 rdq55 c (lvds)* n29 pr43a 3 t (lvds)* pr53a 3 rdq55 t (lvds)* vccio vccio3 3 vccio3 3 r27 pr42b 3 vref2_3 c pr52b 3 vref2_3/rdq55 c r28 pr42a 3 vref1_3 t pr52a 3 vref1_3/rdq55 t p29 pr41b 3 pclkc3_0 c (lvds)* pr51b 3 pclkc3_0/rdq55 c (lvds)* p28 pr41a 3 pclkt3_0 t (lvds)* pr51a 3 pclkt3_0/rdq55 t (lvds)* m30 pr39b 2 pclkc2_0/rdq36 c pr49b 2 pclkc2_0/rdq46 c m29 pr39a 2 pclkt2_0/rdq36 t pr49a 2 pclkt2_0/rdq46 t gndio gndio2 - gndio2 - p23 pr38b 2 rdq36 c (lvds)* pr48b 2 rdq46 c (lvds)* p24 pr38a 2 rdq36 t (lvds)* pr48a 2 rdq46 t (lvds)* r26 pr37b 2 rdq36 c pr47b 2 rdq46 c p27 pr37a 2 rdq36 t pr47a 2 rdq46 t vccio vccio2 2 vccio2 2 p25 pr36b 2 rdq36 c (lvds)* pr46b 2 rdq46 c (lvds)* p26 pr36a 2 rdqs36 t (lvds)* pr46a 2 rdqs46 t (lvds)* k30 pr35b 2 rdq36 c pr45b 2 rdq46 c gndio gndio2 - gndio2 - k29 pr35a 2 rdq36 t pr45a 2 rdq46 t n22 pr34b 2 rdq36 c (lvds)* pr44b 2 rdq46 c (lvds)* p22 pr34a 2 rdq36 t (lvds)* pr44a 2 rdq46 t (lvds)* j30 pr33b 2 rum3_spllc_fb_a/rdq36 c pr43b 2 rum3_spllc_fb_a/rdq46 c vccio vccio2 2 vccio2 2 j29 pr33a 2 rum3_spllt_fb_a/rdq36 t pr43a 2 rum3_spllt_fb_a/rdq46 t n24 pr32b 2 rum3_spllc_in_a/rdq36 c (lvds)* pr42b 2 rum3_spllc_in_a/rdq46 c (lvds)* n23 pr32a 2 rum3_spllt_in_a/rdq36 t (lvds) * pr42a 2 rum3_spllt_in_a/rdq46 t (lvds)* n25 pr30b 2 rdq27 c pr40b 2 rdq37 c n26 pr30a 2 rdq27 t pr40a 2 rdq37 t gndio gndio2 - gndio2 - m27 pr29b 2 rdq27 c (lvds)* pr39b 2 rdq37 c (lvds)* m28 pr29a 2 rdq27 t (lvds)* pr39a 2 rdq37 t (lvds)* h30 pr28b 2 rdq27 c pr38b 2 rdq37 c g30 pr28a 2 rdq27 t pr38a 2 rdq37 t vccio vccio2 2 vccio2 2 m25 pr27b 2 rdq27 c (lvds)* pr37b 2 rdq37 c (lvds)* m26 pr27a 2 rdqs27 t (lvds)* pr37a 2 rdqs37 t (lvds)* l30 pr26b 2 rdq27 c pr36b 2 rdq37 c gndio gndio2 - gndio2 - l29 pr26a 2 rdq27 t pr36a 2 rdq37 t l28 pr25b 2 rdq27 c (lvds)* pr35b 2 rdq37 c (lvds)* l27 pr25a 2 rdq27 t (lvds)* pr35a 2 rdq37 t (lvds)* h29 pr24b 2 rdq27 c pr34b 2 rdq37 c vccio vccio2 2 vccio2 2 g29 pr24a 2 rdq27 t pr34a 2 rdq37 t l22 pr23b 2 rdq27 c (lvds)* pr33b 2 rdq37 c (lvds)* lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-194 pinout information lattice semiconductor latticeecp2 /m family data sheet m22 pr23a 2 rdq27 t (lvds)* pr33a 2 rdq37 t (lvds)* f30 pr21b 2 c pr31b 2 rdq28 c gndio gndio2 - gndio2 - f29 pr21a 2 t pr31a 2 rdq28 t --- -- --- -- e30 pr20b 2 c (lvds)* pr30b 2 rdq28 c (lvds)* e29 pr20a 2 t (lvds)* pr30a 2 rdq28 t (lvds)* vccio vccio2 2 - - l25 pr19b 2 c pr29b 2 rdq28 c l26 pr19a 2 t pr29a 2 rdq28 t - - - vccio2 2 h28 pr18b 2 c (lvds)* pr28b 2 rdq28 c (lvds)* j28 pr18a 2 t (lvds)* pr28a 2 rdqs28 t (lvds)* g28 pr16b 2 c pr27b 2 rdq28 c gndio gndio2 - gndio2 - g27 pr16a 2 t pr27a 2 rdq28 t l24 nc - pr26b 2 rdq28 c (lvds)* l23 nc - pr26a 2 rdq28 t (lvds)* d30 nc - pr25b 2 rdq28 c - - - vccio2 2 d29 nc - pr25a 2 rdq28 t k24 nc - pr24b 2 rdq28 c (lvds)* k25 nc - pr24a 2 rdq28 t (lvds)* j27 nc - pr22b 2 c - - - gndio2 - k26 nc - pr22a 2 t k23 pr15b 2 c (lvds)* pr21b 2 c (lvds)* k22 pr15a 2 t (lvds)* pr21a 2 t (lvds)* j22 pr14b 2 c pr20b 2 c vccio vccio2 - vccio2 2 j23 pr14a 2 t pr20a 2 t - - - gndio2 - --- -- j26 nc - pr17b 2 rdq15 c (lvds)* h26 nc - pr17a 2 rdq15 t (lvds)* h27 nc - pr16b 2 rdq15 c g26 nc - pr16a 2 rdq15 t - - - vccio2 2 h23 nc - pr15b 2 rdq15 c (lvds)* h24 nc - pr15a 2 rdqs15 t (lvds)* d28 nc - pr14b 2 rdq15 c - - - gndio2 - e28 nc - pr14a 2 rdq15 t g24 pr13b 2 c (lvds)* pr13b 2 rdq15 c (lvds)* h25 pr13a 2 t (lvds)* pr13a 2 rdq15 t (lvds)* d27 pr12b 2 rum0_spllc_fb_a c pr12b 2 rum0_spllc_fb_a/rdq15 c gndio gndio2 - vccio2 2 e27 pr12a 2 rum0_spllt_fb_a t pr12a 2 rum0_spllt_fb_a/rdq15 t lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-195 pinout information lattice semiconductor latticeecp2 /m family data sheet f26 pr11b 2 rum0_spllc_in_a c (lvds)* pr11b 2 rum0_spllc_in_a/rdq15 c (lvds)* g25 pr11a 2 rum0_spllt_in_a t (lvds)* pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* f24 pr9b 2 vref2_2 c pr9b 2 vref2_2 c vccio vccio2 - - - gndio gndio2 - gndio2 - f25 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 vccio2 2 g23 xres - xres 1 c30 urc_sq_vccrx0 12 urc_sq_vccrx0 12 a29 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b30 urc_sq_vccib0 12 urc_sq_vccib0 12 b29 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c27 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a26 urc_sq_hdoutp0 12 t urc_sq_hdoutp0 12 t a27 urc_sq_vccob0 12 urc_sq_vccob0 12 b26 urc_sq_hdoutn0 12 c urc_sq_hdoutn0 12 c c26 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b25 urc_sq_hdoutn1 12 c urc_sq_hdoutn1 12 c c25 urc_sq_vccob1 12 urc_sq_vccob1 12 a25 urc_sq_hdoutp1 12 t urc_sq_hdoutp1 12 t c29 urc_sq_vccrx1 12 urc_sq_vccrx1 12 b28 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c28 urc_sq_vccib1 12 urc_sq_vccib1 12 a28 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b24 urc_sq_vccaux33 12 urc_sq_vccaux33 12 e24 urc_sq_refclkn 12 c urc_sq_refclkn 12 c d24 urc_sq_refclkp 12 t urc_sq_refclkp 12 t c24 urc_sq_vccp 12 urc_sq_vccp 12 a20 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c20 urc_sq_vccib2 12 urc_sq_vccib2 12 b20 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c19 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a23 urc_sq_hdoutp2 12 t urc_sq_hdoutp2 12 t c23 urc_sq_vccob2 12 urc_sq_vccob2 12 b23 urc_sq_hdoutn2 12 c urc_sq_hdoutn2 12 c c22 urc_sq_vcctx2 12 urc_sq_vcctx2 12 b22 urc_sq_hdoutn3 12 c urc_sq_hdoutn3 12 c a21 urc_sq_vccob3 12 urc_sq_vccob3 12 a22 urc_sq_hdoutp3 12 t urc_sq_hdoutp3 12 t c21 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b19 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b18 urc_sq_vccib3 12 urc_sq_vccib3 12 a19 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c18 urc_sq_vccrx3 12 urc_sq_vccrx3 12 d23 pt73b 1 c pt82b 1 c gndio gndio1 - gndio1 - e21 pt73a 1 t pt82a 1 t d26 pt72b 1 c pt81b 1 c e26 pt72a 1 t pt81a 1 t lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-196 pinout information lattice semiconductor latticeecp2 /m family data sheet e23 pt71b 1 c pt80b 1 c - - - vccio1 1 g22 pt71a 1 t pt80a 1 t vccio vccio1 1 - - d22 pt70b 1 c pt79b 1 c f21 pt70a 1 t pt79a 1 t g18 pt69b 1 c pt78b 1 c h18 pt69a 1 t pt78a 1 t d20 pt68b 1 c pt77b 1 c gndio gndio1 - gndio1 - d21 pt68a 1 t pt77a 1 t e20 pt67b 1 c pt76b 1 c e19 pt67a 1 t pt76a 1 t d19 pt66b 1 c pt75b 1 c vccio vccio1 1 vccio1 1 e18 pt66a 1 t pt75a 1 t d18 pt65b 1 c pt74b 1 c c17 pt65a 1 t pt74a 1 t a17 pt64b 1 c pt73b 1 c b17 pt64a 1 t pt73a 1 t gndio gndio1 - gndio1 - vccio vccio1 1 vccio1 1 j18 nc - pt66b 1 c j19 nc - pt66a 1 t h17 nc - pt65b 1 c j17 nc - pt65a 1 t f18 nc - pt64b 1 c f17 nc - pt64a 1 t - - - gndio1 - a16 pt54b 1 c pt63b 1 c b16 pt54a 1 t pt63a 1 t g17 pt53b 1 c pt62b 1 c g16 pt53a 1 t pt62a 1 t vccio vccio1 1 vccio1 1 h16 pt52b 1 c pt61b 1 c f16 pt52a 1 t pt61a 1 t j16 pt51b 1 c pt60b 1 c g15 pt51a 1 t pt60a 1 t gndio gndio1 - gndio1 - c16 pt50b 1 c pt59b 1 c d16 pt50a 1 t pt59a 1 t j15 pt49b 1 c pt58b 1 c h15 pt49a 1 t pt58a 1 t vccio vccio1 1 vccio1 1 a15 pt48b 1 vref2_1 c pt57b 1 vref2_1 c b15 pt48a 1 vref1_1 t pt57a 1 vref1_1 t f15 pt47b 1 pclkc1_0 c pt56b 1 pclkc1_0 c e16 pt47a 1 pclkt1_0 t pt56a 1 pclkt1_0 t c15 pt46b 0 pclkc0_0 c pt55b 0 pclkc0_0 c lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-197 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio0 - gndio0 - d15 pt46a 0 pclkt0_0 t pt55a 0 pclkt0_0 t c14 pt45b 0 vref2_0 c pt54b 0 vref2_0 c e15 pt45a 0 vref1_0 t pt54a 0 vref1_0 t g14 pt44b 0 c pt53b 0 c vccio vccio0 0 vccio0 0 j14 pt44a 0 t pt53a 0 t f14 pt43b 0 c pt52b 0 c h14 pt43a 0 t pt52a 0 t a14 pt42b 0 c pt51b 0 c b14 pt42a 0 t pt51a 0 t d13 pt41b 0 c pt50b 0 c gndio gndio0 - gndio0 - f13 pt41a 0 t pt50a 0 t g13 pt40b 0 c pt49b 0 c vccio vccio0 0 vccio0 0 j11 pt40a 0 t pt49a 0 t d4 pt38b 0 c pt47b 0 c d5 pt38a 0 t pt47a 0 t e5 pt37b 0 c pt46b 0 c f6 pt37a 0 t pt46a 0 t gndio gndio0 - gndio0 - vccio vccio0 0 vccio0 0 f7 pt34b 0 c pt43b 0 c d8 pt34a 0 t pt43a 0 t gndio gndio0 - gndio0 - j13 pt32b 0 c pt41b 0 c g11 pt32a 0 t pt41a 0 t h13 pt31b 0 c pt40b 0 c h12 pt31a 0 t pt40a 0 t vccio vccio0 0 vccio0 0 e8 pt30b 0 c pt39b 0 c d9 pt30a 0 t pt39a 0 t d12 pt28b 0 c pt37b 0 c gndio gndio0 - gndio0 - e13 pt28a 0 t pt37a 0 t vccio vccio0 0 vccio0 0 gndio gndio0 - gndio0 - j12 pt5b 0 c pt31b 0 c gndio gndio0 - - - vccio vccio0 0 vccio0 0 h10 pt5a 0 t pt31a 0 t e12 pt4b 0 c pt30b 0 c d11 pt4a 0 t pt30a 0 t h11 pt3b 0 c pt29b 0 c f11 pt3a 0 t pt29a 0 t c13 vcc - ulc_sq_vccrx0 11 a12 pt19a 0 t ulc_sq_hdinp0 11 t b13 nc - ulc_sq_vccib0 11 lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-198 pinout information lattice semiconductor latticeecp2 /m family data sheet b12 pt19b 0 c ulc_sq_hdinn0 11 c c10 vcc - ulc_sq_vcctx0 11 a9 pt17a 0 t ulc_sq_hdoutp0 11 t a10 nc - ulc_sq_vccob0 11 b9 pt17b 0 c ulc_sq_hdoutn0 11 c c9 vcc - ulc_sq_vcctx1 11 b8 pt18b 0 c ulc_sq_hdoutn1 11 c c8 nc - ulc_sq_vccob1 11 a8 pt18a 0 t ulc_sq_hdoutp1 11 t c12 vcc - ulc_sq_vccrx1 11 b11 pt16b 0 c ulc_sq_hdinn1 11 c c11 nc - ulc_sq_vccib1 11 a11 pt16a 0 t ulc_sq_hdinp1 11 t b7 vccaux - ulc_sq_vccaux33 11 e7 pt15b 0 c ulc_sq_refclkn 11 c d7 pt15a 0 t ulc_sq_refclkp 11 t c7 vcc - ulc_sq_vccp 11 a3 pt12a 0 t ulc_sq_hdinp2 11 t c3 nc - ulc_sq_vccib2 11 b3 pt12b 0 c ulc_sq_hdinn2 11 c c2 vcc - ulc_sq_vccrx2 11 a6 pt14a 0 t ulc_sq_hdoutp2 11 t c6 nc - ulc_sq_vccob2 11 b6 pt14b 0 c ulc_sq_hdoutn2 11 c c5 vcc - ulc_sq_vcctx2 11 b5 pt13b 0 c ulc_sq_hdoutn3 11 c a4 nc - ulc_sq_vccob3 11 a5 pt13a 0 t ulc_sq_hdoutp3 11 t c4 vcc - ulc_sq_vcctx3 11 b2 pt11b 0 c ulc_sq_hdinn3 11 c b1 nc - ulc_sq_vccib3 11 a2 pt11a 0 t ulc_sq_hdinp3 11 t c1 vcc - ulc_sq_vccrx3 11 l12 vcc - vcc - l13 vcc - vcc - l18 vcc - vcc - l19 vcc - vcc - m11 vcc - vcc - m12 vcc - vcc - m13 vcc - vcc - m14 vcc - vcc - m15 vcc - vcc - m16 vcc - vcc - m17 vcc - vcc - m18 vcc - vcc - m19 vcc - vcc - m20 vcc - vcc - n11 vcc - vcc - n12 vcc - vcc - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-199 pinout information lattice semiconductor latticeecp2 /m family data sheet n19 vcc - vcc - n20 vcc - vcc - p12 vcc - vcc - p19 vcc - vcc - r12 vcc - vcc - r19 vcc - vcc - t12 vcc - vcc - t19 vcc - vcc - u12 vcc - vcc - u19 vcc - vcc - v11 vcc - vcc - v12 vcc - vcc - v19 vcc - vcc - v20 vcc - vcc - w11 vcc - vcc - w12 vcc - vcc - w13 vcc - vcc - w14 vcc - vcc - w15 vcc - vcc - w16 vcc - vcc - w17 vcc - vcc - w18 vcc - vcc - w19 vcc - vcc - w20 vcc - vcc - y12 vcc - vcc - y13 vcc - vcc - y18 vcc - vcc - y19 vcc - vcc - d14 vccio0 0 vccio0 0 e6 vccio0 0 vccio0 0 e9 vccio0 0 vccio0 0 f12 vccio0 0 vccio0 0 k12 vccio0 0 vccio0 0 k13 vccio0 0 vccio0 0 d17 vccio1 1 vccio1 1 e22 vccio1 1 vccio1 1 e25 vccio1 1 vccio1 1 f19 vccio1 1 vccio1 1 k18 vccio1 1 vccio1 1 k19 vccio1 1 vccio1 1 f28 vccio2 2 vccio2 2 j25 vccio2 2 vccio2 2 k28 vccio2 2 vccio2 2 m21 vccio2 2 vccio2 2 m24 vccio2 2 vccio2 2 n21 vccio2 2 vccio2 2 n28 vccio2 2 vccio2 2 p21 vccio2 2 vccio2 2 r25 vccio2 2 vccio2 2 lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-200 pinout information lattice semiconductor latticeecp2 /m family data sheet aa28 vccio3 3 vccio3 3 ab25 vccio3 3 vccio3 3 ae28 vccio3 3 vccio3 3 t25 vccio3 3 vccio3 3 u21 vccio3 3 vccio3 3 v21 vccio3 3 vccio3 3 v28 vccio3 3 vccio3 3 w21 vccio3 3 vccio3 3 w24 vccio3 3 vccio3 3 aa18 vccio4 4 vccio4 4 aa19 vccio4 4 vccio4 4 ae19 vccio4 4 vccio4 4 af22 vccio4 4 vccio4 4 ag17 vccio4 4 vccio4 4 ag25 vccio4 4 vccio4 4 aa12 vccio5 5 vccio5 5 aa13 vccio5 5 vccio5 5 ae12 vccio5 5 vccio5 5 af9 vccio5 5 vccio5 5 ag14 vccio5 5 vccio5 5 ag6 vccio5 5 vccio5 5 aa3 vccio6 6 vccio6 6 ab6 vccio6 6 vccio6 6 ae3 vccio6 6 vccio6 6 t6 vccio6 6 vccio6 6 u10 vccio6 6 vccio6 6 v10 vccio6 6 vccio6 6 v3 vccio6 6 vccio6 6 w10 vccio6 6 vccio6 6 w7 vccio6 6 vccio6 6 f3 vccio7 7 vccio7 7 j6 vccio7 7 vccio7 7 k3 vccio7 7 vccio7 7 m10 vccio7 7 vccio7 7 m7 vccio7 7 vccio7 7 n10 vccio7 7 vccio7 7 n3 vccio7 7 vccio7 7 p10 vccio7 7 vccio7 7 r6 vccio7 7 vccio7 7 aa25 vccio8 8 vccio8 8 ad28 vccio8 8 vccio8 8 aa10 vccaux - vccaux - aa11 vccaux - vccaux - aa20 vccaux - vccaux - aa21 vccaux - vccaux - k10 vccaux - vccaux - k11 vccaux - vccaux - k20 vccaux - vccaux - k21 vccaux - vccaux - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-201 pinout information lattice semiconductor latticeecp2 /m family data sheet l10 vccaux - vccaux - l11 vccaux - vccaux - l20 vccaux - vccaux - l21 vccaux - vccaux - y10 vccaux - vccaux - y11 vccaux - vccaux - y20 vccaux - vccaux - y21 vccaux - vccaux - a1 gnd - gnd - a13 gnd - gnd - a18 gnd - gnd - a24 gnd - gnd - a30 gnd - gnd - a7 gnd - gnd - aa14 gnd - gnd - aa15 gnd - gnd - aa16 gnd - gnd - aa17 gnd - gnd - aa24 gnd - gnd - aa27 gnd - gnd - aa4 gnd - gnd - ab24 gnd - gnd - ab7 gnd - gnd - ad12 gnd - gnd - ad19 gnd - gnd - ad27 gnd - gnd - ae22 gnd - gnd - ae27 gnd - gnd - ae4 gnd - gnd - ae9 gnd - gnd - af14 gnd - gnd - af17 gnd - gnd - af25 gnd - gnd - af6 gnd - gnd - aj10 gnd - gnd - aj21 gnd - gnd - aj27 gnd - gnd - aj4 gnd - gnd - ak1 gnd - gnd - ak13 gnd - gnd - ak18 gnd - gnd - ak24 gnd - gnd - ak30 gnd - gnd - ak7 gnd - gnd - b10 gnd - gnd - b21 gnd - gnd - b27 gnd - gnd - b4 gnd - gnd - d25 gnd - gnd - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-202 pinout information lattice semiconductor latticeecp2 /m family data sheet d6 gnd - gnd - e14 gnd - gnd - e17 gnd - gnd - f22 gnd - gnd - f27 gnd - gnd - f4 gnd - gnd - f9 gnd - gnd - g12 gnd - gnd - g19 gnd - gnd - j24 gnd - gnd - j7 gnd - gnd - k14 gnd - gnd - k15 gnd - gnd - k16 gnd - gnd - k17 gnd - gnd - k27 gnd - gnd - k4 gnd - gnd - l14 gnd - gnd - l15 gnd - gnd - l16 gnd - gnd - l17 gnd - gnd - m23 gnd - gnd - m8 gnd - gnd - n14 gnd - gnd - n15 gnd - gnd - n16 gnd - gnd - n17 gnd - gnd - n27 gnd - gnd - n4 gnd - gnd - p11 gnd - gnd - p13 gnd - gnd - p14 gnd - gnd - p15 gnd - gnd - p16 gnd - gnd - p17 gnd - gnd - p18 gnd - gnd - p20 gnd - gnd - r10 gnd - gnd - r11 gnd - gnd - r13 gnd - gnd - r14 gnd - gnd - r15 gnd - gnd - r16 gnd - gnd - r17 gnd - gnd - r18 gnd - gnd - r20 gnd - gnd - r21 gnd - gnd - r24 gnd - gnd - r7 gnd - gnd - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-203 pinout information lattice semiconductor latticeecp2 /m family data sheet t10 gnd - gnd - t11 gnd - gnd - t13 gnd - gnd - t14 gnd - gnd - t15 gnd - gnd - t16 gnd - gnd - t17 gnd - gnd - t18 gnd - gnd - t20 gnd - gnd - t21 gnd - gnd - t24 gnd - gnd - t7 gnd - gnd - u11 gnd - gnd - u13 gnd - gnd - u14 gnd - gnd - u15 gnd - gnd - u16 gnd - gnd - u17 gnd - gnd - u18 gnd - gnd - u20 gnd - gnd - v14 gnd - gnd - v15 gnd - gnd - v16 gnd - gnd - v17 gnd - gnd - v27 gnd - gnd - v4 gnd - gnd - w23 gnd - gnd - w8 gnd - gnd - y14 gnd - gnd - y15 gnd - gnd - y16 gnd - gnd - y17 gnd - gnd - aa26 nc - nc - ab10 pl73b 6 ldq71 c (lvds)* nc - ab11 nc - nc - ab12 nc - nc - ab13 nc - nc - ab14 nc - nc - ab15 nc - nc - ab16 nc - nc - ab17 nc - nc - ab19 nc - nc - ab20 nc - nc - ab21 nc - nc - ab9 pl73a 6 ldq71 t (lvds)* nc - ac10 pl74b 6 ldq71 c nc - ac11 nc - nc - ac21 nc - nc - ac22 nc - nc - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-204 pinout information lattice semiconductor latticeecp2 /m family data sheet ac8 pl70b 6 ldq71 c nc - ac9 pl74a 6 ldq71 t nc - ad21 nc - nc - ad22 nc - nc - ad4 pl68a 6 ldq71 t nc - ad5 pl68b 6 ldq71 c nc - ad6 pl71a 6 ldqs71 t (lvds)* nc - ad7 pl72a 6 ldq71 t nc - ad8 pl72b 6 ldq71 c nc - ae23 nc - nc - ae5 pl69a 6 ldq71 t (lvds)* nc - ae6 pl70a 6 ldq71 t nc - ae7 pl71b 6 ldq71 c (lvds)* nc - af20 nc - nc - af23 nc - nc - af5 pl69b 6 ldq71 c (lvds)* nc - ag23 nc - nc - ag26 nc - nc - d10 pt10a 0 t nc - e10 pt9b 0 c nc - e11 pt10b 0 c nc - f10 pt9a 0 t nc - f20 nc - nc - f23 nc - nc - f8 pl6b 7 ldq6 c (lvds)* nc - g10 nc - nc - g20 nc - nc - g21 nc - nc - g7 pl8a 7 ldq6 t (lvds)* nc - g8 pl6a 7 ldqs6**** t (lvds)* nc - g9 pl5a 7 ldq6 t nc - h19 nc - nc - h20 nc - nc - h21 nc - nc - h22 nc - nc - h6 pl8b 7 ldq6 c (lvds)* nc - h8 pl5b 7 ldq6 c nc - h9 pl2a 7 ldq6 t (lvds)* nc - j10 pl2b 7 ldq6 c (lvds)* nc - j20 nc - nc - j21 nc - nc - j9 pl4a 7 ldq6 t (lvds)* nc - k9 pl4b 7 ldq6 c (lvds)* nc - r9 nc - nc - u22 nc - nc - w9 nc - nc - n13 vccpll - vccpll - n18 vccpll - vccpll - v13 vccpll - vccpll - lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-205 pinout information lattice semiconductor latticeecp2 /m family data sheet v18 vccpll - vccpll - * supports true lvds. other differential si gnals must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. *** these sysconfig pins are dedicated i/o pi ns for configuration. the outpus are ac tively driven during normal device operati on. ****due to packaging bond out option, this dqs does not have al l the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc current drawn by i/os between g nd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one con- nection with a package ball or pin. lfe2m50e/se and lfe2m70e/se logi c signal connect ions: 900 fpbga lfe2m50e/se lfe2m70e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-206 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m100e/se logic signal connections: 900 fpbga lfe2m100e/se ball number ball/pad function ba nk dual function differential d2 pl9a 7 vref2_7 t d3 pl9b 7 vref1_7 c gndio gndio7 - j8 pl11a 7 lum0_spllt_in_a/ldq15 t (lvds)* h7 pl11b 7 lum0_spllc_in_a/ldq15 c (lvds)* e3 pl12a 7 lum0_spllt_fb_a/ldq15 t e4 pl12b 7 lum0_spllc_fb_a/ldq15 c g6 pl13a 7 ldq15 t (lvds)* f5 pl13b 7 ldq15 c (lvds)* e2 pl14a 7 ldq15 t d1 pl14b 7 ldq15 c gndio gndio7 - g5 pl15a 7 ldqs15 t (lvds)* g4 pl15b 7 ldq15 c (lvds)* k7 pl16a 7 ldq15 t k8 pl16b 7 ldq15 c e1 pl17a 7 ldq15 t (lvds)* f2 pl17b 7 ldq15 c (lvds)* f1 pl18a 7 ldq15 t gndio gndio7 - g3 pl18b 7 ldq15 c gndio gndio7 - h5 pl25a 7 ldq23 t (lvds)* h4 pl25b 7 ldq23 c (lvds)* j5 pl26a 7 ldq23 t j4 pl26b 7 ldq23 c gndio gndio7 - g2 pl28a 7 ldq32 t (lvds)* g1 pl28b 7 ldq32 c (lvds)* l9 pl29a 7 ldq32 t l7 pl29b 7 ldq32 c k6 pl30a 7 ldq32 t (lvds)* k5 pl30b 7 ldq32 c (lvds)* l8 pl31a 7 ldq32 t l6 pl31b 7 ldq32 c gndio gndio7 - h3 pl32a 7 ldqs32 t (lvds)* h2 pl32b 7 ldq32 c (lvds)* n8 pl33a 7 ldq32 t m9 pl33b 7 ldq32 c j3 pl34a 7 ldq32 t (lvds)* --- 4-207 pinout information lattice semiconductor latticeecp2 /m family data sheet j2 pl34b 7 ldq32 c (lvds)* h1 pl35a 7 ldq32 t gndio gndio7 - j1 pl35b 7 ldq32 c gndio gndio7 - l5 pl41a 7 ldq45 t (lvds)* l4 pl41b 7 ldq45 c (lvds)* n9 pl42a 7 ldq45 t n7 pl42b 7 ldq45 c k2 pl43a 7 ldq45 t (lvds)* k1 pl43b 7 ldq45 c (lvds)* p9 pl44a 7 ldq45 t p7 pl44b 7 ldq45 c gndio gndio7 - m6 pl45a 7 ldqs45 t (lvds)* m5 pl45b 7 ldq45 c (lvds)* n5 pl46a 7 ldq45 t n6 pl46b 7 ldq45 c m4 pl47a 7 ldq45 t (lvds)* m3 pl47b 7 ldq45 c (lvds)* p6 pl48a 7 ldq45 t gndio gndio7 - p8 pl48b 7 ldq45 c l3 pl50a 7 lum3_spllt_in_a/ldq54 t (lvds)* l2 pl50b 7 lum3_spllc_in_a/ldq54 c (lvds)* p5 pl51a 7 lum3_spllt_fb_a/ldq54 t p4 pl51b 7 lum3_spllc_fb_a/ldq54 c l1 pl52a 7 ldq54 t (lvds)* m2 pl52b 7 ldq54 c (lvds)* r5 pl53a 7 ldq54 t r4 pl53b 7 ldq54 c gndio gndio7 - m1 pl54a 7 ldqs54 t (lvds)* n2 pl54b 7 ldq54 c (lvds)* r8 pl55a 7 ldq54 t t9 pl55b 7 ldq54 c p3 pl56a 7 ldq54 t (lvds)* p2 pl56b 7 ldq54 c (lvds)* n1 pl57a 7 pclkt7_0/ldq54 t gndio gndio7 - p1 pl57b 7 pclkc7_0/ldq54 c t5 pl59a 6 pclkt6_0/ldq63 t (lvds)* t4 pl59b 6 pclkc6_0/ldq63 c (lvds)* lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-208 pinout information lattice semiconductor latticeecp2 /m family data sheet u7 pl60a 6 vref2_6/ldq63 t t8 pl60b 6 vref1_6/ldq63 c r3 pl61a 6 ldq63 t (lvds)* vccio vccio6 6 r2 pl61b 6 ldq63 c (lvds)* r1 pl62a 6 ldq63 t t1 pl62b 6 ldq63 c gndio gndio6 - vccio vccio6 6 t3 pl65a 6 llm4_spllt_in_a/ldq63 t (lvds)* t2 pl65b 6 llm4_spllc_in_a/ldq63 c (lvds)* u9 pl66a 6 llm4_spllt_fb_a/ldq63 t u8 pl66b 6 llm4_spllc_fb_a/ldq63 c gndio gndio6 - u5 pl68a 6 ldq72 t (lvds)* u4 pl68b 6 ldq72 c (lvds)* v9 pl69a 6 ldq72 t v7 pl69b 6 ldq72 c vccio vccio6 6 u3 pl70a 6 ldq72 t (lvds)* u2 pl70b 6 ldq72 c (lvds)* v8 pl71a 6 ldq72 t u6 pl71b 6 ldq72 c gndio gndio6 - u1 pl72a 6 ldqs72 t (lvds)* v2 pl72b 6 ldq72 c (lvds)* v5 pl73a 6 ldq72 t vccio vccio6 6 v6 pl73b 6 ldq72 c v1 pl74a 6 ldq72 t (lvds)* w1 pl74b 6 ldq72 c (lvds)* w5 pl75a 6 ldq72 t gndio gndio6 - w6 pl75b 6 ldq72 c w3 pl77a 6 ldq81 t (lvds)* w4 pl77b 6 ldq81 c (lvds)* w2 pl78a 6 ldq81 t y4 pl78b 6 ldq81 c y1 pl79a 6 ldq81 t (lvds)* vccio vccio6 6 y2 pl79b 6 ldq81 c (lvds)* y5 pl80a 6 ldq81 t y6 pl80b 6 ldq81 c lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-209 pinout information lattice semiconductor latticeecp2 /m family data sheet aa1 pl81a 6 ldqs81 t (lvds)* gndio gndio6 - aa2 pl81b 6 ldq81 c (lvds)* y3 pl82a 6 ldq81 t ab1 pl82b 6 ldq81 c vccio vccio6 6 y9 pl83a 6 ldq81 t (lvds)* y8 pl83b 6 ldq81 c (lvds)* y7 pl84a 6 ldq81 t aa7 pl84b 6 ldq81 c gndio gndio6 - vccio vccio6 6 ab2 pl95a 6 ldq99 t (lvds)* ab3 pl95b 6 ldq99 c (lvds)* aa5 pl96a 6 ldq99 t aa6 pl96b 6 ldq99 c ab4 pl97a 6 ldq99 t (lvds)* vccio vccio6 6 ab5 pl97b 6 ldq99 c (lvds)* aa8 pl98a 6 ldq99 t aa9 pl98b 6 ldq99 c ac1 pl99a 6 llm0_gpllt_in_a**/ldqs99 t (lvds)* gndio gndio6 - ac2 pl99b 6 llm0_gpllc_in_a**/ldq99 c (lvds)* ac4 pl100a 6 llm0_gpllt_fb_a/ldq99 t ac3 pl100b 6 llm0_gpllc_fb_a/ldq99 c vccio vccio6 6 ac7 pl101a 6 llm0_gdllt_in_a**/ldq99 t (lvds)* ac6 pl101b 6 llm0_gdllc_in_a**/ldq99 c (lvds)* ac5 pl102a 6 llm0_gdllt_fb_a/ldq99 t ad3 pl102b 6 llm0_gdllc_fb_a/ldq99 c gndio gndio6 - ab8 llm0_pllcap 6 ad2 pl104a 6 t ad1 pl104b 6 c ae2 tck - ae1 tdi - af2 tms - af1 tdo - ag1 vccj - ah1 llc_sq_vccrx3 14 ak2 llc_sq_hdinp3 14 t aj1 llc_sq_vccib3 14 lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-210 pinout information lattice semiconductor latticeecp2 /m family data sheet aj2 llc_sq_hdinn3 14 c ah4 llc_sq_vcctx3 14 ak5 llc_sq_hdoutp3 14 t ak4 llc_sq_vccob3 14 aj5 llc_sq_hdoutn3 14 c ah5 llc_sq_vcctx2 14 aj6 llc_sq_hdoutn2 14 c ah6 llc_sq_vccob2 14 ak6 llc_sq_hdoutp2 14 t ah2 llc_sq_vccrx2 14 aj3 llc_sq_hdinn2 14 c ah3 llc_sq_vccib2 14 ak3 llc_sq_hdinp2 14 t ah7 llc_sq_vccp 14 ag7 llc_sq_refclkp 14 t af7 llc_sq_refclkn 14 c aj7 llc_sq_vccaux33 14 ak11 llc_sq_hdinp1 14 t ah11 llc_sq_vccib1 14 aj11 llc_sq_hdinn1 14 c ah12 llc_sq_vccrx1 14 ak8 llc_sq_hdoutp1 14 t ah8 llc_sq_vccob1 14 aj8 llc_sq_hdoutn1 14 c ah9 llc_sq_vcctx1 14 aj9 llc_sq_hdoutn0 14 c ak10 llc_sq_vccob0 14 ak9 llc_sq_hdoutp0 14 t ah10 llc_sq_vcctx0 14 aj12 llc_sq_hdinn0 14 c aj13 llc_sq_vccib0 14 ak12 llc_sq_hdinp0 14 t ah13 llc_sq_vccrx0 14 af10 pb30a 5 bdq33 t ae8 pb30b 5 bdq33 c ae11 pb31a 5 bdq33 t vccio vccio5 5 ad9 pb31b 5 bdq33 c ae10 pb32a 5 bdq33 t ad10 pb32b 5 bdq33 c ae13 pb33a 5 bdqs33 t gndio gndio5 - ac12 pb33b 5 bdq33 c lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-211 pinout information lattice semiconductor latticeecp2 /m family data sheet ag2 pb34a 5 bdq33 t ag3 pb34b 5 bdq33 c ad13 pb35a 5 bdq33 t vccio vccio5 5 ac13 pb35b 5 bdq33 c ae14 pb36a 5 bdq33 t ac14 pb36b 5 bdq33 c af3 pb37a 5 bdq33 t gndio gndio5 - af4 pb37b 5 bdq33 c --- ag4 pb38a 5 bdq42 t ag5 pb38b 5 bdq42 c gndio gndio5 - --- ad11 pb48a 5 bdq51 t af13 pb48b 5 bdq51 c af12 pb49a 5 bdq51 t vccio vccio5 5 ad14 pb49b 5 bdq51 c ag8 pb50a 5 bdq51 t af8 pb50b 5 bdq51 c ae15 pb51a 5 bdqs51**** t gndio gndio5 - --- ac15 pb51b 5 bdq51 c vccio vccio5 5 gndio gndio5 - ad15 pb56a 5 bdq60 t af15 pb56b 5 bdq60 c ag10 pb57a 5 bdq60 t ag9 pb57b 5 bdq60 c ah14 pb58a 5 bdq60 t ag12 pb58b 5 bdq60 c vccio vccio5 5 ag15 pb59a 5 bdq60 t ag13 pb59b 5 bdq60 c gndio gndio5 - af16 pb60a 5 bdqs60 t ah15 pb60b 5 bdq60 c ac16 pb61a 5 vref2_5/bdq60 t ae16 pb61b 5 vref1_5/bdq60 c ag11 pb62a 5 pclkt5_0/bdq60 t lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-212 pinout information lattice semiconductor latticeecp2 /m family data sheet af11 pb62b 5 pclkc5_0/bdq60 c vccio vccio5 5 gndio gndio5 - aj14 pb67a 4 pclkt4_0/bdq69 t vccio vccio4 4 ak14 pb67b 4 pclkc4_0/bdq69 c ak15 pb68a 4 vref2_4/bdq69 t ak16 pb68b 4 vref1_4/bdq69 c af18 pb69a 4 bdqs69 t gndio gndio4 - ad16 pb69b 4 bdq69 c aj15 pb70a 4 bdq69 t ag16 pb70b 4 bdq69 c ae17 pb71a 4 bdq69 t vccio vccio4 4 ac17 pb71b 4 bdq69 c ah16 pb72a 4 bdq69 t ak17 pb72b 4 bdq69 c ag20 pb73a 4 bdq69 t gndio gndio4 - ag21 pb73b 4 bdq69 c ag18 pb74a 4 bdq78 t aj16 pb74b 4 bdq78 c af21 pb75a 4 bdq78 t ag22 pb75b 4 bdq78 c ad17 pb76a 4 bdq78 t af19 pb76b 4 bdq78 c vccio vccio4 4 gndio gndio4 - ah17 pb80a 4 bdq78 t aj17 pb80b 4 bdq78 c vccio vccio4 4 af26 pb82a 4 bdq78 t ae25 pb82b 4 bdq78 c gndio gndio4 - ad24 pb92a 4 bdq96 t ae24 pb92b 4 bdq96 c ad18 pb93a 4 bdq96 t ac18 pb93b 4 bdq96 c ae18 pb94a 4 bdq96 t ag19 pb94b 4 bdq96 c vccio vccio4 4 gndio gndio4 - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-213 pinout information lattice semiconductor latticeecp2 /m family data sheet ac19 pb96a 4 bdqs96 t ad20 pb96b 4 bdq96 c ab18 pb97a 4 bdq96 t ac20 pb97b 4 bdq96 c ae20 pb98a 4 bdq96 t ae21 pb98b 4 bdq96 c vccio vccio4 4 ac23 pb99a 4 bdq96 t ad23 pb99b 4 bdq96 c gndio gndio4 - ah18 lrc_sq_vccrx3 13 ak19 lrc_sq_hdinp3 13 t aj18 lrc_sq_vccib3 13 aj19 lrc_sq_hdinn3 13 c ah21 lrc_sq_vcctx3 13 ak22 lrc_sq_hdoutp3 13 t ak21 lrc_sq_vccob3 13 aj22 lrc_sq_hdoutn3 13 c ah22 lrc_sq_vcctx2 13 aj23 lrc_sq_hdoutn2 13 c ah23 lrc_sq_vccob2 13 ak23 lrc_sq_hdoutp2 13 t ah19 lrc_sq_vccrx2 13 aj20 lrc_sq_hdinn2 13 c ah20 lrc_sq_vccib2 13 ak20 lrc_sq_hdinp2 13 t ah24 lrc_sq_vccp 13 ag24 lrc_sq_refclkp 13 t af24 lrc_sq_refclkn 13 c aj24 lrc_sq_vccaux33 13 ak28 lrc_sq_hdinp1 13 t ah28 lrc_sq_vccib1 13 aj28 lrc_sq_hdinn1 13 c ah29 lrc_sq_vccrx1 13 ak25 lrc_sq_hdoutp1 13 t ah25 lrc_sq_vccob1 13 aj25 lrc_sq_hdoutn1 13 c ah26 lrc_sq_vcctx1 13 aj26 lrc_sq_hdoutn0 13 c ak27 lrc_sq_vccob0 13 ak26 lrc_sq_hdoutp0 13 t ah27 lrc_sq_vcctx0 13 aj29 lrc_sq_hdinn0 13 c lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-214 pinout information lattice semiconductor latticeecp2 /m family data sheet aj30 lrc_sq_vccib0 13 ak29 lrc_sq_hdinp0 13 t ah30 lrc_sq_vccrx0 13 ag27 cfg2 8 ad25 cfg1 8 ag28 cfg0 8 ag30 programn 8 ag29 cclk 8 ac24 initn 8 af27 done 8 gndio gndio8 - af28 writen*** 8 ae26 cs1n*** 8 ab23 csn*** 8 af29 d0/spifastn*** 8 vccio vccio8 8 af30 d1*** 8 ad26 d2*** 8 ae29 d3*** 8 gndio gndio8 - ae30 d4*** 8 ad29 d5*** 8 ac25 d6*** 8 ad30 d7*** 8 vccio vccio8 8 aa22 di/csspi0n*** 8 ac26 dout/cson/csspi1n*** 8 aa23 busy/sispi*** 8 ab22 rlm0_pllcap 3 ac27 pr102b 3 rlm0_gdllc_fb_a/rdq99 c gndio gndio3 - ac28 pr102a 3 rlm0_gdllt_fb_a/rdq99 t ac29 pr101b 3 rlm0_gdllc_in_a**/rdq99 c (lvds)* ac30 pr101a 3 rlm0_gdllt_in_a**/rdq99 t (lvds)* ab30 pr100b 3 rlm0_gpllc_in_a**/rdq99 c vccio vccio3 3 aa30 pr100a 3 rlm0_gpllt_in_a**/rdq99 t ab29 pr99b 3 rlm0_gpllc_fb_a/rdq99 c (lvds)* ab28 pr99a 3 rlm0_gpllt_fb_a/rdqs99 t (lvds)* gndio gndio3 - y22 pr98b 3 rdq99 c y23 pr98a 3 rdq99 t ab26 pr97b 3 rdq99 c (lvds)* lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-215 pinout information lattice semiconductor latticeecp2 /m family data sheet ab27 pr97a 3 rdq99 t (lvds)* vccio vccio3 3 y24 pr96b 3 rdq99 c y25 pr96a 3 rdq99 t aa29 pr95b 3 rdq99 c (lvds)* y28 pr95a 3 rdq99 t (lvds)* y30 pr93b 3 rdq90 c y29 pr93a 3 rdq90 t gndio gndio3 - vccio vccio3 3 w22 pr83b 3 rdq81 c (lvds)* v22 pr83a 3 rdq81 t (lvds)* y27 pr82b 3 rdq81 c vccio vccio3 3 y26 pr82a 3 rdq81 t w30 pr81b 3 rdq81 c (lvds)* w29 pr81a 3 rdqs81 t (lvds)* gndio gndio3 - w25 pr80b 3 rdq81 c w26 pr80a 3 rdq81 t u29 pr79b 3 rdq81 c (lvds)* v29 pr79a 3 rdq81 t (lvds)* vccio vccio3 3 v30 pr78b 3 rdq81 c u30 pr78a 3 rdq81 t w27 pr77b 3 rdq81 c (lvds)* w28 pr77a 3 rdq81 t (lvds)* v24 pr75b 3 rdq72 c v25 pr75a 3 rdq72 t gndio gndio3 - u28 pr74b 3 rdq72 c (lvds)* u27 pr74a 3 rdq72 t (lvds)* u23 pr73b 3 rdq72 c v23 pr73a 3 rdq72 t vccio vccio3 3 v26 pr72b 3 rdq72 c (lvds)* u26 pr72a 3 rdqs72 t (lvds)* u25 pr71b 3 rdq72 c gndio gndio3 - u24 pr71a 3 rdq72 t t30 pr70b 3 rdq72 c (lvds)* r30 pr70a 3 rdq72 t (lvds)* t23 pr69b 3 rdq72 c lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-216 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio3 3 t22 pr69a 3 rdq72 t t29 pr68b 3 rdq72 c (lvds)* t28 pr68a 3 rdq72 t (lvds)* r23 pr66b 3 rlm4_spllc_fb_a/rdq63 c gndio gndio3 - --- r22 pr66a 3 rlm4_spllt_fb_a/rdq63 t p30 pr65b 3 rlm4_spllc_in_a/rdq63 c (lvds)* r29 pr65a 3 rlm4_spllt_i n_a/rdq63 t (lvds)* t27 pr64b 3 rdq63 c vccio vccio3 3 t26 pr64a 3 rdq63 t gndio gndio3 - n30 pr61b 3 rdq63 c (lvds)* n29 pr61a 3 rdq63 t (lvds)* vccio vccio3 3 r27 pr60b 3 vref2_3/rdq63 c r28 pr60a 3 vref1_3/rdq63 t p29 pr59b 3 pclkc3_0/rdq63 c (lvds)* p28 pr59a 3 pclkt3_0/rdq63 t (lvds)* m30 pr57b 2 pclkc2_0/rdq54 c m29 pr57a 2 pclkt2_0/rdq54 t gndio gndio2 - p23 pr56b 2 rdq54 c (lvds)* p24 pr56a 2 rdq54 t (lvds)* r26 pr55b 2 rdq54 c p27 pr55a 2 rdq54 t vccio vccio2 2 p25 pr54b 2 rdq54 c (lvds)* p26 pr54a 2 rdqs54 t (lvds)* k30 pr53b 2 rdq54 c gndio gndio2 - k29 pr53a 2 rdq54 t n22 pr52b 2 rdq54 c (lvds)* p22 pr52a 2 rdq54 t (lvds)* j30 pr51b 2 rum3_spllc_fb_a/rdq54 c vccio vccio2 2 j29 pr51a 2 rum3_spllt_fb_a/rdq54 t n24 pr50b 2 rum3_spllc_in_a/rdq54 c (lvds)* n23 pr50a 2 rum3_spllt_in_a/rdq54 t (lvds)* n25 pr48b 2 rdq45 c n26 pr48a 2 rdq45 t lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-217 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio2 - m27 pr47b 2 rdq45 c (lvds)* m28 pr47a 2 rdq45 t (lvds)* h30 pr46b 2 rdq45 c g30 pr46a 2 rdq45 t vccio vccio2 2 m25 pr45b 2 rdq45 c (lvds)* m26 pr45a 2 rdqs45 t (lvds)* l30 pr44b 2 rdq45 c gndio gndio2 - l29 pr44a 2 rdq45 t l28 pr43b 2 rdq45 c (lvds)* l27 pr43a 2 rdq45 t (lvds)* h29 pr42b 2 rdq45 c vccio vccio2 2 g29 pr42a 2 rdq45 t l22 pr41b 2 rdq45 c (lvds)* m22 pr41a 2 rdq45 t (lvds)* f30 pr40b 2 c gndio gndio2 - f29 pr40a 2 t vccio vccio2 2 gndio gndio2 - e30 pr34b 2 rdq32 c (lvds)* e29 pr34a 2 rdq32 t (lvds)* --- l25 pr33b 2 rdq32 c l26 pr33a 2 rdq32 t vccio vccio2 2 h28 pr32b 2 rdq32 c (lvds)* j28 pr32a 2 rdqs32 t (lvds)* g28 pr31b 2 rdq32 c gndio gndio2 - g27 pr31a 2 rdq32 t l24 pr30b 2 rdq32 c (lvds)* l23 pr30a 2 rdq32 t (lvds)* d30 pr29b 2 rdq32 c vccio vccio2 2 d29 pr29a 2 rdq32 t k24 pr28b 2 rdq32 c (lvds)* k25 pr28a 2 rdq32 t (lvds)* j27 pr26b 2 rdq23 c gndio gndio2 - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-218 pinout information lattice semiconductor latticeecp2 /m family data sheet k26 pr26a 2 rdq23 t k23 pr25b 2 rdq23 c (lvds)* k22 pr25a 2 rdq23 t (lvds)* j22 pr24b 2 rdq23 c vccio vccio2 2 j23 pr24a 2 rdq23 t gndio gndio2 - vccio vccio2 2 j26 pr17b 2 rdq15 c (lvds)* h26 pr17a 2 rdq15 t (lvds)* h27 pr16b 2 rdq15 c g26 pr16a 2 rdq15 t vccio vccio2 2 h23 pr15b 2 rdq15 c (lvds)* h24 pr15a 2 rdqs15 t (lvds)* d28 pr14b 2 rdq15 c gndio gndio2 - e28 pr14a 2 rdq15 t g24 pr13b 2 rdq15 c (lvds)* h25 pr13a 2 rdq15 t (lvds)* d27 pr12b 2 rum0_spllc_fb_a/rdq15 c vccio vccio2 2 e27 pr12a 2 rum0_spllt_fb_a/rdq15 t f26 pr11b 2 rum0_spllc_in_a/rdq15 c (lvds)* g25 pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* f24 pr9b 2 vref2_2 c --- gndio gndio2 - f25 pr9a 2 vref1_2 t vccio vccio2 2 g23 xres 1 c30 urc_sq_vccrx0 12 a29 urc_sq_hdinp0 12 t b30 urc_sq_vccib0 12 b29 urc_sq_hdinn0 12 c c27 urc_sq_vcctx0 12 a26 urc_sq_hdoutp0 12 t a27 urc_sq_vccob0 12 b26 urc_sq_hdoutn0 12 c c26 urc_sq_vcctx1 12 b25 urc_sq_hdoutn1 12 c c25 urc_sq_vccob1 12 a25 urc_sq_hdoutp1 12 t lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-219 pinout information lattice semiconductor latticeecp2 /m family data sheet c29 urc_sq_vccrx1 12 b28 urc_sq_hdinn1 12 c c28 urc_sq_vccib1 12 a28 urc_sq_hdinp1 12 t b24 urc_sq_vccaux33 12 e24 urc_sq_refclkn 12 c d24 urc_sq_refclkp 12 t c24 urc_sq_vccp 12 a20 urc_sq_hdinp2 12 t c20 urc_sq_vccib2 12 b20 urc_sq_hdinn2 12 c c19 urc_sq_vccrx2 12 a23 urc_sq_hdoutp2 12 t c23 urc_sq_vccob2 12 b23 urc_sq_hdoutn2 12 c c22 urc_sq_vcctx2 12 b22 urc_sq_hdoutn3 12 c a21 urc_sq_vccob3 12 a22 urc_sq_hdoutp3 12 t c21 urc_sq_vcctx3 12 b19 urc_sq_hdinn3 12 c b18 urc_sq_vccib3 12 a19 urc_sq_hdinp3 12 t c18 urc_sq_vccrx3 12 d23 pt100b 1 c gndio gndio1 - e21 pt100a 1 t d26 pt99b 1 c e26 pt99a 1 t e23 pt98b 1 c vccio vccio1 1 g22 pt98a 1 t --- d22 pt97b 1 c f21 pt97a 1 t g18 pt96b 1 c h18 pt96a 1 t d20 pt95b 1 c gndio gndio1 - d21 pt95a 1 t e20 pt94b 1 c vccio vccio1 1 e19 pt94a 1 t lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-220 pinout information lattice semiconductor latticeecp2 /m family data sheet d19 pt93b 1 c e18 pt93a 1 t d18 pt92b 1 c c17 pt92a 1 t a17 pt91b 1 c b17 pt91a 1 t gndio gndio1 - vccio vccio1 1 j18 pt75b 1 c j19 pt75a 1 t h17 pt74b 1 c j17 pt74a 1 t f18 pt73b 1 c f17 pt73a 1 t gndio gndio1 - a16 pt72b 1 c b16 pt72a 1 t g17 pt71b 1 c g16 pt71a 1 t vccio vccio1 1 h16 pt70b 1 c f16 pt70a 1 t j16 pt69b 1 c g15 pt69a 1 t gndio gndio1 - c16 pt68b 1 c d16 pt68a 1 t j15 pt67b 1 c h15 pt67a 1 t vccio vccio1 1 a15 pt66b 1 vref2_1 c b15 pt66a 1 vref1_1 t f15 pt65b 1 pclkc1_0 c e16 pt65a 1 pclkt1_0 t c15 pt64b 0 pclkc0_0 c gndio gndio0 - d15 pt64a 0 pclkt0_0 t c14 pt63b 0 vref2_0 c e15 pt63a 0 vref1_0 t g14 pt62b 0 c vccio vccio0 0 j14 pt62a 0 t f14 pt61b 0 c lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-221 pinout information lattice semiconductor latticeecp2 /m family data sheet h14 pt61a 0 t a14 pt60b 0 c b14 pt60a 0 t d13 pt59b 0 c gndio gndio0 - f13 pt59a 0 t g13 pt58b 0 c vccio vccio0 0 j11 pt58a 0 t d4 pt57b 0 d5 pt56a 0 e5 pt55b 0 c f6 pt55a 0 t gndio gndio0 - vccio vccio0 0 f7 pt52b 0 c d8 pt52a 0 t gndio gndio0 - j13 pt50b 0 c g11 pt50a 0 t h13 pt49b 0 c h12 pt49a 0 t vccio vccio0 0 e8 pt48b 0 c d9 pt48a 0 t d12 pt46b 0 c gndio gndio0 - e13 pt46a 0 t vccio vccio0 0 gndio gndio0 - j12 pt31b 0 c --- vccio vccio0 0 h10 pt31a 0 t e12 pt30b 0 c d11 pt30a 0 t h11 pt29b 0 c f11 pt29a 0 t c13 ulc_sq_vccrx0 11 a12 ulc_sq_hdinp0 11 t b13 ulc_sq_vccib0 11 b12 ulc_sq_hdinn0 11 c c10 ulc_sq_vcctx0 11 lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-222 pinout information lattice semiconductor latticeecp2 /m family data sheet a9 ulc_sq_hdoutp0 11 t a10 ulc_sq_vccob0 11 b9 ulc_sq_hdoutn0 11 c c9 ulc_sq_vcctx1 11 b8 ulc_sq_hdoutn1 11 c c8 ulc_sq_vccob1 11 a8 ulc_sq_hdoutp1 11 t c12 ulc_sq_vccrx1 11 b11 ulc_sq_hdinn1 11 c c11 ulc_sq_vccib1 11 a11 ulc_sq_hdinp1 11 t b7 ulc_sq_vccaux33 11 e7 ulc_sq_refclkn 11 c d7 ulc_sq_refclkp 11 t c7 ulc_sq_vccp 11 a3 ulc_sq_hdinp2 11 t c3 ulc_sq_vccib2 11 b3 ulc_sq_hdinn2 11 c c2 ulc_sq_vccrx2 11 a6 ulc_sq_hdoutp2 11 t c6 ulc_sq_vccob2 11 b6 ulc_sq_hdoutn2 11 c c5 ulc_sq_vcctx2 11 b5 ulc_sq_hdoutn3 11 c a4 ulc_sq_vccob3 11 a5 ulc_sq_hdoutp3 11 t c4 ulc_sq_vcctx3 11 b2 ulc_sq_hdinn3 11 c b1 ulc_sq_vccib3 11 a2 ulc_sq_hdinp3 11 t c1 ulc_sq_vccrx3 11 l12 vcc - l13 vcc - l18 vcc - l19 vcc - m11 vcc - m12 vcc - m13 vcc - m14 vcc - m15 vcc - m16 vcc - m17 vcc - m18 vcc - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-223 pinout information lattice semiconductor latticeecp2 /m family data sheet m19 vcc - m20 vcc - n11 vcc - n12 vcc - n19 vcc - n20 vcc - p12 vcc - p19 vcc - r12 vcc - r19 vcc - t12 vcc - t19 vcc - u12 vcc - u19 vcc - v11 vcc - v12 vcc - v19 vcc - v20 vcc - w11 vcc - w12 vcc - w13 vcc - w14 vcc - w15 vcc - w16 vcc - w17 vcc - w18 vcc - w19 vcc - w20 vcc - y12 vcc - y13 vcc - y18 vcc - y19 vcc - d14 vccio0 0 e6 vccio0 0 e9 vccio0 0 f12 vccio0 0 k12 vccio0 0 k13 vccio0 0 d17 vccio1 1 e22 vccio1 1 e25 vccio1 1 f19 vccio1 1 k18 vccio1 1 lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-224 pinout information lattice semiconductor latticeecp2 /m family data sheet k19 vccio1 1 f28 vccio2 2 j25 vccio2 2 k28 vccio2 2 m21 vccio2 2 m24 vccio2 2 n21 vccio2 2 n28 vccio2 2 p21 vccio2 2 r25 vccio2 2 aa28 vccio3 3 ab25 vccio3 3 ae28 vccio3 3 t25 vccio3 3 u21 vccio3 3 v21 vccio3 3 v28 vccio3 3 w21 vccio3 3 w24 vccio3 3 aa18 vccio4 4 aa19 vccio4 4 ae19 vccio4 4 af22 vccio4 4 ag17 vccio4 4 ag25 vccio4 4 aa12 vccio5 5 aa13 vccio5 5 ae12 vccio5 5 af9 vccio5 5 ag14 vccio5 5 ag6 vccio5 5 aa3 vccio6 6 ab6 vccio6 6 ae3 vccio6 6 t6 vccio6 6 u10 vccio6 6 v10 vccio6 6 v3 vccio6 6 w10 vccio6 6 w7 vccio6 6 f3 vccio7 7 j6 vccio7 7 k3 vccio7 7 lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-225 pinout information lattice semiconductor latticeecp2 /m family data sheet m10 vccio7 7 m7 vccio7 7 n10 vccio7 7 n3 vccio7 7 p10 vccio7 7 r6 vccio7 7 aa25 vccio8 8 ad28 vccio8 8 aa10 vccaux - aa11 vccaux - aa20 vccaux - aa21 vccaux - k10 vccaux - k11 vccaux - k20 vccaux - k21 vccaux - l10 vccaux - l11 vccaux - l20 vccaux - l21 vccaux - y10 vccaux - y11 vccaux - y20 vccaux - y21 vccaux - a1 gnd - a13 gnd - a18 gnd - a24 gnd - a30 gnd - a7 gnd - aa14 gnd - aa15 gnd - aa16 gnd - aa17 gnd - aa24 gnd - aa27 gnd - aa4 gnd - ab24 gnd - ab7 gnd - ad12 gnd - ad19 gnd - ad27 gnd - ae22 gnd - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-226 pinout information lattice semiconductor latticeecp2 /m family data sheet ae27 gnd - ae4 gnd - ae9 gnd - af14 gnd - af17 gnd - af25 gnd - af6 gnd - aj10 gnd - aj21 gnd - aj27 gnd - aj4 gnd - ak1 gnd - ak13 gnd - ak18 gnd - ak24 gnd - ak30 gnd - ak7 gnd - b10 gnd - b21 gnd - b27 gnd - b4 gnd - d25 gnd - d6 gnd - e14 gnd - e17 gnd - f22 gnd - f27 gnd - f4 gnd - f9 gnd - g12 gnd - g19 gnd - j24 gnd - j7 gnd - k14 gnd - k15 gnd - k16 gnd - k17 gnd - k27 gnd - k4 gnd - l14 gnd - l15 gnd - l16 gnd - l17 gnd - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-227 pinout information lattice semiconductor latticeecp2 /m family data sheet m23 gnd - m8 gnd - n14 gnd - n15 gnd - n16 gnd - n17 gnd - n27 gnd - n4 gnd - p11 gnd - p13 gnd - p14 gnd - p15 gnd - p16 gnd - p17 gnd - p18 gnd - p20 gnd - r10 gnd - r11 gnd - r13 gnd - r14 gnd - r15 gnd - r16 gnd - r17 gnd - r18 gnd - r20 gnd - r21 gnd - r24 gnd - r7 gnd - t10 gnd - t11 gnd - t13 gnd - t14 gnd - t15 gnd - t16 gnd - t17 gnd - t18 gnd - t20 gnd - t21 gnd - t24 gnd - t7 gnd - u11 gnd - u13 gnd - u14 gnd - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-228 pinout information lattice semiconductor latticeecp2 /m family data sheet u15 gnd - u16 gnd - u17 gnd - u18 gnd - u20 gnd - v14 gnd - v15 gnd - v16 gnd - v17 gnd - v27 gnd - v4 gnd - w23 gnd - w8 gnd - y14 gnd - y15 gnd - y16 gnd - y17 gnd - aa26 nc - ab10 nc - ab11 nc - ab12 nc - ab13 nc - ab14 nc - ab15 nc - ab16 nc - ab17 nc - ab19 nc - ab20 nc - ab21 nc - ab9 nc - ac10 nc - ac11 nc - ac21 nc - ac22 nc - ac8 nc - ac9 nc - ad21 nc - ad22 nc - ad4 nc - ad5 nc - ad6 nc - ad7 nc - ad8 nc - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-229 pinout information lattice semiconductor latticeecp2 /m family data sheet ae23 nc - ae5 nc - ae6 nc - ae7 nc - af20 nc - af23 nc - af5 nc - ag23 nc - ag26 nc - d10 nc - e10 nc - e11 nc - f10 nc - f20 nc - f23 nc - f8 nc - g10 nc - g20 nc - g21 nc - g7 nc - g8 nc - g9 nc - h19 nc - h20 nc - h21 nc - h22 nc - h6 nc - h8 nc - h9 nc - j10 nc - j20 nc - j21 nc - j9 nc - k9 nc - r9 nc - u22 nc - w9 nc - n13 vccpll - n18 vccpll - v13 vccpll - lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-230 pinout information lattice semiconductor latticeecp2 /m family data sheet v18 vccpll - * supports true lvds. other differential si gnals must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. *** these sysconfig pins are dedicated i/o pi ns for configuration. the outpus are ac tively driven during normal device operati on. ****due to packaging bond out option, this dqs does not have al l the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc cu rrent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the substrate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2m100e/se logic signal co nnections: 900 fpbga (cont.) lfe2m100e/se ball number ball/pad function ba nk dual function differential 4-231 pinout information lattice semiconductor latticeecp2 /m family data sheet lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential vccio vccio7 7 vccio7 7 f4 pl9a 7 vref2_7 t pl9a 7 vref2_7 t f3 pl9b 7 vref1_7 c pl9b 7 vref1_7 c gndio gndio7 - gndio7 - e1 pl11a 7 lum0_spllt_in_a/ld q15 t (lvds)* pl11a 7 lum0_spl lt_in_a/ldq15 t (lvds)* e2 pl11b 7 lum0_spllc_in_a/ldq15 c (lvds) * pl11b 7 lum0_spllc_in_ a/ldq15 c (lvds)* k9 pl12a 7 lum0_spllt_fb_a/ldq15 t pl12a 7 lum0_spllt_fb_a/ldq15 t h7 pl12b 7 lum0_spllc_f b_a/ldq15 c pl12b 7 lum0 _spllc_fb_a/ldq15 c vccio vccio7 7 vccio7 7 f1 pl13a 7 ldq15 t (lvds)* pl13a 7 ldq15 t (lvds)* f2 pl13b 7 ldq15 c (lvds)* pl13b 7 ldq15 c (lvds)* j8 pl14a 7 ldq15 t pl14a 7 ldq15 t h6 pl14b 7 ldq15 c pl14b 7 ldq15 c gndio gndio7 - gndio7 - g2 pl15a 7 ldqs15 t (lvds)* pl15a 7 ldqs15 t (lvds)* g1 pl15b 7 ldq15 c (lvds)* pl15b 7 ldq15 c (lvds)* j7 pl16a 7 ldq15 t pl16a 7 ldq15 t vccio vccio7 7 vccio7 7 l8 pl16b 7 ldq15 c pl16b 7 ldq15 c l9 pl17a 7 ldq15 t (lvds)* pl17a 7 ldq15 t (lvds)* l10 pl17b 7 ldq15 c (lvds)* pl17b 7 ldq15 c (lvds)* h5 pl18a 7 ldq15 t pl18a 7 ldq15 t gndio gndio7 - gndio7 - j6 pl18b 7 ldq15 c pl18b 7 ldq15 c h2 nc - pl19a 7 ldq23 t (lvds)* h1 nc - pl19b 7 ldq23 c (lvds)* g5 nc - pl20a 7 ldq23 t g6 nc - pl20b 7 ldq23 c m9 nc - pl21a 7 ldq23 t (lvds)* - - - vccio7 7 m10 nc - pl21b 7 ldq23 c (lvds)* h3 nc - pl22a 7 ldq23 t h4 nc - pl22b 7 ldq23 c j2 pl19a 7 t (lvds)* pl23a 7 ldqs23 t (lvds)* - - - gndio7 - j1 pl19b 7 c (lvds)* pl23b 7 ldq23 c (lvds)* k2 pl20a 7 t pl24a 7 ldq23 t k1 pl20b 7 c pl24b 7 ldq23 c vccio vccio7 7 vccio7 7 j4 pl21a 7 t (lvds)* pl25a 7 ldq23 t (lvds)* j3 pl21b 7 c (lvds)* pl25b 7 ldq23 c (lvds)* j5 pl22a 7 t pl26a 7 ldq23 t k5 pl22b 7 c pl26b 7 ldq23 c gndio gndio7 - gndio7 - l2 pl24a 7 ldq28 t (lvds)* pl28a 7 ldq32 t (lvds)* l1 pl24b 7 ldq28 c (lvds)* pl28b 7 ldq32 c (lvds)* l7 pl25a 7 ldq28 t pl29a 7 ldq32 t k6 pl25b 7 ldq28 c pl29b 7 ldq32 c vccio vccio7 7 vccio7 7 m2 pl26a 7 ldq28 t (lvds)* pl30a 7 ldq32 t (lvds)* 4-232 pinout information lattice semiconductor latticeecp2 /m family data sheet m1 pl26b 7 ldq28 c (lvds)* pl30b 7 ldq32 c (lvds)* l6 pl27a 7 ldq28 t pl31a 7 ldq32 t l5 pl27b 7 ldq28 c pl31b 7 ldq32 c gndio gndio7 - gndio7 - l3 pl28a 7 ldqs28 t (lvds)* pl32a 7 ldqs32 t (lvds)* l4 pl28b 7 ldq28 c (lvds)* pl32b 7 ldq32 c (lvds)* m3 pl29a 7 ldq28 t pl33a 7 ldq32 t vccio vccio7 7 vccio7 7 m4 pl29b 7 ldq28 c pl33b 7 ldq32 c n1 pl30a 7 ldq28 t (lvds)* pl34a 7 ldq32 t (lvds)* n2 pl30b 7 ldq28 c (lvds)* pl34b 7 ldq32 c (lvds)* m5 pl31a 7 ldq28 t pl35a 7 ldq32 t gndio gndio7 - gndio7 - n6 pl31b 7 ldq28 c pl35b 7 ldq32 c p3 nc - pl37a 7 t (lvds)* - - - gndio7 - p4 nc - pl37b 7 c (lvds)* p9 nc - pl38a 7 t m7 nc - pl38b 7 c - - - vccio7 7 p1 nc - pl39a 7 t (lvds)* p2 nc - pl39b 7 c (lvds)* n7 nc - pl40a 7 t p7 nc - pl40b 7 c - - - gndio7 - p5 pl33a 7 ldq37 t (lvds)* pl41a 7 ldq45 t (lvds)* n5 pl33b 7 ldq37 c (lvds)* pl41b 7 ldq45 c (lvds)* p8 pl34a 7 ldq37 t pl42a 7 ldq45 t p6 pl34b 7 ldq37 c pl42b 7 ldq45 c vccio vccio7 7 vccio7 7 r3 pl35a 7 ldq37 t (lvds)* pl43a 7 ldq45 t (lvds)* r4 pl35b 7 ldq37 c (lvds)* pl43b 7 ldq45 c (lvds)* r10 pl36a 7 ldq37 t pl44a 7 ldq45 t p11 pl36b 7 ldq37 c pl44b 7 ldq45 c gndio gndio7 - gndio7 - r7 pl37a 7 ldqs37 t (lvds)* pl45a 7 ldqs45 t (lvds)* r8 pl37b 7 ldq37 c (lvds)* pl45b 7 ldq45 c (lvds)* r5 pl38a 7 ldq37 t pl46a 7 ldq45 t vccio vccio7 7 vccio7 7 t5 pl38b 7 ldq37 c pl46b 7 ldq45 c r1 pl39a 7 ldq37 t (lvds)* pl47a 7 ldq45 t (lvds)* r2 pl39b 7 ldq37 c (lvds)* pl47b 7 ldq45 c (lvds)* r11 pl40a 7 ldq37 t pl48a 7 ldq45 t gndio gndio7 - gndio7 - t10 pl40b 7 ldq37 c pl48b 7 ldq45 c t1 pl42a 7 lum3_spllt_in_a/ld q46 t (lvds)* pl50a 7 lum3_spl lt_in_a/ldq54 t (lvds)* t2 pl42b 7 lum3_spllc_in_a/ldq46 c (lvds) * pl50b 7 lum3_spllc_in_ a/ldq54 c (lvds)* u10 pl43a 7 lum3_spllt_fb_a/ldq46 t pl51a 7 lum3_spllt_fb_a/ldq54 t u8 pl43b 7 lum3_spllc_f b_a/ldq46 c pl51b 7 lum3 _spllc_fb_a/ldq54 c vccio vccio7 7 vccio7 7 t6 pl44a 7 ldq46 t (lvds)* pl52a 7 ldq54 t (lvds)* lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-233 pinout information lattice semiconductor latticeecp2 /m family data sheet r6 pl44b 7 ldq46 c (lvds)* pl52b 7 ldq54 c (lvds)* u9 pl45a 7 ldq46 t pl53a 7 ldq54 t t7 pl45b 7 ldq46 c pl53b 7 ldq54 c gndio gndio7 - gndio7 - u5 pl46a 7 ldqs46 t (lvds)* pl54a 7 ldqs54 t (lvds)* u6 pl46b 7 ldq46 c (lvds)* pl54b 7 ldq54 c (lvds)* u7 pl47a 7 ldq46 t pl55a 7 ldq54 t vccio vccio7 7 vccio7 7 v9 pl47b 7 ldq46 c pl55b 7 ldq54 c v11 pl48a 7 ldq46 t (lvds)* pl56a 7 ldq54 t (lvds)* v10 pl48b 7 ldq46 c (lvds)* pl56b 7 ldq54 c (lvds)* u4 pl49a 7 pclkt7_0/ldq46 t pl57a 7 pclkt7_0/ldq54 t gndio gndio7 - gndio7 - u3 pl49b 7 pclkc7_0/ldq46 c pl57b 7 pclkc7_0/ldq54 c u2 pl51a 6 pclkt6_0/ldq55 t (lvds)* p l59a 6 pclkt6_0/ldq63 t (lvds)* u1 pl51b 6 pclkc6_0/ldq55 c (lvds)* pl59b 6 pclkc6_0/ldq63 c (lvds)* v5 pl52a 6 vref2_6/ldq55 t pl60a 6 vref2_6/ldq63 t v6 pl52b 6 vref1_6/ldq55 c pl60b 6 vref1_6/ldq63 c v7 pl53a 6 ldq55 t (lvds)* pl61a 6 ldq63 t (lvds)* vccio vccio6 6 vccio6 6 v8 pl53b 6 ldq55 c (lvds)* pl61b 6 ldq63 c (lvds)* v4 pl54a 6 ldq55 t pl62a 6 ldq63 t v3 pl54b 6 ldq55 c pl62b 6 ldq63 c v2 pl55a 6 ldqs55 t (lvds)* pl63a 6 ldqs63 t (lvds)* gndio gndio6 - gndio6 - v1 pl55b 6 ldq55 c (lvds)* pl63b 6 ldq63 c (lvds)* w7 pl56a 6 ldq55 t pl64a 6 ldq63 t w5 pl56b 6 ldq55 c pl64b 6 ldq63 c vccio vccio6 6 vccio6 6 w2 pl57a 6 llm3_spllt_in_a/ld q55 t (lvds)* pl65a 6 llm4_spllt_in_a/ldq63 t (lvds)* w1 pl57b 6 llm3_spllc_in_a/ld q55 c (lvds)* pl65b 6 llm4_spl lc_in_a/ldq63 c (lvds)* y6 pl58a 6 llm3_spllt_f b_a/ldq55 t pl66a 6 llm4 _spllt_fb_a/ldq63 t w6 pl58b 6 llm3_spllc_fb_a/ldq55 c pl66b 6 llm4_spllc_fb_a/ldq63 c gndio gndio6 - gndio6 - y1 pl60a 6 ldq64 t (lvds)* pl68a 6 ldq72 t (lvds)* y2 pl60b 6 ldq64 c (lvds)* pl68b 6 ldq72 c (lvds)* y7 pl61a 6 ldq64 t pl69a 6 ldq72 t y5 pl61b 6 ldq64 c pl69b 6 ldq72 c vccio vccio6 6 vccio6 6 w10 pl62a 6 ldq64 t (lvds)* pl70a 6 ldq72 t (lvds)* y8 pl62b 6 ldq64 c (lvds)* pl70b 6 ldq72 c (lvds)* y4 pl63a 6 ldq64 t pl71a 6 ldq72 t y3 pl63b 6 ldq64 c pl71b 6 ldq72 c gndio gndio6 - gndio6 - aa1 pl64a 6 ldqs64 t (lvds)* pl72a 6 ldqs72 t (lvds)* aa2 pl64b 6 ldq64 c (lvds)* pl72b 6 ldq72 c (lvds)* aa8 pl65a 6 ldq64 t pl73a 6 ldq72 t vccio vccio6 6 vccio6 6 y9 pl65b 6 ldq64 c pl73b 6 ldq72 c aa6 pl66a 6 ldq64 t (lvds)* pl74a 6 ldq72 t (lvds)* aa7 pl66b 6 ldq64 c (lvds)* pl74b 6 ldq72 c (lvds)* lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-234 pinout information lattice semiconductor latticeecp2 /m family data sheet aa4 pl67a 6 ldq64 t pl75a 6 ldq72 t gndio gndio6 - gndio6 - aa3 pl67b 6 ldq64 c pl75b 6 ldq72 c aa9 pl69a 6 ldq73 t (lvds)* pl77a 6 ldq81 t (lvds)* aa10 pl69b 6 ldq73 c (lvds)* pl77b 6 ldq81 c (lvds)* aa5 pl70a 6 ldq73 t pl78a 6 ldq81 t ab6 pl70b 6 ldq73 c pl78b 6 ldq81 c ab1 pl71a 6 ldq73 t (lvds)* pl79a 6 ldq81 t (lvds)* vccio vccio6 6 vccio6 6 ab2 pl71b 6 ldq73 c (lvds)* pl79b 6 ldq81 c (lvds)* ac8 pl72a 6 ldq73 t pl80a 6 ldq81 t ab10 pl72b 6 ldq73 c pl80b 6 ldq81 c ac1 pl73a 6 ldqs73 t (lvds)* pl81a 6 ldqs81 t (lvds)* gndio gndio6 - gndio6 - ac2 pl73b 6 ldq73 c (lvds)* pl81b 6 ldq81 c (lvds)* ab7 pl74a 6 ldq73 t pl82a 6 ldq81 t ab5 pl74b 6 ldq73 c pl82b 6 ldq81 c vccio vccio6 6 vccio6 6 ac3 pl75a 6 ldq73 t (lvds)* pl83a 6 ldq81 t (lvds)* ac4 pl75b 6 ldq73 c (lvds)* pl83b 6 ldq81 c (lvds)* ac10 pl76a 6 ldq73 t pl84a 6 ldq81 t ac9 pl76b 6 ldq73 c pl84b 6 ldq81 c gndio gndio6 - gndio6 - ac7 nc - pl86a 6 ldq90 t (lvds)* ac5 nc - pl86b 6 ldq90 c (lvds)* ac6 nc - pl87a 6 ldq90 t ad5 nc - pl87b 6 ldq90 c - - - vccio6 6 ad4 nc - pl88a 6 ldq90 t (lvds)* ad3 nc - pl88b 6 ldq90 c (lvds)* ad10 nc - pl89a 6 ldq90 t ad8 nc - pl89b 6 ldq90 c - - - gndio6 - ad2 nc - pl90a 6 ldqs90 t (lvds)* ad1 nc - pl90b 6 ldq90 c (lvds)* ad9 nc - pl91a 6 ldq90 t - - - vccio6 6 ac11 nc - pl91b 6 ldq90 c ad6 nc - pl92a 6 ldq90 t (lvds)* ad7 nc - pl92b 6 ldq90 c (lvds)* ae1 nc - pl93a 6 ldq90 t - - - gndio6 - ae2 nc - pl93b 6 ldq90 c af2 pl78a 6 ldq82 t (lvds)* pl95a 6 ldq99 t (lvds)* af1 pl78b 6 ldq82 c (lvds)* pl95b 6 ldq99 c (lvds)* ae5 pl79a 6 ldq82 t pl96a 6 ldq99 t ae6 pl79b 6 ldq82 c pl96b 6 ldq99 c af4 pl80a 6 ldq82 t (lvds)* pl97a 6 ldq99 t (lvds)* vccio vccio6 6 vccio6 6 af3 pl80b 6 ldq82 c (lvds)* pl97b 6 ldq99 c (lvds)* af5 pl81a 6 ldq82 t pl98a 6 ldq99 t lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-235 pinout information lattice semiconductor latticeecp2 /m family data sheet af6 pl81b 6 ldq82 c pl98b 6 ldq99 c ag1 pl82a 6 llm0_gpllt_in_a**/ldqs82 t (lvds)* pl99a 6 llm0_gpllt_in_a**/ ldqs99 t (lvds)* gndio gndio6 - gndio6 - ag2 pl82b 6 llm0_gpllc_in_a**/ldq82 c (lvds)* pl99b 6 llm0_gpllc_in_a**/ldq99 c (lvds)* ae9 pl83a 6 llm0_gpllt_fb_a/ldq82 t pl100a 6 llm0_gpllt_fb_a/ldq99 t af7 pl83b 6 llm0_gpllc_fb_a/ldq82 c pl100b 6 llm0_gpllc_fb_a/ldq99 c vccio vccio6 6 vccio6 6 ah1 pl84a 6 llm0_gdllt_in_a**/ldq82 t (lvds)* pl101a 6 llm0_gdllt_in_a**/ldq99 t (lvds)* ah2 pl84b 6 llm0_gdllc_in_a**/ldq82 c (lvds)* pl101b 6 llm0_gdllc_in_a**/ ldq99 c (lvds)* ag5 pl85a 6 llm0_gdllt_fb_a/ldq82 t pl102a 6 llm0_gdllt_fb_a/ldq99 t ag4 pl85b 6 llm0_gdllc_fb_a/ldq82 c pl102b 6 llm0_gdllc_fb_a/ldq99 c gndio gndio6 - gndio6 - ag6 llm0_pllcap 6 llm0_pllcap 6 aj1 pl87a 6 t pl104a 6 t aj2 pl87b 6 c pl104b 6 c ak2 tck - tck - ak1 tdi - tdi - al1 tms - tms - af10 tdo - tdo - ak3 vccj - vccj - an2 llc_sq_vccrx3 14 llc_sq_vccrx3 14 am2 llc_sq_hdinp3 14 t llc_sq_hdinp3 14 t an1 llc_sq_vccib3 14 llc_sq_vccib3 14 am3 llc_sq_hdinn3 14 c llc_sq_hdinn3 14 c an3 llc_sq_vcctx3 14 llc_sq_vcctx3 14 ap2 llc_sq_hdoutp3 14 t llc_sq_hdoutp3 14 t am1 llc_sq_vccob3 14 llc_sq_vccob3 14 ap3 llc_sq_hdoutn3 14 c llc_sq_hdoutn3 14 c an4 llc_sq_vcctx2 14 llc_sq_vcctx2 14 ap4 llc_sq_hdoutn2 14 c llc_sq_hdoutn2 14 c al3 llc_sq_vccob2 14 llc_sq_vccob2 14 ap5 llc_sq_hdoutp2 14 t llc_sq_hdoutp2 14 t an5 llc_sq_vccrx2 14 llc_sq_vccrx2 14 am4 llc_sq_hdinn2 14 c llc_sq_hdinn2 14 c al4 llc_sq_vccib2 14 llc_sq_vccib2 14 am5 llc_sq_hdinp2 14 t llc_sq_hdinp2 14 t al6 llc_sq_vccp 14 llc_sq_vccp 14 al5 llc_sq_refclkp 14 t llc_sq_refclkp 14 t ak5 llc_sq_refclkn 14 c llc_sq_refclkn 14 c ak6 llc_sq_vccaux33 14 llc_sq_vccaux33 14 am6 llc_sq_hdinp1 14 t llc_sq_hdinp1 14 t al8 llc_sq_vccib1 14 llc_sq_vccib1 14 am7 llc_sq_hdinn1 14 c llc_sq_hdinn1 14 c an6 llc_sq_vccrx1 14 llc_sq_vccrx1 14 ap6 llc_sq_hdoutp1 14 t llc_sq_hdoutp1 14 t ak7 llc_sq_vccob1 14 llc_sq_vccob1 14 ap7 llc_sq_hdoutn1 14 c llc_sq_hdoutn1 14 c an7 llc_sq_vcctx1 14 llc_sq_vcctx1 14 ap8 llc_sq_hdoutn0 14 c llc_sq_hdoutn0 14 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-236 pinout information lattice semiconductor latticeecp2 /m family data sheet al9 llc_sq_vccob0 14 llc_sq_vccob0 14 ap9 llc_sq_hdoutp0 14 t llc_sq_hdoutp0 14 t an8 llc_sq_vcctx0 14 llc_sq_vcctx0 14 am8 llc_sq_hdinn0 14 c llc_sq_hdinn0 14 c an9 llc_sq_vccib0 14 llc_sq_vccib0 14 am9 llc_sq_hdinp0 14 t llc_sq_hdinp0 14 t al7 llc_sq_vccrx0 14 llc_sq_vccrx0 14 - - - vccio5 5 aj12 nc - pb32a 5 bdq33 t ah12 nc - pb32b 5 bdq33 c - - - gndio5 - - - - vccio5 5 al13 nc - pb36a 5 bdq33 t ak13 nc - pb36b 5 bdq33 c - - - gndio5 - ae14 nc - pb38a 5 bdq42 t ag13 nc - pb38b 5 bdq42 c an14 pb30a 5 bdq33 t pb39a 5 bdq42 t ap14 pb30b 5 bdq33 c pb39b 5 bdq42 c ah14 pb31a 5 bdq33 t pb40a 5 bdq42 t aj15 pb31b 5 bdq33 c pb40b 5 bdq42 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - al14 pb33a 5 bdqs33 t pb42a 5 bdqs42 t am14 pb33b 5 bdq33 c pb42b 5 bdq42 c af14 pb35a 5 bdq33 t pb44a 5 bdq42 t af13 pb35b 5 bdq33 c pb44b 5 bdq42 c vccio vccio5 5 vccio5 5 ae15 pb36a 5 bdq33 t pb45a 5 bdq42 t ag14 pb36b 5 bdq33 c pb45b 5 bdq42 c ah15 pb37a 5 bdq33 t pb46a 5 bdq42 t ak15 pb37b 5 bdq33 c pb46b 5 bdq42 c gndio gndio5 - gndio5 - al15 pb38a 5 bdq42 t pb47a 5 bdq51 t am15 pb38b 5 bdq42 c pb47b 5 bdq51 c ak16 pb39a 5 bdq42 t pb48a 5 bdq51 t aj16 pb39b 5 bdq42 c pb48b 5 bdq51 c an15 pb40a 5 bdq42 t pb49a 5 bdq51 t vccio vccio5 5 vccio5 5 ap15 pb40b 5 bdq42 c pb49b 5 bdq51 c ag15 pb42a 5 bdqs42 t pb51a 5 bdqs51 t gndio gndio5 - gndio5 - ae16 pb42b 5 bdq42 c pb51b 5 bdq51 c af15 pb44a 5 bdq42 t pb53a 5 bdq51 t vccio vccio5 5 vccio5 5 ad16 pb44b 5 bdq42 c pb53b 5 bdq51 c ak17 pb45a 5 bdq42 t pb54a 5 bdq51 t ah16 pb45b 5 bdq42 c pb54b 5 bdq51 c an16 pb46a 5 bdq42 t pb55a 5 bdq51 t gndio gndio5 - gndio5 - ap16 pb46b 5 bdq42 c pb55b 5 bdq51 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-237 pinout information lattice semiconductor latticeecp2 /m family data sheet al17 pb47a 5 bdq51 t pb56a 5 bdq60 t am17 pb47b 5 bdq51 c pb56b 5 bdq60 c an17 pb48a 5 bdq51 t pb57a 5 bdq60 t ap17 pb48b 5 bdq51 c pb57b 5 bdq60 c ad17 pb49a 5 bdq51 t pb58a 5 bdq60 t ae17 pb49b 5 bdq51 c pb58b 5 bdq60 c vccio vccio5 5 vccio5 5 al18 pb50a 5 bdq51 t pb59a 5 bdq60 t am18 pb50b 5 bdq51 c pb59b 5 bdq60 c gndio gndio5 - gndio5 - ap18 pb51a 5 bdqs51 t pb60a 5 bdqs60 t an18 pb51b 5 bdq51 c pb60b 5 bdq60 c ag17 pb52a 5 vref2_5/bdq51 t pb61a 5 vref2_5/bdq60 t aj17 pb52b 5 vref1_5/bdq51 c pb61b 5 vref1_5/bdq60 c af17 pb53a 5 pclkt5_ 0/bdq51 t pb62a 5 pclkt5_0/bdq60 t ah17 pb53b 5 pclkc5_0/bdq5 1 c pb62b 5 pclkc5_0/bdq60 c vccio vccio5 5 vccio5 5 gndio gndio5 - gndio5 - af18 pb58a 4 pclkt4_ 0/bdq60 t pb67a 4 pclkt4_0/bdq69 t vccio vccio4 4 vccio4 4 ad18 pb58b 4 pclkc4_0/bdq6 0 c pb67b 4 pclkc4_0/bdq69 c ap19 pb59a 4 vref2_4/bdq60 t pb68a 4 vref2_4/bdq69 t an19 pb59b 4 vref1_4/bdq60 c pb68b 4 vref1_4/bdq69 c ap20 pb60a 4 bdqs60 t pb69a 4 bdqs69 t gndio gndio4 - gndio4 - am20 pb60b 4 bdq60 c pb69b 4 bdq69 c an20 pb61a 4 bdq60 t pb70a 4 bdq69 t am21 pb61b 4 bdq60 c pb70b 4 bdq69 c ag18 pb62a 4 bdq60 t pb71a 4 bdq69 t vccio vccio4 4 vccio4 4 ae18 pb62b 4 bdq60 c pb71b 4 bdq69 c aj18 pb63a 4 bdq60 t pb72a 4 bdq69 t ah18 pb63b 4 bdq60 c pb72b 4 bdq69 c ak18 pb64a 4 bdq60 t pb73a 4 bdq69 t gndio gndio4 - gndio4 - ak19 pb64b 4 bdq60 c pb73b 4 bdq69 c ap21 pb65a 4 bdq69 t pb74a 4 bdq78 t an21 pb65b 4 bdq69 c pb74b 4 bdq78 c al20 pb66a 4 bdq69 t pb75a 4 bdq78 t ak20 pb66b 4 bdq69 c pb75b 4 bdq78 c an22 pb67a 4 bdq69 t pb76a 4 bdq78 t al21 pb67b 4 bdq69 c pb76b 4 bdq78 c vccio vccio4 4 vccio4 4 gndio gndio4 - gndio4 - ah19 pb69a 4 bdqs69 t pb78a 4 bdqs78 t aj20 pb69b 4 bdq69 c pb78b 4 bdq78 c ad20 pb71a 4 bdq69 t pb80a 4 bdq78 t af20 pb71b 4 bdq69 c pb80b 4 bdq78 c vccio vccio4 4 vccio4 4 aj19 pb72a 4 bdq69 t pb81a 4 bdq78 t ah20 pb72b 4 bdq69 c pb81b 4 bdq78 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-238 pinout information lattice semiconductor latticeecp2 /m family data sheet ae20 pb73a 4 bdq69 t pb82a 4 bdq78 t ag20 pb73b 4 bdq69 c pb82b 4 bdq78 c gndio gndio4 - gndio4 - ah22 nc - pb89a 4 bdq87 t - - - vccio4 4 ah21 nc - pb89b 4 bdq87 c ag22 nc - pb90a 4 bdq87 t ag21 nc - pb90b 4 bdq87 c - - - gndio4 - am22 pb74a 4 bdq78 t pb92a 4 bdq96 t al22 pb74b 4 bdq78 c pb92b 4 bdq96 c vccio vccio4 4 vccio4 4 ap23 pb77a 4 bdq78 t pb95a 4 bdq96 t an23 pb77b 4 bdq78 c pb95b 4 bdq96 c gndio gndio4 - gndio4 - am24 pb78a 4 bdqs78 t pb96a 4 bdqs96 t al24 pb78b 4 bdq78 c pb96b 4 bdq96 c ak22 pb79a 4 bdq78 t pb97a 4 bdq96 t aj22 pb79b 4 bdq78 c pb97b 4 bdq96 c al23 pb80a 4 bdq78 t pb98a 4 bdq96 t ak23 pb80b 4 bdq78 c pb98b 4 bdq96 c vccio vccio4 4 vccio4 4 aj23 pb81a 4 bdq78 t pb99a 4 bdq96 t ah23 pb81b 4 bdq78 c pb99b 4 bdq96 c gndio gndio4 - gndio4 - al28 lrc_sq_vccrx3 13 lrc_sq_vccrx3 13 am26 lrc_sq_hdinp3 13 t lrc_sq_hdinp3 13 t an26 lrc_sq_vccib3 13 lrc_sq_vccib3 13 am27 lrc_sq_hdinn3 13 c lrc_sq_hdinn3 13 c an27 lrc_sq_vcctx3 13 lrc_sq_vcctx3 13 ap26 lrc_sq_hdoutp3 13 t lrc_sq_hdoutp3 13 t al26 lrc_sq_vccob3 13 lrc_sq_vccob3 13 ap27 lrc_sq_hdoutn3 13 c lrc_sq_hdoutn3 13 c an28 lrc_sq_vcctx2 13 lrc_sq_vcctx2 13 ap28 lrc_sq_hdoutn2 13 c lrc_sq_hdoutn2 13 c ak28 lrc_sq_vccob2 13 lrc_sq_vccob2 13 ap29 lrc_sq_hdoutp2 13 t lrc_sq_hdoutp2 13 t an29 lrc_sq_vccrx2 13 lrc_sq_vccrx2 13 am28 lrc_sq_hdinn2 13 c lrc_sq_hdinn2 13 c al27 lrc_sq_vccib2 13 lrc_sq_vccib2 13 am29 lrc_sq_hdinp2 13 t lrc_sq_hdinp2 13 t al29 lrc_sq_vccp 13 lrc_sq_vccp 13 al30 lrc_sq_refclkp 13 t lrc_sq_refclkp 13 t ak30 lrc_sq_refclkn 13 c lrc_sq_refclkn 13 c ak29 lrc_sq_vccaux33 13 lrc_sq_vccaux33 13 am30 lrc_sq_hdinp1 13 t lrc_sq_hdinp1 13 t al31 lrc_sq_vccib1 13 lrc_sq_vccib1 13 am31 lrc_sq_hdinn1 13 c lrc_sq_hdinn1 13 c an30 lrc_sq_vccrx1 13 lrc_sq_vccrx1 13 ap30 lrc_sq_hdoutp1 13 t lrc_sq_hdoutp1 13 t al32 lrc_sq_vccob1 13 lrc_sq_vccob1 13 lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-239 pinout information lattice semiconductor latticeecp2 /m family data sheet ap31 lrc_sq_hdoutn1 13 c lrc_sq_hdoutn1 13 c an31 lrc_sq_vcctx1 13 lrc_sq_vcctx1 13 ap32 lrc_sq_hdoutn0 13 c lrc_sq_hdoutn0 13 c am34 lrc_sq_vccob0 13 lrc_sq_vccob0 13 ap33 lrc_sq_hdoutp0 13 t lrc_sq_hdoutp0 13 t an32 lrc_sq_vcctx0 13 lrc_sq_vcctx0 13 am32 lrc_sq_hdinn0 13 c lrc_sq_hdinn0 13 c an34 lrc_sq_vccib0 13 lrc_sq_vccib0 13 am33 lrc_sq_hdinp0 13 t lrc_sq_hdinp0 13 t an33 lrc_sq_vccrx0 13 lrc_sq_vccrx0 13 ah28 cfg2 8 cfg2 8 ad24 cfg1 8 cfg1 8 aj29 cfg0 8 cfg0 8 af25 programn 8 programn 8 aj28 cclk 8 cclk 8 ae25 initn 8 initn 8 ak31 done 8 done 8 gndio gndio8 - gndio8 - ae24 writen*** 8 writen*** 8 aj30 cs1n*** 8 cs1n*** 8 ad25 csn*** 8 csn*** 8 ag29 d0/spifastn*** 8 d0/spifastn*** 8 vccio vccio8 8 vccio8 8 ag28 d1*** 8 d1*** 8 ag30 d2*** 8 d2*** 8 ah29 d3*** 8 d3*** 8 gndio gndio8 - gndio8 - af26 d4*** 8 d4*** 8 ah30 d5*** 8 d5*** 8 ae26 d6*** 8 d6*** 8 aj31 d7*** 8 d7*** 8 vccio vccio8 8 vccio8 8 ag27 di/csspi0n*** 8 di/csspi0n*** 8 ak32 dout/cson/ csspi1n*** 8 dout/cson/ csspi1n*** 8 ak33 busy/sispi*** 8 busy/sispi*** 8 af27 rlm0_pllcap 3 rlm0_pllcap 3 af28 pr85b 3 rlm0_gdllc_fb_a c pr102b 3 rlm0_gdllc_fb_a/rdq99 c gndio gndio3 - gndio3 - ad26 pr85a 3 rlm0_gdllt_fb_a t pr102a 3 rlm0_gdllt_fb_a/rdq99 t aj32 pr84b 3 rlm0_gdllc_in_a** c (lvds)* pr101b 3 rlm0_gdllc_in_a**/ rdq99 c (lvds)* aj33 pr84a 3 rlm0_gdllt_i n_a** t (lvds)* pr101a 3 rlm0_gdllt_in_a**/ rdq99 t (lvds)* aj34 pr83b 3 rlm0_gpllc_in_a** c pr100b 3 rlm0_gpllc_in_a**/ rdq99 c vccio vccio3 3 vccio3 3 ak34 pr83a 3 rlm0_gpllt_in_a** t pr100a 3 rlm0_gpllt_in_a**/ rdq99 t ah33 pr82b 3 rlm0_gpllc_fb_a c (lvds)* p r99b 3 rlm0_gpllc_fb_a/rdq99 c (lvds)* ah34 pr82a 3 rlm0_gpllt_fb_a/rdqs82**** t (lvds)* pr99a 3 rlm0_gpllt_fb_a/ rdqs99 t (lvds)* gndio gndio3 - gndio3 - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-240 pinout information lattice semiconductor latticeecp2 /m family data sheet af29 pr81b 3 rdq82 c pr98b 3 rdq99 c af31 pr81a 3 rdq82 t pr98a 3 rdq99 t ag33 pr80b 3 rdq82 c (lvds)* pr97b 3 rdq99 c (lvds)* ag34 pr80a 3 rdq82 t (lvds)* pr97a 3 rdq99 t (lvds)* vccio vccio3 3 vccio3 3 af30 pr79b 3 rdq82 c pr96b 3 rdq99 c af32 pr79a 3 rdq82 t pr96a 3 rdq99 t ae29 pr78b 3 rdq82 c (lvds)* pr95b 3 rdq99 c (lvds)* ae30 pr78a 3 rdq82 t (lvds)* pr95a 3 rdq99 t (lvds)* af33 nc - pr93b 3 rdq90 c af34 nc - pr93a 3 rdq90 t - - - gndio3 - ac27 nc - pr92b 3 rdq90 c (lvds)* ac28 nc - pr92a 3 rdq90 t (lvds)* ad29 nc - pr91b 3 rdq90 c ad30 nc - pr91a 3 rdq90 t - - - vccio3 3 ae33 nc - pr90b 3 rdq90 c (lvds)* ae34 nc - pr90a 3 rdqs90 t (lvds)* ad32 nc - pr89b 3 rdq90 c - - - gndio3 - ad31 nc - pr89a 3 rdq90 t ab25 nc - pr88b 3 rdq90 c (lvds)* ac25 nc - pr88a 3 rdq90 t (lvds)* ab28 nc - pr87b 3 rdq90 c - - - vccio3 3 aa26 nc - pr87a 3 rdq90 t ad33 nc - pr86b 3 rdq90 c (lvds)* ad34 nc - pr86a 3 rdq90 t (lvds)* ac29 pr76b 3 rdq73 c pr84b 3 rdq81 c gndio gndio3 - gndio3 - aa27 pr76a 3 rdq73 t pr84a 3 rdq81 t ac32 pr75b 3 rdq73 c (lvds)* pr83b 3 rdq81 c (lvds)* ac31 pr75a 3 rdq73 t (lvds)* pr83a 3 rdq81 t (lvds)* aa25 pr74b 3 rdq73 c pr82b 3 rdq81 c vccio vccio3 3 vccio3 3 ac24 pr74a 3 rdq73 t pr82a 3 rdq81 t ac33 pr73b 3 rdq73 c (lvds)* pr81b 3 rdq81 c (lvds)* ac34 pr73a 3 rdqs73 t (lvds)* pr81a 3 rdqs81 t (lvds)* gndio gndio3 - gndio3 - ab24 pr72b 3 rdq73 c pr80b 3 rdq81 c y26 pr72a 3 rdq73 t pr80a 3 rdq81 t ab33 pr71b 3 rdq73 c (lvds)* pr79b 3 rdq81 c (lvds)* ab34 pr71a 3 rdq73 t (lvds)* pr79a 3 rdq81 t (lvds)* vccio vccio3 3 vccio3 3 y27 pr70b 3 rdq73 c pr78b 3 rdq81 c ab29 pr70a 3 rdq73 t pr78a 3 rdq81 t aa34 pr69b 3 rdq73 c (lvds)* pr77b 3 rdq81 c (lvds)* aa33 pr69a 3 rdq73 t (lvds)* pr77a 3 rdq81 t (lvds)* aa31 pr67b 3 rdq64 c pr75b 3 rdq72 c aa32 pr67a 3 rdq64 t pr75a 3 rdq72 t lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-241 pinout information lattice semiconductor latticeecp2 /m family data sheet gndio gndio3 - gndio3 - aa28 pr66b 3 rdq64 c (lvds)* pr74b 3 rdq72 c (lvds)* aa29 pr66a 3 rdq64 t (lvds)* pr74a 3 rdq72 t (lvds)* aa30 pr65b 3 rdq64 c pr73b 3 rdq72 c ab30 pr65a 3 rdq64 t pr73a 3 rdq72 t vccio vccio3 3 vccio3 3 y28 pr64b 3 rdq64 c (lvds)* pr72b 3 rdq72 c (lvds)* y29 pr64a 3 rdqs64 t (lvds) * pr72a 3 rdqs72 t (lvds)* aa24 pr63b 3 rdq64 c pr71b 3 rdq72 c gndio gndio3 - gndio3 - y25 pr63a 3 rdq64 t pr71a 3 rdq72 t y31 pr62b 3 rdq64 c (lvds)* pr70b 3 rdq72 c (lvds)* y30 pr62a 3 rdq64 t (lvds)* pr70a 3 rdq72 t (lvds)* y24 pr61b 3 rdq64 c pr69b 3 rdq72 c vccio vccio3 3 vccio3 3 w25 pr61a 3 rdq64 t pr69a 3 rdq72 t y33 pr60b 3 rdq64 c (lvds)* pr68b 3 rdq72 c (lvds)* y34 pr60a 3 rdq64 t (lvds)* pr68a 3 rdq72 t (lvds)* w28 pr58b 3 rlm3_spllc_fb_a/rdq55 c pr66b 3 rlm4_spllc_fb_a/rdq63 c gndio gndio3 - gndio3 - v26 pr58a 3 rlm3_spllt_fb_a/rdq55 t pr66a 3 rlm4_spllt_fb_a/rdq63 t v28 pr57b 3 rlm3_spllc_in_a/rdq55 c (lvds) * pr65b 3 rlm4_spllc_in_a/rdq63 c (lvds)* v27 pr57a 3 rlm3_spllt_in_a/rdq55 t (lvds) * pr65a 3 rlm4_spllt_in_a/rdq63 t (lvds)* v25 pr56b 3 rdq55 c pr64b 3 rdq63 c vccio vccio3 3 vccio3 3 w24 pr56a 3 rdq55 t pr64a 3 rdq63 t w33 pr55b 3 rdq55 c (lvds)* pr63b 3 rdq63 c (lvds)* w34 pr55a 3 rdqs55 t (lvds) * pr63a 3 rdqs63 t (lvds)* gndio gndio3 - gndio3 - v24 pr54b 3 rdq55 c pr62b 3 rdq63 c u26 pr54a 3 rdq55 t pr62a 3 rdq63 t w29 pr53b 3 rdq55 c (lvds)* pr61b 3 rdq63 c (lvds)* w30 pr53a 3 rdq55 t (lvds)* pr61a 3 rdq63 t (lvds)* vccio vccio3 3 vccio3 3 u27 pr52b 3 vref2_3/rdq55 c pr60b 3 vref2_3/rdq63 c v29 pr52a 3 vref1_3/rdq55 t pr60a 3 vref1_3/rdq63 t v31 pr51b 3 pclkc3_0/rdq55 c (lvds)* pr59b 3 pclkc3_0/rdq63 c (lvds)* v32 pr51a 3 pclkt3_0/rdq55 t (lvds)* pr59a 3 pclkt3_0/rdq63 t (lvds)* v33 pr49b 2 pclkc2_0/rdq46 c pr57b 2 pclkc2_0/rdq54 c v34 pr49a 2 pclkt2_0/rdq46 t pr57a 2 pclkt2_0/rdq54 t gndio gndio2 - gndio2 - u24 pr48b 2 rdq46 c (lvds)* pr56b 2 rdq54 c (lvds)* u25 pr48a 2 rdq46 t (lvds)* pr56a 2 rdq54 t (lvds)* v30 pr47b 2 rdq46 c pr55b 2 rdq54 c y32 pr47a 2 rdq46 t pr55a 2 rdq54 t vccio vccio2 2 vccio2 2 u28 pr46b 2 rdq46 c (lvds)* pr54b 2 rdq54 c (lvds)* u29 pr46a 2 rdqs46 t (lvds)* pr54a 2 rdqs54 t (lvds)* u33 pr45b 2 rdq46 c pr53b 2 rdq54 c gndio gndio2 - gndio2 - u34 pr45a 2 rdq46 t pr53a 2 rdq54 t lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-242 pinout information lattice semiconductor latticeecp2 /m family data sheet t30 pr44b 2 rdq46 c (lvds)* pr52b 2 rdq54 c (lvds)* u30 pr44a 2 rdq46 t (lvds)* pr52a 2 rdq54 t (lvds)* t29 pr43b 2 rum3_spllc_fb_a/rdq46 c pr51b 2 rum3_spllc_fb_a/rdq54 c vccio vccio2 2 vccio2 2 t28 pr43a 2 rum3_spllt_fb_a/rdq46 t pr51a 2 rum3_spllt_fb_a/rdq54 t u31 pr42b 2 rum3_spllc_in_a/rdq46 c (lvds)* pr50b 2 rum3_spllc_in_a/rdq54 c (lvds)* u32 pr42a 2 rum3_spllt_in_a/rdq46 t (lvds)* pr50a 2 rum3_spllt_in_a/rdq54 t (lvds)* t33 pr40b 2 rdq37 c pr48b 2 rdq45 c t34 pr40a 2 rdq37 t pr48a 2 rdq45 t gndio gndio2 - gndio2 - r27 pr39b 2 rdq37 c (lvds)* pr47b 2 rdq45 c (lvds)* r28 pr39a 2 rdq37 t (lvds)* pr47a 2 rdq45 t (lvds)* r29 pr38b 2 rdq37 c pr46b 2 rdq45 c r30 pr38a 2 rdq37 t pr46a 2 rdq45 t vccio vccio2 2 vccio2 2 r33 pr37b 2 rdq37 c (lvds)* pr45b 2 rdq45 c (lvds)* r34 pr37a 2 rdqs37 t (lvds)* pr45a 2 rdqs45 t (lvds)* r32 pr36b 2 rdq37 c pr44b 2 rdq45 c gndio gndio2 - gndio2 - r31 pr36a 2 rdq37 t pr44a 2 rdq45 t p34 pr35b 2 rdq37 c (lvds)* pr43b 2 rdq45 c (lvds)* p33 pr35a 2 rdq37 t (lvds)* pr43a 2 rdq45 t (lvds)* r26 pr34b 2 rdq37 c pr42b 2 rdq45 c vccio vccio2 2 vccio2 2 t25 pr34a 2 rdq37 t pr42a 2 rdq45 t p28 pr33b 2 rdq37 c (lvds)* pr41b 2 rdq45 c (lvds)* p27 pr33a 2 rdq37 t (lvds)* pr41a 2 rdq45 t (lvds)* p30 nc - pr40b 2 c - - - gndio2 - p29 nc - pr40a 2 t p31 nc - pr39b 2 c (lvds)* p32 nc - pr39a 2 t (lvds)* r25 nc - pr38b 2 c - - - vccio2 2 t24 nc - pr38a 2 t n34 nc - pr37b 2 c (lvds)* n33 nc - pr37a 2 t (lvds)* gndio gndio2 - gndio2 - m34 pr31b 2 rdq28 c pr35b 2 rdq32 c m33 pr31a 2 rdq28 t pr35a 2 rdq32 t - - - gndio2 - r24 pr30b 2 rdq28 c (lvds)* pr34b 2 rdq32 c (lvds)* p24 pr30a 2 rdq28 t (lvds)* pr34a 2 rdq32 t (lvds)* n30 pr29b 2 rdq28 c pr33b 2 rdq32 c m29 pr29a 2 rdq28 t pr33a 2 rdq32 t vccio vccio2 2 vccio2 2 n28 pr28b 2 rdq28 c (lvds)* pr32b 2 rdq32 c (lvds)* n29 pr28a 2 rdqs28 t (lvds)* pr32a 2 rdqs32 t (lvds)* n24 pr27b 2 rdq28 c pr31b 2 rdq32 c gndio gndio2 - gndio2 - n25 pr27a 2 rdq28 t pr31a 2 rdq32 t lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-243 pinout information lattice semiconductor latticeecp2 /m family data sheet m28 pr26b 2 rdq28 c (lvds)* pr30b 2 rdq32 c (lvds)* m27 pr26a 2 rdq28 t (lvds)* pr30a 2 rdq32 t (lvds)* l27 pr25b 2 rdq28 c pr29b 2 rdq32 c vccio vccio2 2 vccio2 2 m26 pr25a 2 rdq28 t pr29a 2 rdq32 t m32 pr24b 2 rdq28 c (lvds)* pr28b 2 rdq32 c (lvds)* m31 pr24a 2 rdq28 t (lvds)* pr28a 2 rdq32 t (lvds)* gndio gndio2 - gndio2 - - - - vccio2 2 l34 pr22b 2 c pr22b 2 rdq23 c l33 pr22a 2 t pr22a 2 rdq23 t l32 pr21b 2 c (lvds)* pr21b 2 rdq23 c (lvds)* l31 pr21a 2 t (lvds)* pr21a 2 rdq23 t (lvds)* vccio vccio2 2 vccio2 2 l28 pr20b 2 c pr20b 2 rdq23 c l29 pr20a 2 t pr20a 2 rdq23 t m30 pr19b 2 c (lvds)* pr19b 2 rdq23 c (lvds)* l30 pr19a 2 t (lvds)* pr19a 2 rdq23 t (lvds)* k34 pr18b 2 rdq15 c pr18b 2 rdq15 c k33 pr18a 2 rdq15 t pr18a 2 rdq15 t gndio gndio2 - gndio2 - k30 pr17b 2 rdq15 c (lvds)* pr17b 2 rdq15 c (lvds)* k29 pr17a 2 rdq15 t (lvds)* pr17a 2 rdq15 t (lvds)* j34 pr16b 2 rdq15 c pr16b 2 rdq15 c j33 pr16a 2 rdq15 t pr16a 2 rdq15 t vccio vccio2 2 vccio2 2 j32 pr15b 2 rdq15 c (lvds)* pr15b 2 rdq15 c (lvds)* j31 pr15a 2 rdqs15 t (lvds) * pr15a 2 rdqs15 t (lvds)* h33 pr14b 2 rdq15 c pr14b 2 rdq15 c gndio gndio2 - gndio2 - h34 pr14a 2 rdq15 t pr14a 2 rdq15 t j30 pr13b 2 rdq15 c (lvds)* pr13b 2 rdq15 c (lvds)* j29 pr13a 2 rdq15 t (lvds)* pr13a 2 rdq15 t (lvds)* vccio vccio2 2 vccio2 2 j27 pr11b 2 rum0_spllc_in_a/rdq15 c (lvds) * pr11b 2 rum0_spllc_in_ a/rdq15 c (lvds)* j28 pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* pr11a 2 rum0_spllt_in_a/rdq15 t (lvds)* h31 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 - gndio2 - h32 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 vccio2 2 h30 xres 1 xres 1 b33 urc_sq_vccrx0 12 urc_sq_vccrx0 12 c33 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b34 urc_sq_vccib0 12 urc_sq_vccib0 12 c32 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c b32 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a33 urc_sq_hdoutp0 12 t urc_sq_hdoutp0 12 t c34 urc_sq_vccob0 12 urc_sq_vccob0 12 a32 urc_sq_hdoutn0 12 c urc_sq_hdoutn0 12 c b31 urc_sq_vcctx1 12 urc_sq_vcctx1 12 a31 urc_sq_hdoutn1 12 c urc_sq_hdoutn1 12 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-244 pinout information lattice semiconductor latticeecp2 /m family data sheet d32 urc_sq_vccob1 12 urc_sq_vccob1 12 a30 urc_sq_hdoutp1 12 t urc_sq_hdoutp1 12 t b30 urc_sq_vccrx1 12 urc_sq_vccrx1 12 c31 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c d31 urc_sq_vccib1 12 urc_sq_vccib1 12 c30 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t e29 urc_sq_vccaux33 12 urc_sq_vccaux33 12 e30 urc_sq_refclkn 12 c urc_sq_refclkn 12 c d30 urc_sq_refclkp 12 t urc_sq_refclkp 12 t d29 urc_sq_vccp 12 urc_sq_vccp 12 c29 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t d27 urc_sq_vccib2 12 urc_sq_vccib2 12 c28 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c b29 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a29 urc_sq_hdoutp2 12 t urc_sq_hdoutp2 12 t e28 urc_sq_vccob2 12 urc_sq_vccob2 12 a28 urc_sq_hdoutn2 12 c urc_sq_hdoutn2 12 c b28 urc_sq_vcctx2 12 urc_sq_vcctx2 12 a27 urc_sq_hdoutn3 12 c urc_sq_hdoutn3 12 c d26 urc_sq_vccob3 12 urc_sq_vccob3 12 a26 urc_sq_hdoutp3 12 t urc_sq_hdoutp3 12 t b27 urc_sq_vcctx3 12 urc_sq_vcctx3 12 c27 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b26 urc_sq_vccib3 12 urc_sq_vccib3 12 c26 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t d28 urc_sq_vccrx3 12 urc_sq_vccrx3 12 e23 pt82b 1 c pt100b 1 c gndio gndio1 - gndio1 - f23 pt82a 1 t pt100a 1 t f24 nc - pt99b 1 c g23 nc - pt99a 1 t d23 pt80b 1 c pt98b 1 c vccio vccio1 1 vccio1 1 d22 pt80a 1 t pt98a 1 t - - - gndio1 - - - - vccio1 1 c21 pt79b 1 c pt88b 1 c d21 pt79a 1 t pt88a 1 t gndio gndio1 - gndio1 - b21 pt77b 1 c pt86b 1 c a21 pt77a 1 t pt86a 1 t f22 pt76b 1 c pt85b 1 c e22 pt76a 1 t pt85a 1 t vccio vccio1 1 vccio1 1 gndio gndio1 - - - j22 nc - pt84b 1 c g22 nc - pt84a 1 t - - - gndio1 - h22 pt72b 1 c pt81b 1 c k22 pt72a 1 t pt81a 1 t g21 pt71b 1 c pt80b 1 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-245 pinout information lattice semiconductor latticeecp2 /m family data sheet vccio vccio1 1 vccio1 1 j21 pt71a 1 t pt80a 1 t h21 nc - pt79b 1 c k21 nc - pt79a 1 t d20 pt69b 1 c pt78b 1 c f20 pt69a 1 t pt78a 1 t c20 pt68b 1 c pt77b 1 c gndio gndio1 - gndio1 - e20 pt68a 1 t pt77a 1 t g20 pt67b 1 c pt76b 1 c vccio vccio1 1 vccio1 1 j20 pt67a 1 t pt76a 1 t a20 pt66b 1 c pt75b 1 c b20 pt66a 1 t pt75a 1 t gndio gndio1 - gndio1 - a19 pt63b 1 c pt72b 1 c b19 pt63a 1 t pt72a 1 t k20 pt62b 1 c pt71b 1 c h20 pt62a 1 t pt71a 1 t vccio vccio1 1 vccio1 1 l19 nc - pt70b 1 c l20 nc - pt70a 1 t e19 pt60b 1 c pt69b 1 c c18 pt60a 1 t pt69a 1 t gndio gndio1 - gndio1 - f19 pt59b 1 c pt68b 1 c d18 pt59a 1 t pt68a 1 t l18 nc - pt67b 1 c k19 nc - pt67a 1 t vccio vccio1 1 vccio1 1 a18 pt57b 1 vref2_1 c pt66b 1 vref2_1 c b18 pt57a 1 vref1_1 t pt66a 1 vref1_1 t g18 pt56b 1 pclkc1_0 c pt65b 1 pclkc1_0 c e18 pt56a 1 pclkt1_0 t pt65a 1 pclkt1_0 t f18 pt55b 0 pclkc0_0 c pt64b 0 pclkc0_0 c gndio gndio0 - gndio0 - g19 pt55a 0 pclkt0_0 t pt64a 0 pclkt0_0 t h18 pt54b 0 vref2_0 c pt63b 0 vref2_0 c k18 pt54a 0 vref1_0 t pt63a 0 vref1_0 t vccio vccio0 0 vccio0 0 j18 pt53b 0 c pt60b 0 c l17 pt53a 0 t pt60a 0 t g17 pt52b 0 c pt59b 0 c - - - gndio0 - j17 pt52a 0 t pt59a 0 t h17 pt51b 0 c pt58b 0 c - - - vccio0 0 k17 pt51a 0 t pt58a 0 t b17 pt50b 0 c pt57b 0 c gndio gndio0 - - - a17 pt50a 0 t pt57a 0 t lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-246 pinout information lattice semiconductor latticeecp2 /m family data sheet d17 pt49b 0 c pt56b 0 c vccio vccio0 0 - - f17 pt49a 0 t pt56a 0 t b16 pt48b 0 c pt55b 0 c a16 pt48a 0 t pt55a 0 t - - - gndio0 - - - - vccio0 0 e17 pt47b 0 c pt52b 0 c c17 pt47a 0 t pt52a 0 t k16 pt46b 0 c pt51b 0 c j15 pt46a 0 t pt51a 0 t gndio gndio0 - gndio0 - g16 pt45b 0 c pt50b 0 c h15 pt45a 0 t pt50a 0 t a15 pt44b 0 c pt49b 0 c b15 pt44a 0 t pt49a 0 t vccio vccio0 0 vccio0 0 l16 pt43b 0 c pt48b 0 c k15 pt43a 0 t pt48a 0 t f16 pt42b 0 c pt47b 0 c e16 pt42a 0 t pt47a 0 t e15 pt41b 0 c pt46b 0 c gndio gndio0 - gndio0 - g15 pt41a 0 t pt46a 0 t j14 nc - pt45b 0 c l15 nc - pt45a 0 t h14 nc - pt44b 0 c vccio vccio0 0 vccio0 0 k14 nc - pt44a 0 t f15 pt38b 0 c pt42b 0 c g14 pt38a 0 t pt42a 0 t c15 pt37b 0 c pt41b 0 c gndio gndio0 - gndio0 - d14 pt37a 0 t pt41a 0 t g13 pt36b 0 c pt40b 0 c - - - vccio0 0 j13 pt36a 0 t pt40a 0 t b14 pt35b 0 c pt39b 0 c vccio vccio0 0 - - a14 pt35a 0 t pt39a 0 t f13 pt34b 0 c pt38b 0 c h13 pt34a 0 t pt38a 0 t d13 pt33b 0 c pt37b 0 c c14 pt33a 0 t pt37a 0 t gndio gndio0 - gndio0 - e13 pt32b 0 c pt32b 0 c d12 pt32a 0 t pt32a 0 t g12 pt31b 0 c pt31b 0 c e12 pt31a 0 t pt31a 0 t vccio vccio0 0 vccio0 0 f12 nc - pt30b 0 c lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-247 pinout information lattice semiconductor latticeecp2 /m family data sheet d11 nc - pt30a 0 t f11 nc - pt29b 0 c e11 nc - pt29a 0 t d7 ulc_sq_vccrx0 11 ulc_sq_vccrx0 11 c9 ulc_sq_hdinp0 11 t ulc_sq_hdinp0 11 t b9 ulc_sq_vccib0 11 ulc_sq_vccib0 11 c8 ulc_sq_hdinn0 11 c ulc_sq_hdinn0 11 c b8 ulc_sq_vcctx0 11 ulc_sq_vcctx0 11 a9 ulc_sq_hdoutp0 11 t ulc_sq_hdoutp0 11 t d9 ulc_sq_vccob0 11 ulc_sq_vccob0 11 a8 ulc_sq_hdoutn0 11 c ulc_sq_hdoutn0 11 c b7 ulc_sq_vcctx1 11 ulc_sq_vcctx1 11 a7 ulc_sq_hdoutn1 11 c ulc_sq_hdoutn1 11 c e7 ulc_sq_vccob1 11 ulc_sq_vccob1 11 a6 ulc_sq_hdoutp1 11 t ulc_sq_hdoutp1 11 t b6 ulc_sq_vccrx1 11 ulc_sq_vccrx1 11 c7 ulc_sq_hdinn1 11 c ulc_sq_hdinn1 11 c d8 ulc_sq_vccib1 11 ulc_sq_vccib1 11 c6 ulc_sq_hdinp1 11 t ulc_sq_hdinp1 11 t e6 ulc_sq_vccaux33 11 ulc_sq_vccaux33 11 e5 ulc_sq_refclkn 11 c ulc_sq_refclkn 11 c d5 ulc_sq_refclkp 11 t ulc_sq_refclkp 11 t d6 ulc_sq_vccp 11 ulc_sq_vccp 11 c5 ulc_sq_hdinp2 11 t ulc_sq_hdinp2 11 t d4 ulc_sq_vccib2 11 ulc_sq_vccib2 11 c4 ulc_sq_hdinn2 11 c ulc_sq_hdinn2 11 c b5 ulc_sq_vccrx2 11 ulc_sq_vccrx2 11 a5 ulc_sq_hdoutp2 11 t ulc_sq_hdoutp2 11 t d3 ulc_sq_vccob2 11 ulc_sq_vccob2 11 a4 ulc_sq_hdoutn2 11 c ulc_sq_hdoutn2 11 c b4 ulc_sq_vcctx2 11 ulc_sq_vcctx2 11 a3 ulc_sq_hdoutn3 11 c ulc_sq_hdoutn3 11 c c1 ulc_sq_vccob3 11 ulc_sq_vccob3 11 a2 ulc_sq_hdoutp3 11 t ulc_sq_hdoutp3 11 t b3 ulc_sq_vcctx3 11 ulc_sq_vcctx3 11 c3 ulc_sq_hdinn3 11 c ulc_sq_hdinn3 11 c b1 ulc_sq_vccib3 11 ulc_sq_vccib3 11 c2 ulc_sq_hdinp3 11 t ulc_sq_hdinp3 11 t b2 ulc_sq_vccrx3 11 ulc_sq_vccrx3 11 aa13 vcc - vcc - aa14 vcc - vcc - aa15 vcc - vcc - aa16 vcc - vcc - aa17 vcc - vcc - aa18 vcc - vcc - aa19 vcc - vcc - aa20 vcc - vcc - aa21 vcc - vcc - aa22 vcc - vcc - ab14 vcc - vcc - ab15 vcc - vcc - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-248 pinout information lattice semiconductor latticeecp2 /m family data sheet ab20 vcc - vcc - ab21 vcc - vcc - n14 vcc - vcc - n15 vcc - vcc - n20 vcc - vcc - n21 vcc - vcc - p13 vcc - vcc - p14 vcc - vcc - p15 vcc - vcc - p16 vcc - vcc - p17 vcc - vcc - p18 vcc - vcc - p19 vcc - vcc - p20 vcc - vcc - p21 vcc - vcc - p22 vcc - vcc - r13 vcc - vcc - r14 vcc - vcc - r21 vcc - vcc - r22 vcc - vcc - t14 vcc - vcc - t21 vcc - vcc - u14 vcc - vcc - u21 vcc - vcc - v14 vcc - vcc - v21 vcc - vcc - w14 vcc - vcc - w21 vcc - vcc - y13 vcc - vcc - y14 vcc - vcc - y21 vcc - vcc - y22 vcc - vcc - c12 vccio0 0 vccio0 0 c16 vccio0 0 vccio0 0 e14 vccio0 0 vccio0 0 h12 vccio0 0 vccio0 0 h16 vccio0 0 vccio0 0 m14 vccio0 0 vccio0 0 m15 vccio0 0 vccio0 0 c19 vccio1 1 vccio1 1 c23 vccio1 1 vccio1 1 e21 vccio1 1 vccio1 1 h19 vccio1 1 vccio1 1 h23 vccio1 1 vccio1 1 m20 vccio1 1 vccio1 1 m21 vccio1 1 vccio1 1 g32 vccio2 2 vccio2 2 k28 vccio2 2 vccio2 2 k32 vccio2 2 vccio2 2 n27 vccio2 2 vccio2 2 n32 vccio2 2 vccio2 2 lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-249 pinout information lattice semiconductor latticeecp2 /m family data sheet p23 vccio2 2 vccio2 2 r23 vccio2 2 vccio2 2 t27 vccio2 2 vccio2 2 t32 vccio2 2 vccio2 2 aa23 vccio3 3 vccio3 3 ab27 vccio3 3 vccio3 3 ab32 vccio3 3 vccio3 3 ae28 vccio3 3 vccio3 3 ae32 vccio3 3 vccio3 3 ah32 vccio3 3 vccio3 3 w27 vccio3 3 vccio3 3 w32 vccio3 3 vccio3 3 y23 vccio3 3 vccio3 3 ac20 vccio4 4 vccio4 4 ac21 vccio4 4 vccio4 4 ag19 vccio4 4 vccio4 4 ag23 vccio4 4 vccio4 4 ak21 vccio4 4 vccio4 4 am19 vccio4 4 vccio4 4 am23 vccio4 4 vccio4 4 ac14 vccio5 5 vccio5 5 ac15 vccio5 5 vccio5 5 ag12 vccio5 5 vccio5 5 ag16 vccio5 5 vccio5 5 ak14 vccio5 5 vccio5 5 am12 vccio5 5 vccio5 5 am16 vccio5 5 vccio5 5 aa12 vccio6 6 vccio6 6 ab3 vccio6 6 vccio6 6 ab8 vccio6 6 vccio6 6 ae3 vccio6 6 vccio6 6 ae7 vccio6 6 vccio6 6 ah3 vccio6 6 vccio6 6 w3 vccio6 6 vccio6 6 w8 vccio6 6 vccio6 6 y12 vccio6 6 vccio6 6 g3 vccio7 7 vccio7 7 k3 vccio7 7 vccio7 7 k7 vccio7 7 vccio7 7 n3 vccio7 7 vccio7 7 n8 vccio7 7 vccio7 7 p12 vccio7 7 vccio7 7 r12 vccio7 7 vccio7 7 t3 vccio7 7 vccio7 7 t8 vccio7 7 vccio7 7 ad28 vccio8 8 vccio8 8 ag32 vccio8 8 vccio8 8 ab12 vccaux - vccaux - ab13 vccaux - vccaux - ab22 vccaux - vccaux - ab23 vccaux - vccaux - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-250 pinout information lattice semiconductor latticeecp2 /m family data sheet ac13 vccaux - vccaux - ac22 vccaux - vccaux - m13 vccaux - vccaux - m22 vccaux - vccaux - n12 vccaux - vccaux - n13 vccaux - vccaux - n22 vccaux - vccaux - n23 vccaux - vccaux - a1 gnd - gnd - a10 gnd - gnd - a13 gnd - gnd - a22 gnd - gnd - a25 gnd - gnd - a34 gnd - gnd - ab16 gnd - gnd - ab17 gnd - gnd - ab18 gnd - gnd - ab19 gnd - gnd - ab26 gnd - gnd - ab31 gnd - gnd - ab4 gnd - gnd - ab9 gnd - gnd - ac16 gnd - gnd - ac17 gnd - gnd - ac18 gnd - gnd - ac19 gnd - gnd - ad27 gnd - gnd - ae27 gnd - gnd - ae31 gnd - gnd - ae4 gnd - gnd - ae8 gnd - gnd - af12 gnd - gnd - af16 gnd - gnd - af19 gnd - gnd - af23 gnd - gnd - ag31 gnd - gnd - ah31 gnd - gnd - ah4 gnd - gnd - aj14 gnd - gnd - aj21 gnd - gnd - ak27 gnd - gnd - ak8 gnd - gnd - al10 gnd - gnd - al16 gnd - gnd - al19 gnd - gnd - al2 gnd - gnd - al25 gnd - gnd - al33 gnd - gnd - ap1 gnd - gnd - ap10 gnd - gnd - ap13 gnd - gnd - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-251 pinout information lattice semiconductor latticeecp2 /m family data sheet ap22 gnd - gnd - ap25 gnd - gnd - ap34 gnd - gnd - d10 gnd - gnd - d16 gnd - gnd - d19 gnd - gnd - d2 gnd - gnd - d25 gnd - gnd - d33 gnd - gnd - e27 gnd - gnd - e8 gnd - gnd - f14 gnd - gnd - f21 gnd - gnd - g31 gnd - gnd - g4 gnd - gnd - j12 gnd - gnd - j16 gnd - gnd - j19 gnd - gnd - j23 gnd - gnd - k27 gnd - gnd - k31 gnd - gnd - k4 gnd - gnd - k8 gnd - gnd - m16 gnd - gnd - m17 gnd - gnd - m18 gnd - gnd - m19 gnd - gnd - n16 gnd - gnd - n17 gnd - gnd - n18 gnd - gnd - n19 gnd - gnd - n26 gnd - gnd - n31 gnd - gnd - n4 gnd - gnd - n9 gnd - gnd - r16 gnd - gnd - r17 gnd - gnd - r18 gnd - gnd - r19 gnd - gnd - t12 gnd - gnd - t13 gnd - gnd - t15 gnd - gnd - t16 gnd - gnd - t17 gnd - gnd - t18 gnd - gnd - t19 gnd - gnd - t20 gnd - gnd - t22 gnd - gnd - t23 gnd - gnd - t26 gnd - gnd - t31 gnd - gnd - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-252 pinout information lattice semiconductor latticeecp2 /m family data sheet t4 gnd - gnd - t9 gnd - gnd - u12 gnd - gnd - u13 gnd - gnd - u15 gnd - gnd - u16 gnd - gnd - u17 gnd - gnd - u18 gnd - gnd - u19 gnd - gnd - u20 gnd - gnd - u22 gnd - gnd - u23 gnd - gnd - v12 gnd - gnd - v13 gnd - gnd - v15 gnd - gnd - v16 gnd - gnd - v17 gnd - gnd - v18 gnd - gnd - v19 gnd - gnd - v20 gnd - gnd - v22 gnd - gnd - v23 gnd - gnd - w12 gnd - gnd - w13 gnd - gnd - w15 gnd - gnd - w16 gnd - gnd - w17 gnd - gnd - w18 gnd - gnd - w19 gnd - gnd - w20 gnd - gnd - w22 gnd - gnd - w23 gnd - gnd - w26 gnd - gnd - w31 gnd - gnd - w4 gnd - gnd - w9 gnd - gnd - y16 gnd - gnd - y17 gnd - gnd - y18 gnd - gnd - y19 gnd - gnd - a11 nc - nc - a12 nc - nc - a23 nc - nc - a24 nc - nc - aa11 nc - nc - ab11 nc - nc - ac26 nc - nc - ac30 nc - nc - ad11 nc - nc - ad12 nc - nc - ad13 nc - nc - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-253 pinout information lattice semiconductor latticeecp2 /m family data sheet ad14 nc - nc - ad15 nc - nc - ad19 nc - nc - ad21 nc - nc - ad22 nc - nc - ad23 nc - nc - ae10 nc - nc - ae11 nc - nc - ae12 nc - nc - ae13 nc - nc - ae19 nc - nc - ae21 nc - nc - ae22 nc - nc - ae23 nc - nc - af11 nc - nc - af21 nc - nc - af22 nc - nc - af24 nc - nc - af8 nc - nc - af9 nc - nc - ag10 nc - nc - ag11 nc - nc - ag24 nc - nc - ag25 nc - nc - ag26 nc - nc - ag3 nc - nc - ag7 nc - nc - ag8 nc - nc - ag9 nc - nc - ah10 nc - nc - ah11 nc - nc - ah13 nc - nc - ah24 nc - nc - ah25 nc - nc - ah26 nc - nc - ah27 nc - nc - ah5 nc - nc - ah6 nc - nc - ah7 nc - nc - ah8 nc - nc - ah9 nc - nc - aj10 nc - nc - aj11 nc - nc - aj13 nc - nc - aj24 nc - nc - aj25 nc - nc - aj26 nc - nc - aj27 nc - nc - aj3 nc - nc - aj4 nc - nc - aj5 nc - nc - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-254 pinout information lattice semiconductor latticeecp2 /m family data sheet aj6 nc - nc - aj7 nc - nc - aj8 nc - nc - aj9 nc - nc - ak10 nc - nc - ak11 nc - nc - ak12 nc - nc - ak24 nc - nc - ak25 nc - nc - ak26 nc - nc - ak4 nc - nc - ak9 nc - nc - al11 nc - nc - al12 nc - nc - al34 nc - nc - am10 nc - nc - am11 nc - nc - am13 nc - nc - am25 nc - nc - an10 nc - nc - an11 nc - nc - an12 nc - nc - an13 nc - nc - an24 nc - nc - an25 nc - nc - ap11 nc - nc - ap12 nc - nc - ap24 nc - nc - b10 nc - nc - b11 nc - nc - b12 nc - nc - b13 nc - nc - b22 nc - nc - b23 nc - nc - b24 nc - nc - b25 nc - nc - c10 nc - nc - c11 nc - nc - c13 nc - nc - c22 nc - nc - c24 nc - nc - c25 nc - nc - d1 nc - nc - d15 nc - nc - d24 nc - nc - d34 nc - nc - e10 nc - nc - e24 nc - nc - e25 nc - nc - e26 nc - nc - e3 nc - nc - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-255 pinout information lattice semiconductor latticeecp2 /m family data sheet e31 nc - nc - e32 nc - nc - e33 nc - nc - e34 nc - nc - e4 nc - nc - e9 nc - nc - f10 nc - nc - f25 nc - nc - f26 nc - nc - f27 nc - nc - f28 nc - nc - f29 nc - nc - f30 nc - nc - f31 nc - nc - f32 nc - nc - f33 nc - nc - f34 nc - nc - f5 nc - nc - f6 nc - nc - f7 nc - nc - f8 nc - nc - f9 nc - nc - g10 nc - nc - g11 nc - nc - g24 nc - nc - g25 nc - nc - g26 nc - nc - g27 nc - nc - g28 nc - nc - g29 nc - nc - g30 nc - nc - g33 nc - nc - g34 nc - nc - g7 nc - nc - g8 nc - nc - g9 nc - nc - h10 nc - nc - h11 nc - nc - h24 nc - nc - h25 nc - nc - h26 nc - nc - h27 nc - nc - h28 nc - nc - h29 nc - nc - h8 nc - nc - h9 nc - nc - j10 nc - nc - j11 nc - nc - j24 nc - nc - j25 nc - nc - j26 nc - nc - lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential 4-256 pinout information lattice semiconductor latticeecp2 /m family data sheet j9 nc - nc - k10 nc - nc - k11 nc - nc - k12 nc - nc - k13 nc - nc - k23 nc - nc - k24 nc - nc - k25 nc - nc - k26 nc - nc - l11 nc - nc - l12 nc - nc - l13 nc - nc - l14 nc - nc - l21 nc - nc - l22 nc - nc - l23 nc - nc - l24 nc - nc - l25 nc - nc - l26 nc - nc - m11 nc - nc - m24 nc - nc - m25 nc - nc - m6 nc - nc - m8 nc - nc - n10 nc - nc - n11 nc - nc - p10 nc - nc - p25 nc - nc - p26 nc - nc - r9 nc - nc - t11 nc - nc - u11 nc - nc - w11 nc - nc - y10 nc - nc - y11 nc - nc - r15 vccpll - vccpll - r20 vccpll - vccpll - y15 vccpll - vccpll - y20 vccpll - vccpll - * supports true lvds. other differential signal s must be emulated with external resistors. ** these dedicated input pins can be used for gp lls or gdlls within the respective quadrant. *** for density migration, board design must take into account t hat these sysconfig pins are du al function for the lower densit y devices (ecp2m20 and ecp2m35) and are dedicated pins for the higher density devices (ecp2m50, ecp2m70, and ecp2m100). ****due to packaging bond out option, this dqs does not have all the necessary dq pins bonded out for a full 8-bit data width. note: vccio and gnd pads are used to determine the average dc curr ent drawn by i/os between gnd/vccio connections, or between t he last gnd/vccio in an i/o bank and the end of an i/o bank. the subs trate pads listed in the pin table do not necessarily have a one to one connection with a package ball or pin. lfe2m70e/se and lfe2m100e/se logi c signal connections: 1152 fpbga lfe2m70e/se lfe2m100e/se ball number ball/pad function bank dual function differential ball/pad function bank dual function differential www.latticesemi.com 5-1 ds1006 order info_01.6 november 2009 data sheet ds1006 ? 2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. latticeecp2 part number description lfe2 ? xx xe ? x xxxxxx x grade c = commercial i = industrial logic capacity 6 = 6k luts 12 = 12k luts 20 = 20k luts 35 = 35k luts 50 = 50k luts 70 = 70k luts supply voltage e = 1.2v encryption s = security series (encryption feature) blank = standard series (no encryption) speed 5 = slowest 6 7 = fastest package t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga tn144 = 144-pin lead-free tqfp qn208 = 208-pin lead-free pqfp fn256 = 256-ball lead-free fpbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga fn900 = 900-ball lead-free fpbga device family ecp2 (latticeecp2 fpga) ordering information note:tlatticeecp2 devices are dual marked. for example, the commercial speed grade lfe2-50e-7f672c is also marked with industrial grade -6i (lfe2-50e-6f672i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest co mmercial speed grade does not have industrial markings. the markings appear as follows: lfe2-50e 7f672c-6i datecode lfe2-50se 7f672c-6i datecode latticeecp2/m family data sheet ordering information 5-2 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 standard series devi ces, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5t144c 90 1.2v -5 tqfp 144 com 6 lfe2-6e-6t144c 90 1.2v -6 tqfp 144 com 6 lfe2-6e-7t144c 90 1.2v -7 tqfp 144 com 6 lfe2-6e-5f256c 190 1.2v -5 fpbga 256 com 6 lfe2-6e-6f256c 190 1.2v -6 fpbga 256 com 6 lfe2-6e-7f256c 190 1.2v -7 fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5t144c 93 1.2v -5 tqfp 144 com 12 lfe2-12e-6t144c 93 1.2v -6 tqfp 144 com 12 lfe2-12e-7t144c 93 1.2v -7 tqfp 144 com 12 lfe2-12e-5q208c 131 1.2v -5 pqfp 208 com 12 lfe2-12e-6q208c 131 1.2v -6 pqfp 208 com 12 lfe2-12e-7q208c 131 1.2v -7 pqfp 208 com 12 lfe2-12e-5f256c 193 1.2v -5 fpbga 256 com 12 lfe2-12e-6f256c 193 1.2v -6 fpbga 256 com 12 lfe2-12e-7f256c 193 1.2v -7 fpbga 256 com 12 lfe2-12e-5f484c 297 1.2v -5 fpbga 484 com 12 lfe2-12e-6f484c 297 1.2v -6 fpbga 484 com 12 lfe2-12e-7f484c 297 1.2v -7 fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5q208c 131 1.2v -5 pqfp 208 com 20 lfe2-20e-6q208c 131 1.2v -6 pqfp 208 com 20 lfe2-20e-7q208c 131 1.2v -7 pqfp 208 com 20 lfe2-20e-5f256c 193 1.2v -5 fpbga 256 com 20 lfe2-20e-6f256c 193 1.2v -6 fpbga 256 com 20 lfe2-20e-7f256c 193 1.2v -7 fpbga 256 com 20 lfe2-20e-5f484c 331 1.2v -5 fpbga 484 com 20 lfe2-20e-6f484c 331 1.2v -6 fpbga 484 com 20 lfe2-20e-7f484c 331 1.2v -7 fpbga 484 com 20 lfe2-20e-5f672c 402 1.2v -5 fpbga 672 com 20 lfe2-20e-6f672c 402 1.2v -6 fpbga 672 com 20 lfe2-20e-7f672c 402 1.2v -7 fpbga 672 com 20 5-3 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5f484c 331 1.2v -5 fpbga 484 com 35 lfe2-35e-6f484c 331 1.2v -6 fpbga 484 com 35 lfe2-35e-7f484c 331 1.2v -7 fpbga 484 com 35 lfe2-35e-5f672c 450 1.2v -5 fpbga 672 com 35 lfe2-35e-6f672c 450 1.2v -6 fpbga 672 com 35 lfe2-35e-7f672c 450 1.2v -7 fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5f484c 339 1.2v -5 fpbga 484 com 50 lfe2-50e-6f484c 339 1.2v -6 fpbga 484 com 50 lfe2-50e-7f484c 339 1.2v -7 fpbga 484 com 50 lfe2-50e-5f672c 500 1.2v -5 fpbga 672 com 50 lfe2-50e-6f672c 500 1.2v -6 fpbga 672 com 50 lfe2-50e-7f672c 500 1.2v -7 fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5f672c 500 1.2v -5 fpbga 672 com 70 lfe2-70e-6f672c 500 1.2v -6 fpbga 672 com 70 lfe2-70e-7f672c 500 1.2v -7 fpbga 672 com 70 lfe2-70e-5f900c 583 1.2v -5 fpbga 900 com 70 lfe2-70e-6f900c 583 1.2v -6 fpbga 900 com 70 lfe2-70e-7f900c 583 1.2v -7 fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5t144i 90 1.2v -5 tqfp 144 ind 6 lfe2-6e-6t144i 90 1.2v -6 tqfp 144 ind 6 lfe2-6e-5f256i 190 1.2v -5 fpbga 256 ind 6 lfe2-6e-6f256i 190 1.2v -6 fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5t144i 93 1.2v -5 tqfp 144 ind 12 lfe2-12e-6t144i 93 1.2v -6 tqfp 144 ind 12 lfe2-12e-5q208i 131 1.2v -5 pqfp 208 ind 12 lfe2-12e-6q208i 131 1.2v -6 pqfp 208 ind 12 lfe2-12e-5f256i 193 1.2v -5 fpbga 256 ind 12 lfe2-12e-6f256i 193 1.2v -6 fpbga 256 ind 12 lfe2-12e-5f484i 297 1.2v -5 fpbga 484 ind 12 lfe2-12e-6f484i 297 1.2v -6 fpbga 484 ind 12 5-4 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5q208i 131 1.2v -5 pqfp 208 ind 20 lfe2-20e-6q208i 131 1.2v -6 pqfp 208 ind 20 lfe2-20e-5f256i 193 1.2v -5 fpbga 256 ind 20 lfe2-20e-6f256i 193 1.2v -6 fpbga 256 ind 20 lfe2-20e-5f484i 331 1.2v -5 fpbga 484 ind 20 lfe2-20e-6f484i 331 1.2v -6 fpbga 484 ind 20 lfe2-20e-5f672i 402 1.2v -5 fpbga 672 ind 20 lfe2-20e-6f672i 402 1.2v -6 fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5f484i 331 1.2v -5 fpbga 484 ind 35 lfe2-35e-6f484i 331 1.2v -6 fpbga 484 ind 35 lfe2-35e-5f672i 450 1.2v -5 fpbga 672 ind 35 lfe2-35e-6f672i 450 1.2v -6 fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5f484i 339 1.2v -5 fpbga 484 ind 50 lfe2-50e-6f484i 339 1.2v -6 fpbga 484 ind 50 lfe2-50e-5f672i 500 1.2v -5 fpbga 672 ind 50 lfe2-50e-6f672i 500 1.2v -6 fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5f672i 500 1.2v -5 fpbga 672 ind 70 lfe2-70e-6f672i 500 1.2v -6 fpbga 672 ind 70 lfe2-70e-5f900i 583 1.2v -5 fpbga 900 ind 70 lfe2-70e-6f900i 583 1.2v -6 fpbga 900 ind 70 5-5 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 standard series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5tn144c 90 1.2v -5 lead-free tqfp 144 com 6 lfe2-6e-6tn144c 90 1.2v -6 lead-free tqfp 144 com 6 lfe2-6e-7tn144c 90 1.2v -7 lead-free tqfp 144 com 6 lfe2-6e-5fn256c 190 1.2v -5 lead-free fpbga 256 com 6 lfe2-6e-6fn256c 190 1.2v -6 lead-free fpbga 256 com 6 lfe2-6e-7fn256c 190 1.2v -7 lead-free fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5tn144c 93 1.2v -5 lead-free tqfp 144 com 12 lfe2-12e-6tn144c 93 1.2v -6 lead-free tqfp 144 com 12 lfe2-12e-7tn144c 93 1.2v -7 lead-free tqfp 144 com 12 lfe2-12e-5qn208c 131 1.2v -5 lead-free pqfp 208 com 12 lfe2-12e-6qn208c 131 1.2v -6 lead-free pqfp 208 com 12 lfe2-12e-7qn208c 131 1.2v -7 lead-free pqfp 208 com 12 lfe2-12e-5fn256c 193 1.2v -5 lead-free fpbga 256 com 12 lfe2-12e-6fn256c 193 1.2v -6 lead-free fpbga 256 com 12 lfe2-12e-7fn256c 193 1.2v -7 lead-free fpbga 256 com 12 lfe2-12e-5fn484c 297 1.2v -5 lead-free fpbga 484 com 12 lfe2-12e-6fn484c 297 1.2v -6 lead-free fpbga 484 com 12 lfe2-12e-7fn484c 297 1.2v -7 lead-free fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5qn208c 131 1.2v -5 lead-free pqfp 208 com 20 lfe2-20e-6qn208c 131 1.2v -6 lead-free pqfp 208 com 20 lfe2-20e-7qn208c 131 1.2v -7 lead-free pqfp 208 com 20 lfe2-20e-5fn256c 193 1.2v -5 lead-free fpbga 256 com 20 lfe2-20e-6fn256c 193 1.2v -6 lead-free fpbga 256 com 20 lfe2-20e-7fn256c 193 1.2v -7 lead-free fpbga 256 com 20 lfe2-20e-5fn484c 331 1.2v -5 lead-free fpbga 484 com 20 lfe2-20e-6fn484c 331 1.2v -6 lead-free fpbga 484 com 20 lfe2-20e-7fn484c 331 1.2v -7 lead-free fpbga 484 com 20 lfe2-20e-5fn672c 402 1.2v -5 lead-free fpbga 672 com 20 lfe2-20e-6fn672c 402 1.2v -6 lead-free fpbga 672 com 20 lfe2-20e-7fn672c 402 1.2v -7 lead-free fpbga 672 com 20 5-6 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5fn484c 331 1.2v -5 lead-free fpbga 484 com 35 lfe2-35e-6fn484c 331 1.2v -6 lead-free fpbga 484 com 35 lfe2-35e-7fn484c 331 1.2v -7 lead-free fpbga 484 com 35 lfe2-35e-5fn672c 450 1.2v -5 lead-free fpbga 672 com 35 lfe2-35e-6fn672c 450 1.2v -6 lead-free fpbga 672 com 35 lfe2-35e-7fn672c 450 1.2v -7 lead-free fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5fn484c 339 1.2v -5 lead-free fpbga 484 com 50 lfe2-50e-6fn484c 339 1.2v -6 lead-free fpbga 484 com 50 lfe2-50e-7fn484c 339 1.2v -7 lead-free fpbga 484 com 50 lfe2-50e-5fn672c 500 1.2v -5 lead-free fpbga 672 com 50 lfe2-50e-6fn672c 500 1.2v -6 lead-free fpbga 672 com 50 lfe2-50e-7fn672c 500 1.2v -7 lead-free fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5fn672c 500 1.2v -5 lead-free fpbga 672 com 70 lfe2-70e-6fn672c 500 1.2v -6 lead-free fpbga 672 com 70 lfe2-70e-7fn672c 500 1.2v -7 lead-free fpbga 672 com 70 lfe2-70e-5fn900c 583 1.2v -5 lead-free fpbga 900 com 70 lfe2-70e-6fn900c 583 1.2v -6 lead-free fpbga 900 com 70 lfe2-70e-7fn900c 583 1.2v -7 lead-free fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5tn144i 90 1.2v -5 lead-free tqfp 144 ind 6 lfe2-6e-6tn144i 90 1.2v -6 lead-free tqfp 144 ind 6 lfe2-6e-5fn256i 190 1.2v -5 lead-free fpbga 256 ind 6 lfe2-6e-6fn256i 190 1.2v -6 lead-free fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5tn144i 93 1.2v -5 lead-free tqfp 144 ind 12 lfe2-12e-6tn144i 93 1.2v -6 lead-free tqfp 144 ind 12 lfe2-12e-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 12 lfe2-12e-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 12 lfe2-12e-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 12 lfe2-12e-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 12 lfe2-12e-5fn484i 297 1.2v -5 lead-free fpbga 484 ind 12 lfe2-12e-6fn484i 297 1.2v -6 lead-free fpbga 484 ind 12 5-7 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 20 lfe2-20e-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 20 lfe2-20e-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 20 lfe2-20e-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 20 lfe2-20e-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 20 lfe2-20e-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 20 lfe2-20e-5fn672i 402 1.2v -5 lead-free fpbga 672 ind 20 lfe2-20e-6fn672i 402 1.2v -6 lead-free fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 35 lfe2-35e-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 35 lfe2-35e-5fn672i 450 1.2v -5 lead-free fpbga 672 ind 35 lfe2-35e-6fn672i 450 1.2v -6 lead-free fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5fn484i 339 1.2v -5 lead-free fpbga 484 ind 50 lfe2-50e-6fn484i 339 1.2v -6 lead-free fpbga 484 ind 50 lfe2-50e-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 50 lfe2-50e-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 70 lfe2-70e-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 70 lfe2-70e-5fn900i 583 1.2v -5 lead-free fpbga 900 ind 70 lfe2-70e-6fn900i 583 1.2v -6 lead-free fpbga 900 ind 70 5-8 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 s-series devices, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5t144c 90 1.2v -5 tqfp 144 com 6 lfe2-6se-6t144c 90 1.2v -6 tqfp 144 com 6 lfe2-6se-7t144c 90 1.2v -7 tqfp 144 com 6 lfe2-6se-5f256c 190 1.2v -5 fpbga 256 com 6 lfe2-6se-6f256c 190 1.2v -6 fpbga 256 com 6 lfe2-6se-7f256c 190 1.2v -7 fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5t144c 93 1.2v -5 tqfp 144 com 12 lfe2-12se-6t144c 93 1.2v -6 tqfp 144 com 12 LFE2-12SE-7T144C 93 1.2v -7 tqfp 144 com 12 lfe2-12se-5q208c 131 1.2v -5 pqfp 208 com 12 lfe2-12se-6q208c 131 1.2v -6 pqfp 208 com 12 lfe2-12se-7q208c 131 1.2v -7 pqfp 208 com 12 lfe2-12se-5f256c 193 1.2v -5 fpbga 256 com 12 lfe2-12se-6f256c 193 1.2v -6 fpbga 256 com 12 lfe2-12se-7f256c 193 1.2v -7 fpbga 256 com 12 lfe2-12se-5f484c 297 1.2v -5 fpbga 484 com 12 lfe2-12se-6f484c 297 1.2v -6 fpbga 484 com 12 lfe2-12se-7f484c 297 1.2v -7 fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5q208c 131 1.2v -5 pqfp 208 com 20 lfe2-20se-6q208c 131 1.2v -6 pqfp 208 com 20 lfe2-20se-7q208c 131 1.2v -7 pqfp 208 com 20 lfe2-20se-5f256c 193 1.2v -5 fpbga 256 com 20 lfe2-20se-6f256c 193 1.2v -6 fpbga 256 com 20 lfe2-20se-7f256c 193 1.2v -7 fpbga 256 com 20 lfe2-20se-5f484c 331 1.2v -5 fpbga 484 com 20 lfe2-20se-6f484c 331 1.2v -6 fpbga 484 com 20 lfe2-20se-7f484c 331 1.2v -7 fpbga 484 com 20 lfe2-20se-5f672c 402 1.2v -5 fpbga 672 com 20 lfe2-20se-6f672c 402 1.2v -6 fpbga 672 com 20 lfe2-20se-7f672c 402 1.2v -7 fpbga 672 com 20 5-9 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5f484c 331 1.2v -5 fpbga 484 com 35 lfe2-35se-6f484c 331 1.2v -6 fpbga 484 com 35 lfe2-35se-7f484c 331 1.2v -7 fpbga 484 com 35 lfe2-35se-5f672c 450 1.2v -5 fpbga 672 com 35 lfe2-35se-6f672c 450 1.2v -6 fpbga 672 com 35 lfe2-35se-7f672c 450 1.2v -7 fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5f484c 339 1.2v -5 fpbga 484 com 50 lfe2-50se-6f484c 339 1.2v -6 fpbga 484 com 50 lfe2-50se-7f484c 339 1.2v -7 fpbga 484 com 50 lfe2-50se-5f672c 500 1.2v -5 fpbga 672 com 50 lfe2-50se-6f672c 500 1.2v -6 fpbga 672 com 50 lfe2-50se-7f672c 500 1.2v -7 fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5f672c 500 1.2v -5 fpbga 672 com 70 lfe2-70se-6f672c 500 1.2v -6 fpbga 672 com 70 lfe2-70se-7f672c 500 1.2v -7 fpbga 672 com 70 lfe2-70se-5f900c 583 1.2v -5 fpbga 900 com 70 lfe2-70se-6f900c 583 1.2v -6 fpbga 900 com 70 lfe2-70se-7f900c 583 1.2v -7 fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5t144i 90 1.2v -5 tqfp 144 ind 6 lfe2-6se-6t144i 90 1.2v -6 tqfp 144 ind 6 lfe2-6se-5f256i 190 1.2v -5 fpbga 256 ind 6 lfe2-6se-6f256i 190 1.2v -6 fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5t144i 93 1.2v -5 tqfp 144 ind 12 lfe2-12se-6t144i 93 1.2v -6 tqfp 144 ind 12 lfe2-12se-5q208i 131 1.2v -5 pqfp 208 ind 12 lfe2-12se-6q208i 131 1.2v -6 pqfp 208 ind 12 lfe2-12se-5f256i 193 1.2v -5 fpbga 256 ind 12 lfe2-12se-6f256i 193 1.2v -6 fpbga 256 ind 12 lfe2-12se-5f484i 297 1.2v -5 fpbga 484 ind 12 lfe2-12se-6f484i 297 1.2v -6 fpbga 484 ind 12 5-10 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5q208i 131 1.2v -5 pqfp 208 ind 20 lfe2-20se-6q208i 131 1.2v -6 pqfp 208 ind 20 lfe2-20se-5f256i 193 1.2v -5 fpbga 256 ind 20 lfe2-20se-6f256i 193 1.2v -6 fpbga 256 ind 20 lfe2-20se-5f484i 331 1.2v -5 fpbga 484 ind 20 lfe2-20se-6f484i 331 1.2v -6 fpbga 484 ind 20 lfe2-20se-5f672i 402 1.2v -5 fpbga 672 ind 20 lfe2-20se-6f672i 402 1.2v -6 fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5f484i 331 1.2v -5 fpbga 484 ind 35 lfe2-35se-6f484i 331 1.2v -6 fpbga 484 ind 35 lfe2-35se-5f672i 450 1.2v -5 fpbga 672 ind 35 lfe2-35se-6f672i 450 1.2v -6 fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5f484i 339 1.2v -5 fpbga 484 ind 50 lfe2-50se-6f484i 339 1.2v -6 fpbga 484 ind 50 lfe2-50se-5f672i 500 1.2v -5 fpbga 672 ind 50 lfe2-50se-6f672i 500 1.2v -6 fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5f672i 500 1.2v -5 fpbga 672 ind 70 lfe2-70se-6f672i 500 1.2v -6 fpbga 672 ind 70 lfe2-70se-5f900i 583 1.2v -5 fpbga 900 ind 70 lfe2-70se-6f900i 583 1.2v -6 fpbga 900 ind 70 5-11 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2 s-series devi ces, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5tn144c 90 1.2v -5 lead-free tqfp 144 com 6 lfe2-6se-6tn144c 90 1.2v -6 lead-free tqfp 144 com 6 lfe2-6se-7tn144c 90 1.2v -7 lead-free tqfp 144 com 6 lfe2-6se-5fn256c 190 1.2v -5 lead-free fpbga 256 com 6 lfe2-6se-6fn256c 190 1.2v -6 lead-free fpbga 256 com 6 lfe2-6se-7fn256c 190 1.2v -7 lead-free fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5tn144c 93 1.2v -5 lead-free tqfp 144 com 12 lfe2-12se-6tn144c 93 1.2v -6 lead-free tqfp 144 com 12 lfe2-12se-7tn144c 93 1.2v -7 lead-free tqfp 144 com 12 lfe2-12se-5qn208c 131 1.2v -5 lead-free pqfp 208 com 12 lfe2-12se-6qn208c 131 1.2v -6 lead-free pqfp 208 com 12 lfe2-12se-7qn208c 131 1.2v -7 lead-free pqfp 208 com 12 lfe2-12se-5fn256c 193 1.2v -5 lead-free fpbga 256 com 12 lfe2-12se-6fn256c 193 1.2v -6 lead-free fpbga 256 com 12 lfe2-12se-7fn256c 193 1.2v -7 lead-free fpbga 256 com 12 lfe2-12se-5fn484c 297 1.2v -5 lead-free fpbga 484 com 12 lfe2-12se-6fn484c 297 1.2v -6 lead-free fpbga 484 com 12 lfe2-12se-7fn484c 297 1.2v -7 lead-free fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5qn208c 131 1.2v -5 lead-free pqfp 208 com 20 lfe2-20se-6qn208c 131 1.2v -6 lead-free pqfp 208 com 20 lfe2-20se-7qn208c 131 1.2v -7 lead-free pqfp 208 com 20 lfe2-20se-5fn256c 193 1.2v -5 lead-free fpbga 256 com 20 lfe2-20se-6fn256c 193 1.2v -6 lead-free fpbga 256 com 20 lfe2-20se-7fn256c 193 1.2v -7 lead-free fpbga 256 com 20 lfe2-20se-5fn484c 331 1.2v -5 lead-free fpbga 484 com 20 lfe2-20se-6fn484c 331 1.2v -6 lead-free fpbga 484 com 20 lfe2-20se-7fn484c 331 1.2v -7 lead-free fpbga 484 com 20 lfe2-20se-5fn672c 402 1.2v -5 lead-free fpbga 672 com 20 lfe2-20se-6fn672c 402 1.2v -6 lead-free fpbga 672 com 20 lfe2-20se-7fn672c 402 1.2v -7 lead-free fpbga 672 com 20 5-12 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5fn484c 331 1.2v -5 lead-free fpbga 484 com 35 lfe2-35se-6fn484c 331 1.2v -6 lead-free fpbga 484 com 35 lfe2-35se-7fn484c 331 1.2v -7 lead-free fpbga 484 com 35 lfe2-35se-5fn672c 450 1.2v -5 lead-free fpbga 672 com 35 lfe2-35se-6fn672c 450 1.2v -6 lead-free fpbga 672 com 35 lfe2-35se-7fn672c 450 1.2v -7 lead-free fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5fn484c 339 1.2v -5 lead-free fpbga 484 com 50 lfe2-50se-6fn484c 339 1.2v -6 lead-free fpbga 484 com 50 lfe2-50se-7fn484c 339 1.2v -7 lead-free fpbga 484 com 50 lfe2-50se-5fn672c 500 1.2v -5 lead-free fpbga 672 com 50 lfe2-50se-6fn672c 500 1.2v -6 lead-free fpbga 672 com 50 lfe2-50se-7fn672c 500 1.2v -7 lead-free fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5fn672c 500 1.2v -5 lead-free fpbga 672 com 70 lfe2-70se-6fn672c 500 1.2v -6 lead-free fpbga 672 com 70 lfe2-70se-7fn672c 500 1.2v -7 lead-free fpbga 672 com 70 lfe2-70se-5fn900c 583 1.2v -5 lead-free fpbga 900 com 70 lfe2-70se-6fn900c 583 1.2v -6 lead-free fpbga 900 com 70 lfe2-70se-7fn900c 583 1.2v -7 lead-free fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5tn144i 90 1.2v -5 lead-free tqfp 144 ind 6 lfe2-6se-6tn144i 90 1.2v -6 lead-free tqfp 144 ind 6 lfe2-6se-5fn256i 190 1.2v -5 lead-free fpbga 256 ind 6 lfe2-6se-6fn256i 190 1.2v -6 lead-free fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5tn144i 93 1.2v -5 lead-free tqfp 144 ind 12 lfe2-12se-6tn144i 93 1.2v -6 lead-free tqfp 144 ind 12 lfe2-12se-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 12 lfe2-12se-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 12 lfe2-12se-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 12 lfe2-12se-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 12 lfe2-12se-5fn484i 297 1.2v -5 lead-free fpbga 484 ind 12 lfe2-12se-6fn484i 297 1.2v -6 lead-free fpbga 484 ind 12 5-13 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 20 lfe2-20se-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 20 lfe2-20se-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 20 lfe2-20se-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 20 lfe2-20se-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 20 lfe2-20se-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 20 lfe2-20se-5fn672i 402 1.2v -5 lead-free fpbga 672 ind 20 lfe2-20se-6fn672i 402 1.2v -6 lead-free fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 35 lfe2-35se-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 35 lfe2-35se-5fn672i 450 1.2v -5 lead-free fpbga 672 ind 35 lfe2-35se-6fn672i 450 1.2v -6 lead-free fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5fn484i 339 1.2v -5 lead-free fpbga 484 ind 50 lfe2-50se-6fn484i 339 1.2v -6 lead-free fpbga 484 ind 50 lfe2-50se-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 50 lfe2-50se-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 70 lfe2-70se-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 70 lfe2-70se-5fn900i 583 1.2v -5 lead-free fpbga 900 ind 70 lfe2-70se-6fn900i 583 1.2v -6 lead-free fpbga 900 ind 70 5-14 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m part number description lfe2m xxx xe ? x xxxxxx x grade c = commercial i = industrial logic capacity 20 = 20k luts 35 = 35k luts 50 = 50k luts 70 = 70k luts 100 = 100k luts supply voltage e = 1.2v speed 5 = slowest 6 7 = fastest package f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga f1152 = 1152-ball fpbga fn256 = 256-ball lead-free fpbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga fn900 = 900-ball lead-free fpbga fn1152 = 1152-ball lead-free fpbga device family ecp2m (latticeecp2 fpga + serdes) encryption s = security series (encryption feature) blank = standard series (no encryption) ordering information note:tlatticeecp2m devices are dual marked. for example, the commercial speed grade lfe2m50e-7f672c is also marked with industrial grade -6i (lfe2m50e-6f672i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial grade does not have industrial markings. the markings appear as follows: lfe2m35e 7f672c-6i datecode lfe2m35se 7f672c-6i datecode 5-15 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m standard series de vices, conventional packaging commercial part number i/os voltage grad e package pins temp. luts (k) lfe2m20e-5f484c 304 1.2v -5 fpbga 484 com 20 lfe2m20e-6f484c 304 1.2v -6 fpbga 484 com 20 lfe2m20e-7f484c 304 1.2v -7 fpbga 484 com 20 lfe2m20e-5f256c 140 1.2v -5 fpbga 256 com 20 lfe2m20e-6f256c 140 1.2v -6 fpbga 256 com 20 lfe2m20e-7f256c 140 1.2v -7 fpbga 256 com 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35e-5f672c 410 1.2v -5 fpbga 672 com 35 lfe2m35e-6f672c 410 1.2v -6 fpbga 672 com 35 lfe2m35e-7f672c 410 1.2v -7 fpbga 672 com 35 lfe2m35e-5f484c 303 1.2v -5 fpbga 484 com 35 lfe2m35e-6f484c 303 1.2v -6 fpbga 484 com 35 lfe2m35e-7f484c 303 1.2v -7 fpbga 484 com 35 lfe2m35e-5f256c 140 1.2v -5 fpbga 256 com 35 lfe2m35e-6f256c 140 1.2v -6 fpbga 256 com 35 lfe2m35e-7f256c 140 1.2v -7 fpbga 256 com 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50e-5f900c 410 1.2v -5 fpbga 900 com 50 lfe2m50e-6f900c 410 1.2v -6 fpbga 900 com 50 lfe2m50e-7f900c 410 1.2v -7 fpbga 900 com 50 lfe2m50e-5f672c 372 1.2v -5 fpbga 672 com 50 lfe2m50e-6f672c 372 1.2v -6 fpbga 672 com 50 lfe2m50e-7f672c 372 1.2v -7 fpbga 672 com 50 lfe2m50e-5f484c 270 1.2v -5 fpbga 484 com 50 lfe2m50e-6f484c 270 1.2v -6 fpbga 484 com 50 lfe2m50e-7f484c 270 1.2v -7 fpbga 484 com 50 part number i/os voltage grad e package pins temp. luts (k) lfe2m70e-5f1152c 436 1.2v -5 fpbga 1152 com 70 lfe2m70e-6f1152c 436 1.2v -6 fpbga 1152 com 70 lfe2m70e-7f1152c 436 1.2v -7 fpbga 1152 com 70 lfe2m70e-5f900c 416 1.2v -5 fpbga 900 com 70 lfe2m70e-6f900c 416 1.2v -6 fpbga 900 com 70 lfe2m70e-7f900c 416 1.2v -7 fpbga 900 com 70 5-16 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grad e package pins temp. luts (k) lfe2m100e-5f1152c 520 1.2v -5 fpbga 1152 com 100 lfe2m100e-6f1152c 520 1.2v -6 fpbga 1152 com 100 lfe2m100e-7f1152c 520 1.2v -7 fpbga 1152 com 100 lfe2m100e-5f900c 416 1.2v -5 fpbga 900 com 100 lfe2m100e-6f900c 416 1.2v -6 fpbga 900 com 100 lfe2m100e-7f900c 416 1.2v -7 fpbga 900 com 100 5-17 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5f484i 304 1.2v -5 fpbga 484 ind 20 lfe2m20e-6f484i 304 1.2v -6 fpbga 484 ind 20 lfe2m20e-5f256i 140 1.2v -5 fpbga 256 ind 20 lfe2m20e-6f256i 140 1.2v -6 fpbga 256 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5f672i 410 1.2v -5 fpbga 672 ind 35 lfe2m35e-6f672i 410 1.2v -6 fpbga 672 ind 35 lfe2m35e-5f484i 303 1.2v -5 fpbga 484 ind 35 lfe2m35e-6f484i 303 1.2v -6 fpbga 484 ind 35 lfe2m35e-5f256i 140 1.2v -5 fpbga 256 ind 35 lfe2m35e-6f256i 140 1.2v -6 fpbga 256 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5f900i 410 1.2v -5 fpbga 900 ind 50 lfe2m50e-6f900i 410 1.2v -6 fpbga 900 ind 50 lfe2m50e-5f672i 372 1.2v -5 fpbga 672 ind 50 lfe2m50e-6f672i 372 1.2v -6 fpbga 672 ind 50 lfe2m50e-5f484i 270 1.2v -5 fpbga 484 ind 50 lfe2m50e-6f484i 270 1.2v -6 fpbga 484 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5f1152i 436 1.2v -5 fpbga 1152 ind 70 lfe2m70e-6f1152i 436 1.2v -6 fpbga 1152 ind 70 lfe2m70e-5f900i 416 1.2v -5 fpbga 900 ind 70 lfe2m70e-6f900i 416 1.2v -6 fpbga 900 ind 70 part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5f1152i 520 1.2v -5 fpbga 1152 ind 100 lfe2m100e-6f1152i 520 1.2v -6 fpbga 1152 ind 100 lfe2m100e-5f900i 416 1.2v -5 fpbga 900 ind 100 lfe2m100e-6f900i 416 1.2v -6 fpbga 900 ind 100 5-18 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m standard series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5fn484c 304 1.2v -5 lead-free fpbga 484 com 20 lfe2m20e-6fn484c 304 1.2v -6 lead-free fpbga 484 com 20 lfe2m20e-7fn484c 304 1.2v -7 lead-free fpbga 484 com 20 lfe2m20e-5fn256c 140 1.2v -5 lead-free fpbga 256 com 20 lfe2m20e-6fn256c 140 1.2v -6 lead-free fpbga 256 com 20 lfe2m20e-7fn256c 140 1.2v -7 lead-free fpbga 256 com 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5fn672c 410 1.2v -5 lead-free fpbga 672 com 35 lfe2m35e-6fn672c 410 1.2v -6 lead-free fpbga 672 com 35 lfe2m35e-7fn672c 410 1.2v -7 lead-free fpbga 672 com 35 lfe2m35e-5fn484c 303 1.2v -5 lead-free fpbga 484 com 35 lfe2m35e-6fn484c 303 1.2v -6 lead-free fpbga 484 com 35 lfe2m35e-7fn484c 303 1.2v -7 lead-free fpbga 484 com 35 lfe2m35e-5fn256c 140 1.2v -5 lead-free fpbga 256 com 35 lfe2m35e-6fn256c 140 1.2v -6 lead-free fpbga 256 com 35 lfe2m35e-7fn256c 140 1.2v -7 lead-free fpbga 256 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5fn900c 410 1.2v -5 lead-free fpbga 900 com 50 lfe2m50e-6fn900c 410 1.2v -6 lead-free fpbga 900 com 50 lfe2m50e-7fn900c 410 1.2v -7 lead-free fpbga 900 com 50 lfe2m50e-5fn672c 372 1.2v -5 lead-free fpbga 672 com 50 lfe2m50e-6fn672c 372 1.2v -6 lead-free fpbga 672 com 50 lfe2m50e-7fn672c 372 1.2v -7 lead-free fpbga 672 com 50 lfe2m50e-5fn484c 270 1.2v -5 lead-free fpbga 484 com 50 lfe2m50e-6fn484c 270 1.2v -6 lead-free fpbga 484 com 50 lfe2m50e-7fn484c 270 1.2v -7 lead-free fpbga 484 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5fn1152c 436 1.2v -5 lead-free fpbga 1152 com 70 lfe2m70e-6fn1152c 436 1.2v -6 lead-free fpbga 1152 com 70 lfe2m70e-7fn1152c 436 1.2v -7 lead-free fpbga 1152 com 70 lfe2m70e-5fn900c 416 1.2v -5 lead-free fpbga 900 com 70 lfe2m70e-6fn900c 416 1.2v -6 lead-free fpbga 900 com 70 lfe2m70e-7fn900c 416 1.2v -7 lead-free fpbga 900 com 70 5-19 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5fn1152c 520 1.2v -5 lead-free fpbga 1152 com 100 lfe2m100e-6fn1152c 520 1.2v -6 lead-free fpbga 1152 com 100 lfe2m100e-7fn1152c 520 1.2v -7 lead-free fpbga 1152 com 100 lfe2m100e-5fn900c 416 1.2v -5 lead-free fpbga 900 com 100 lfe2m100e-6fn900c 416 1.2v -6 lead-free fpbga 900 com 100 lfe2m100e-7fn900c 416 1.2v -7 lead-free fpbga 900 com 100 part number i/os voltage grad e package pins temp. luts (k) lfe2m20e-5fn484i 304 1.2v -5 lead-free fpbga 484 ind 20 lfe2m20e-6fn484i 304 1.2v -6 lead-free fpbga 484 ind 20 lfe2m20e-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 20 lfe2m20e-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35e-5fn672i 410 1.2v -5 lead-free fpbga 672 ind 35 lfe2m35e-6fn672i 410 1.2v -6 lead-free fpbga 672 ind 35 lfe2m35e-5fn484i 303 1.2v -5 lead-free fpbga 484 ind 35 lfe2m35e-6fn484i 303 1.2v -6 lead-free fpbga 484 ind 35 lfe2m35e-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 35 lfe2m35e-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50e-5fn900i 410 1.2v -5 lead-free fpbga 900 ind 50 lfe2m50e-6fn900i 410 1.2v -6 lead-free fpbga 900 ind 50 lfe2m50e-5fn672i 372 1.2v -5 lead-free fpbga 672 ind 50 lfe2m50e-6fn672i 372 1.2v -6 lead-free fpbga 672 ind 50 lfe2m50e-5fn484i 270 1.2v -5 lead-free fpbga 484 ind 50 lfe2m50e-6fn484i 270 1.2v -6 lead-free fpbga 484 ind 50 part number i/os voltage grad e package pins temp. luts (k) lfe2m70e-5fn1152i 436 1.2v -5 lead-free fpbga 1152 ind 70 lfe2m70e-6fn1152i 436 1.2v -6 lead-free fpbga 1152 ind 70 lfe2m70e-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 70 lfe2m70e-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 70 5-20 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m s-series devices, conventional packaging commercial part number i/os voltage grad e package pins temp. luts (k) lfe2m100e-5fn1152i 520 1.2v -5 lead-free fpbga 1152 ind 100 lfe2m100e-6fn1152i 520 1.2v -6 lead-free fpbga 1152 ind 100 lfe2m100e-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 100 lfe2m100e-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 100 part number i/os voltage grad e package pins temp. luts (k) lfe2m20se-5f484c 304 1.2v -5 fpbga 484 com 20 lfe2m20se-6f484c 304 1.2v -6 fpbga 484 com 20 lfe2m20se-7f484c 304 1.2v -7 fpbga 484 com 20 lfe2m20se-5f256c 140 1.2v -5 fpbga 256 com 20 lfe2m20se-6f256c 140 1.2v -6 fpbga 256 com 20 lfe2m20se-7f256c 140 1.2v -7 fpbga 256 com 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35se-5f672c 410 1.2v -5 fpbga 672 com 35 lfe2m35se-6f672c 410 1.2v -6 fpbga 672 com 35 lfe2m35se-7f672c 410 1.2v -7 fpbga 672 com 35 lfe2m35se-5f484c 303 1.2v -5 fpbga 484 com 35 lfe2m35se-6f484c 303 1.2v -6 fpbga 484 com 35 lfe2m35se-7f484c 303 1.2v -7 fpbga 484 com 35 lfe2m35se-5f256c 140 1.2v -5 fpbga 256 com 35 lfe2m35se-6f256c 140 1.2v -6 fpbga 256 com 35 lfe2m35se-7f256c 140 1.2v -7 fpbga 256 com 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50se-5f900c 410 1.2v -5 fpbga 900 com 50 lfe2m50se-6f900c 410 1.2v -6 fpbga 900 com 50 lfe2m50se-7f900c 410 1.2v -7 fpbga 900 com 50 lfe2m50se-5f672c 372 1.2v -5 fpbga 672 com 50 lfe2m50se-6f672c 372 1.2v -6 fpbga 672 com 50 lfe2m50se-7f672c 372 1.2v -7 fpbga 672 com 50 lfe2m50se-5f484c 270 1.2v -5 fpbga 484 com 50 lfe2m50se-6f484c 270 1.2v -6 fpbga 484 com 50 lfe2m50se-7f484c 270 1.2v -7 fpbga 484 com 50 5-21 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grad e package pins temp. luts (k) lfe2m70se-5f1152c 436 1.2v -5 fpbga 1152 com 70 lfe2m70se-6f1152c 436 1.2v -6 fpbga 1152 com 70 lfe2m70se-7f1152c 436 1.2v -7 fpbga 1152 com 70 lfe2m70se-5f900c 416 1.2v -5 fpbga 900 com 70 lfe2m70se-6f900c 416 1.2v -6 fpbga 900 com 70 lfe2m70se-7f900c 416 1.2v -7 fpbga 900 com 70 part number i/os voltage grad e package pins temp. luts (k) lfe2m100se-5f1152c 520 1.2v -5 fpbga 1152 com 100 lfe2m100se-6f1152c 520 1.2v -6 fpbga 1152 com 100 lfe2m100se-7f1152c 520 1.2v -7 fpbga 1152 com 100 lfe2m100se-5f900c 416 1.2v -5 fpbga 900 com 100 lfe2m100se-6f900c 416 1.2v -6 fpbga 900 com 100 lfe2m100se-7f900c 416 1.2v -7 fpbga 900 com 100 5-22 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grad e package pins temp. luts (k) lfe2m20se-5f484i 304 1.2v -5 fpbga 484 ind 20 lfe2m20se-6f484i 304 1.2v -6 fpbga 484 ind 20 lfe2m20se-5f256i 140 1.2v -5 fpbga 256 ind 20 lfe2m20se-6f256i 140 1.2v -6 fpbga 256 ind 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35se-5f672i 410 1.2v -5 fpbga 672 ind 35 lfe2m35se-6f672i 410 1.2v -6 fpbga 672 ind 35 lfe2m35se-5f484i 303 1.2v -5 fpbga 484 ind 35 lfe2m35se-6f484i 303 1.2v -6 fpbga 484 ind 35 lfe2m35se-5f256i 140 1.2v -5 fpbga 256 ind 35 lfe2m35se-6f256i 140 1.2v -6 fpbga 256 ind 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50se-5f900i 410 1.2v -5 fpbga 900 ind 50 lfe2m50se-6f900i 410 1.2v -6 fpbga 900 ind 50 lfe2m50se-5f672i 372 1.2v -5 fpbga 672 ind 50 lfe2m50se-6f672i 372 1.2v -6 fpbga 672 ind 50 lfe2m50se-5f484i 270 1.2v -5 fpbga 484 ind 50 lfe2m50se-6f484i 270 1.2v -6 fpbga 484 ind 50 part number i/os voltage grad e package pins temp. luts (k) lfe2m70se-5f1152i 436 1.2v -5 fpbga 1152 ind 70 lfe2m70se-6f1152i 436 1.2v -6 fpbga 1152 ind 70 lfe2m70se-5f900i 416 1.2v -5 fpbga 900 ind 70 lfe2m70se-6f900i 416 1.2v -6 fpbga 900 ind 70 part number i/os voltage grad e package pins temp. luts (k) lfe2m100se-5f1152i 520 1.2v -5 fpbga 1152 ind 100 lfe2m100se-6f1152i 520 1.2v -6 fpbga 1152 ind 100 lfe2m100se-5f900i 416 1.2v -5 fpbga 900 ind 100 lfe2m100se-6f900i 416 1.2v -6 fpbga 900 ind 100 5-23 ordering information lattice semiconductor latticeecp2 /m family data sheet latticeecp2m s-series de vices, lead-free packaging commercial part number i/os voltage grad e package pins temp. luts (k) lfe2m20se-5fn484c 304 1.2v -5 lead-free fpbga 484 com 20 lfe2m20se-6fn484c 304 1.2v -6 lead-free fpbga 484 com 20 lfe2m20se-7fn484c 304 1.2v -7 lead-free fpbga 484 com 20 lfe2m20se-5fn256c 140 1.2v -5 lead-free fpbga 256 com 20 lfe2m20se-6fn256c 140 1.2v -6 lead-free fpbga 256 com 20 lfe2m20se-7fn256c 140 1.2v -7 lead-free fpbga 256 com 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35se-5fn672c 410 1.2v -5 lead-free fpbga 672 com 35 lfe2m35se-6fn672c 410 1.2v -6 lead-free fpbga 672 com 35 lfe2m35se-7fn672c 410 1.2v -7 lead-free fpbga 672 com 35 lfe2m35se-5fn484c 303 1.2v -5 lead-free fpbga 484 com 35 lfe2m35se-6fn484c 303 1.2v -6 lead-free fpbga 484 com 35 lfe2m35se-7fn484c 303 1.2v -7 lead-free fpbga 484 com 35 lfe2m35se-5fn256c 140 1.2v -5 lead-free fpbga 256 com 35 lfe2m35se-6fn256c 140 1.2v -6 lead-free fpbga 256 com 35 lfe2m35se-7fn256c 140 1.2v -7 lead-free fpbga 256 com 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50se-5fn900c 410 1.2v -5 lead-free fpbga 900 com 50 lfe2m50se-6fn900c 410 1.2v -6 lead-free fpbga 900 com 50 lfe2m50se-7fn900c 410 1.2v -7 lead-free fpbga 900 com 50 lfe2m50se-5fn672c 372 1.2v -5 lead-free fpbga 672 com 50 lfe2m50se-6fn672c 372 1.2v -6 lead-free fpbga 672 com 50 lfe2m50se-7fn672c 372 1.2v -7 lead-free fpbga 672 com 50 lfe2m50se-5fn484c 270 1.2v -5 lead-free fpbga 484 com 50 lfe2m50se-6fn484c 270 1.2v -6 lead-free fpbga 484 com 50 lfe2m50se-7fn484c 270 1.2v -7 lead-free fpbga 484 com 50 part number i/os voltage grad e package pins temp. luts (k) lfe2m70se-5fn1152c 436 1.2v -5 lead-free fpbga 1152 com 70 lfe2m70se-6fn1152c 436 1.2v -6 lead-free fpbga 1152 com 70 lfe2m70se-7fn1152c 436 1.2v -7 lead-free fpbga 1152 com 70 lfe2m70se-5fn900c 416 1.2v -5 lead-free fpbga 900 com 70 lfe2m70se-6fn900c 416 416 -6 lead-free fpbga 900 com 70 lfe2m70se-7fn900c 416 416 -7 lead-free fpbga 900 com 70 5-24 ordering information lattice semiconductor latticeecp2 /m family data sheet part number i/os voltage grad e package pins temp. luts (k) lfe2m100se-5fn1152c 520 1.2v -5 lead-free fpbga 1152 com 100 lfe2m100se-6fn1152c 520 1.2v -6 lead-free fpbga 1152 com 100 lfe2m100se-7fn1152c 520 1.2v -7 lead-free fpbga 1152 com 100 lfe2m100se-5fn900c 416 1.2v -5 lead-free fpbga 900 com 100 lfe2m100se-6fn900c 416 1.2v -6 lead-free fpbga 900 com 100 lfe2m100se-7fn900c 416 1.2v -7 lead-free fpbga 900 com 100 5-25 ordering information lattice semiconductor latticeecp2 /m family data sheet industrial part number i/os voltage grad e package pins temp. luts (k) lfe2m20se-5fn484i 304 1.2v -5 lead-free fpbga 484 ind 20 lfe2m20se-6fn484i 304 1.2v -6 lead-free fpbga 484 ind 20 lfe2m20se-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 20 lfe2m20se-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 20 part number i/os voltage grad e package pins temp. luts (k) lfe2m35se-5fn672i 410 1.2v -5 lead-free fpbga 672 ind 35 lfe2m35se-6fn672i 410 1.2v -6 lead-free fpbga 672 ind 35 lfe2m35se-5fn484i 303 1.2v -5 lead-free fpbga 484 ind 35 lfe2m35se-6fn484i 303 1.2v -6 lead-free fpbga 484 ind 35 lfe2m35se-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 35 lfe2m35se-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 35 part number i/os voltage grad e package pins temp. luts (k) lfe2m50se-5fn900i 410 1.2v -5 lead-free fpbga 900 ind 50 lfe2m50se-6fn900i 410 1.2v -6 lead-free fpbga 900 ind 50 lfe2m50se-5fn672i 372 1.2v -5 lead-free fpbga 672 ind 50 lfe2m50se-6fn672i 372 1.2v -6 lead-free fpbga 672 ind 50 lfe2m50se-5fn484i 270 1.2v -5 lead-free fpbga 484 ind 50 lfe2m50se-6fn484i 270 1.2v -6 lead-free fpbga 484 ind 50 part number i/os voltage grad e package pins temp. luts (k) lfe2m70se-5fn1152i 436 1.2v -5 lead-free fpbga 1152 ind 70 lfe2m70se-6fn1152i 436 1.2v -6 lead-free fpbga 1152 ind 70 lfe2m70se-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 70 lfe2m70se-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 70 part number i/os voltage grad e package pins temp. luts (k) lfe2m100se-5fn1152i 520 1.2v -5 lead-free fpbga 1152 ind 100 lfe2m100se-6fn1152i 520 1.2v -6 lead-free fpbga 1152 ind 100 lfe2m100se-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 100 lfe2m100se-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 100 september 2006 data sheet ds1006 ? 2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1006 further info_01.0 for further information a variety of technical notes for the latticeecp2/m family are available on the lattice web site at www.latticesemi.com . ? tn1124, latticeecp2m serdes/pcs usage guide ? tn1102, latticeecp2/m sysio usage guide ? tn1103, latticeecp2/m sysclock pll design and usage guide ? tn1104, latticeecp2/m memory usage guide ? tn1105, latticeecp2/m high-speed i/o interface ? tn1106, power estimation and management for latticeecp2/m devices ? tn1107, latticeecp2/m sysdsp usage guide ? tn1108, latticeecp2/m sysconfig usage guide ? tn1109, latticeecp2/m configuration encryption usage guide ? tn1113, latticeecp2/m soft error de tection (sed) usage guide ? tn1162, latticeecp2/m hardware checklist for further information about interface standards refer to the following web sites: ? jedec standards (lvttl , lvcmos, sstl, hstl): www.jedec.org ?pci: www.pcisig.com latticeecp2/m family data sheet supplemental information march 2010 data sheet ds1006 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 ds1006 revision history date version section change summary february 2006 01.0 ? initial release. august 2006 01.1 introduction updated table 1-1 ?latticeecp2 family selection guide?. architecture updated figure 2-2 ?pfu diagram?. updated figure 2-13 ?secondary clock regions ecp2-50?. updated figure 2-25 ?pic diagram?. updated figure 2-26 ?input register block for left, right and bottom edges?. updated figure 2-28 ?output register block for left, right and bottom edges?. updated figure 2-30 ?dqs input routing for left and right edges?. updated figure 2-32 ?edge clock, dll calibration and dqs local bus distribution?. table 2-15 selectable master clock (cclk) frequencies - removed frequencies 15, 20, 21, 22, 23, 30, 34, 41, 45, 51, 55, 60. replaced ?clkindel? with ?clko?. updated sed section. qualified device migration capability when using dqs banks for ddr interfaces. dc and switching characteristics added vccpll to the recommended operating conditions table. removed note 5 from ?hot specifications? section. added notes 7 and 8 to ?initialization supply? current table. change note 6 - ?...down to 95mhz? to ?...down to 95mhz for ddr and 133mhz for ddr2? . new ?typical building block function performance? numbers. new external switching characteristics numbers. new internal switching characteristics numbers. new family timing adders numbers. updated timings for gplls, splls and dlls. added sysconfig waveforms. remove hstl15d_ii from sysio recommended operating conditions table. updated supply and initia lization currents for ecp2-50. pinout information added vccpll to the signal descriptions table. updated logic signal connections tables to include 484-fpbga for the ecp2-50. added logic signal connections tables for ecp2-12 devices. updated pin information summary table to include ecp2-12. updated power supply and nc connections table to include ecp2-12. added note 2 to ddr strobe (dqs) pin table. latticeecp2/m family data sheet revision history 7-2 revision history lattice semiconductor latticeecp2 /m family data sheet added information on: pci, ddr & spi4.2 capabilities of the device- package combination. august 2006 (cont.) 01.1 (cont.) pinout information (cont.) added information on: available device resources per packaged device table. ordering information updated ordering part number table to include ecp2-12. updated topside mark drawing. september 2006 02.0 multiple added information regarding latticeecp2m support throughout. september 2006 02.1 dc and switching characteristics added receiver total jitter tolerance specification table. removed power-up requirements for proper configuration footnote in recommended operating conditions table. december 2006 02.2 introduction latticeecp2 m selection guide table has been updated. architecture figure 2-16. per region secondary clock selection has been updated. figure 2-39. simplified channel block diagram for serdes and pcs has been updated. dc and switching footnotes have been added to recommended operating conditions. dc electrical characteristics table has been updated. supply current (standby) tables have been updated. initialization supply current table have been updated. updated timing numbers to include lfe2-12e (rev a 0.08). pinout information updated to include the entire ecp2 device information as well as 256- fpbga and 484-fpbga pin information for the ecp2m35e. ordering information updated to include the entire ecp2 and ecp2m device ordering infor- mation. february 2007 02.3 architecture updated ebr asynchronous reset section. march 2007 02.4 dc and switching characteristics power-sequencing footnotes have been added to the recommended operating conditions. ddr2 performance has been updated to 266mhz. march 2007 02.5 introduction added ?security se ries? to the latticeecp2 and latticeecp2m families. architecture enhanced configuration option section updated. dc and switching recommended operating cond itions table - footnote 4 updated. ordering information ?security series? ordering part numbers added. april 2007 02.6 introduction latticeecp2m family table has been updated for user i/o counts. ordering information latticeecp2m family ordering part number section has been updated to add 1152-fpbga package for the ecp2m70 and ecp2m100. july 2007 02.7 architecture updated text in ripple mode section. dc and switching ecp2/m supply current information has been updated. typical building block function performance, external switching char- acteristics, internal switching characteristics, family timing adders, sysclock gpll timing, sysclock spll timing, dll timing and sysconfig port timing specifications have been updated (timing rev. a 0.10). serdes timing information has been updated. pci express timing information has been updated. pinout information added latticeecp2m20 pinout information. august 2007 02.8 introduction 1156 -fpbga package option has been removed from the latticeecp2m family. architecture table 2-16. selectable mast er clock (cclk) frequencies during con- figuration table has been updated. dc and switching supply current (standby) table has been updated. date version section change summary 7-3 revision history lattice semiconductor latticeecp2 /m family data sheet dsp function timing has been updated. august 2007 (cont.) 02.8 (cont.) dc and switching (cont.) sysclock gpll timing has been updated. pinout information added ecp2m50 (484/672 /900-fpbga), ecp2m70 (900-fpbga) and ecp2m100 (900-fpbga) pinout information. ordering information 1156-fpbga package option has been removed from the latticeecp2m family. september 2007 02.9 pinout information a dded thermal management text section. february 2008 03.0 architecture added lvcmos33d description. dc and switching latticeecp2m supply current has been updated. typical building block function performance, external switching characteristics, internal switching characteristics, family timing adders, sysclock gpll timing, sysclock spll timing, dll tim- ing and sysconfig port timing specif ications have been updated (tim- ing rev. a 0.11). figure 3-9. read/write mode (nor mal) and figure 3-10. read/write mode with input and output registers have been updated. table 3-8. channel output jitter (max) has been updated. pinout information signal description has been updated. added 1152-fpbga pinouts for the ecp2m70 and ecp2m100. april 2008 03.1 pinout information available ddr interfaces per i/o bank for the lfe2m35 (484/672- fpbga) have been updated. june 2008 03.2 introduction family selection guide table - updated number of ebr sram blocks for the ecp2-70 device. architecture removed read-before-write sysmem ebr mode. clarification of the operation of the secondary clock regions. dc and switching characteristics removed read-before-write sysmem ebr mode. august 2008 03.3 architecture clarification of the operation of the secondary clock regions. pinout information added information for [loc]dq[num] to signal descriptions table. january 2009 03.4 dc and switching characteristics updated typical and max. jitter num bers in channel output jitter table for x10 mode. added channel output jitter table for x20 mode. november 2009 03.5 dc and switching characteristics updated spi/spim configuration waveforms diagram. updated footnotes in latticeecp2 initialization supply current table. updated footnotes in latticeecp2m initialization supply current table. updated footnotes in serdes high speed data receiver (latticeecp2m family only) table. updated max. value for t dinit parameter in latticeecp2/m sys- config port timing specifications table. updated serial output timing and levels table. updated figure 3-5 mlvds updated table 3-7 serial output timing and levels updated table 3-15 power down/power up specification pinout information signal descriptions table - corrected references to ulm, urm, lrm (changed to lum, rum and rlm), added footnote 5. date version section change summary 7-4 revision history lattice semiconductor latticeecp2 /m family data sheet november 2009 (cont.) 03.5 (cont.) pinout information (cont.) latticeecp2m pin information summary, lfe2m50, lfe2m70 and lfe2m100 table - corrected values for lfe2m50, 672 fpbga in available ddr-interfaces per i/o bank. minor corrections in lfe2m20e/se and lfe2m35e/se logic signal connections: 484 fpbga table. minor corrections in lfe2m50e/se and lfe2m70e/se logic signal connections: 900 fpbga table. minor corrections in lfe2m100e/se logic signal connections: 900 fpbga table. updated lfe2-6e/se and lfe2-12e/se logical signal connec- tions (changed d1/spids to d1). ordering information updated latticeecp2m part number description diagram. march 2010 03.6 dc and switching characteristics footnote for sed operating frequency added to the sysconfig port timing specifications table. pinout information changed dual function pin e7 to be d7/spdi0 in logic signal connections tables. changed footnote (***) in logic signal con- nections table. date version section change summary section ii. latticeecp2/m family technical notes www.latticesemi.com 8-1 tn1124_03.4 june 2010 technical note tn1124 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction to pcs the latticeecp2m? fpga family combines a high-performance fpga fabric, high-performance i/os and large embedded ram in a single industry-leading architecture. all latticeecp2m devices also feature up to 16 channels of embedded serdes with associated physical coding sublay er (pcs) logic. the pcs logic can be configured to support numerous industry-standard, high-speed data transfer protocols. each channel of pcs logic contains dedicated transmit and receive serdes for high-speed full-duplex serial data transfers at data rates up to 3.125 gbps. the pcs logic in each channel can be configured to support an array of popular data protocols including ethe rnet (1gbe and sgmii), pc i express, cpri, and obsai. in addition, the pro- tocol-based logic can be fully or partially bypassed in a number of configuratio ns to allow users flexibility in design- ing their own high-speed data interface. the pcs also provides bypass modes that allow for a direct 8-bit or 10-bit interface from the serdes to the fpga logic. each serdes pin can be independently dc-coupled and can allow for both high-speed and low-speed oper- ation on the same serdes pin for such applications as serial digital video. features ? up to 16 channels of high-speed serdes ? 250 mbps to 3.125 gbps per channel ? 3.125gbps operation with low 100mw power per channel ? receive equalization and transmit pre-emphasis for small form factor backplane operation ? supports pci express, ethernet (1gbe and sgmii) plus multiple other standards ? supports user specified generic 8b10b mode ? beacon support for pci express ? out-of-band signal interface for low speed inputs (video application) ? multiple clock rate support ? separate reference clocks for each pcs quad allow easy handling of multiple protocol rates on a single device ? full function embedded physical coding sub-layer (pcs) logic supporting industry standard protocols ? up to 16 channels of full-duplex data supported per device ? multiple protocol support on one chip ? supports popular 8b10b based packet protocols ? serdes only mode allows direct 8- or 10-bit interface to fpga logic ? gigabit ethernet support ? ieee 1000base-x compliant ? 8b10b encoding/decoding ? insertion of /i2/ symbols into the receive data stream for auto-negotiation support ? comma character word alignment ? clock tolerance compensation circuit ? pci express support ? x1 to x4 support in one pcs quad ? integrated word aligner ? 8b10b encoding/decoding ? clock tolerance compensation circuit ? electrical idle and re ceiver detection support ? support for beacon transmission and beacon detection latticeecp2m serdes/pcs usage guide 8-2 lattice semiconductor latticeecp 2m serdes/pcs usage guide ? multiple protocol compliant clock tolerance compensation (ctc) logic ? compensates for frequency differential between reference clock and received data rate ? allows user defined skip pattern of 1, 2, or 4 bytes in length ? integrated loopback modes for system debugging ? three loopback modes are provided for system debugging supported standards the supported standards are listed in table 8-1. table 8-1. supported serdes standards (fully supported) it is possible to support xaui, srio , obsai, cpri, 1xfc, 2xfc, picmg 3.1, picmg 3.4, picmg 3.5 and 3g-sdi standards with the serdes modes specified above. contac t lattice semiconductor technical support group for additional information. architecture overview the pcs logic is arranged in quads containing logic for four independent full-duplex data channels. table 8-2 shows the availability of serdes/pcs quads for each device in the latticeecp2m family. table 8-2. serdes/pcs quads per latticeecp2m device pcs quad figure 8-1 is a layout of a latticeecp2m device showin g the arrangement of pcs quads on the device (the largest array containing 4 quads is shown. other devices have fewer quads). standard rates (mbps) refclk (mhz) fp ga clk (mhz) encoding signal type pci express 2500 100 250 8b10b cml gbe/sgmii 1250 125 125 8b10b cml generic 8b10b 250 to 3125 25 to 312.5 25 to 312.5 8b10b/none cml 10-bit serdes only 1 250 to 3125 25 to 312.5 25 to 312.5 none cml 8-bit serdes only 1 250 to 3125 25 to 312.5 25 to 312.5 none cml sd-sdi 2 143, 177, 270, 360 14.3, 17.7, 27, 36 143, 177, 135, 180 smpte scrambled cml hd-sdi 1483.5, 1485 148. 35, 148.5 148.35, 148.5 smpte scrambled cml cpri 614.4 1228.8 61.44 122.88 61.44 122.88 8b10b cml 1. 8-bit serdes only mode and 10-bit serdes only mode bypass t he link align/comma align, 8b10 b encoder/decoder and the ctc. it does not bypass the cdr. 2. serial digital interface (sdi) for standard definition (sd) : 143mbps, 177mbps bypasses the serdes/pcs block. the clock and da ta come in to the fpga through the rx pins but get into the fpga core via the bscan path. cdr is done in the fpga core. in the transmit direc- tion, decimation is used for these ?low? bit rates. to do the cdr in the fpga, reference clock of 14.3mhz and 17.7mhz are requi red respectively. 270mbps is the most common frequenc y. this will go through the 10-bit data path. device ecp2m20 ecp2m35 ecp2m50 ecp2m70 ecp2m100 quad urc yes yes yes yes yes quad lrc ? ? yes yes yes quad ulc ? ? ? yes yes quad llc ? ? ? yes yes 8-3 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-1. latticeecp2m70/100 block diagram every quad can be programmed into one of several protocol based modes. each quad requires its own reference clock which can be sourced externally from package pins or internally from the fpga logic. since each quad has its own reference clock, different quads can support different standards on the same chip. this feature makes the latticeecp2m family of devices ideal for bridging between different standards. pcs quads are not dedicated solely to industry standard protocols. each quad (and each channel within a quad) can be programmed for many user defined data manipulation modes. for example, modes governing user-defined word alignment, and clock tolerance compensation can be programmed for non-protocol operation. pcs quad and channels each quad on a device supports up to four channels of full-duplex data. th e user can utilize anywhere from one to four channels in a quad depending on the application. many options can be set by the user for each channel inde- pendently within a given quad. figure 8-1 also shows an example of a device with four pcs quads which contain a total of 16 pcs channels. quads are named according to the location of the respective quad on the latticeecp2m array: urpcs (upper right pcs), ulpcs (upper left pcs), lrpcs (l ower right pcs), llpcs (lower left pcs). gpll sysio bank 5 sysio bank 4 sysio bank 0 sysio bank 1 sy s io b ank 6 sysio bank 7 sy s io b ank 3 sysio bank 2 spll dl l quadrant tl quadrant tr quadrant br quadrant bl primary clocks eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 eclk1 dqsdll c lkdiv c lkdiv spll spll gpll spll dl l dqsdll spll spll ulpcs (serdes / pcs quad) urpcs (serdes / pcs quad) llpcs (serdes / pcs quad) lrpcs (serdes / pcs quad) 8-4 lattice semiconductor latticeecp 2m serdes/pcs usage guide per channel pcs/fpga interface ports all pcs quads regardless of chosen mode have the same ex ternal high speed serial interface at the package pins. however, every pcs mode has its own unique list of input/output ports from/to the fpga logic appropriate to the protocol chosen for the quad. a detailed description of the quad input/output signals for each mode is provided in this document. a simplified diagram showing the channels within a single quad is shown in figure 8-2. figure 8-2. pcs quad block diagram locating a pcs quad latticeecp2m-50 and larger devices include two to four pcs quads. users can locate each pcs quad in a desired location us ing the locate preference in the preference file. below is an example of the preference, locate. locate comp "pcs_instantiation_1" site urpcs ; detailed channel block diagram figure 8-3 is a detailed block diagram representation of the major functionality in a single channel of the latticeecp2m serdes/pcs. this diagram shows all the major blocks and the majority of the control and status signals that are visible to the user logic in the fpga. th is diagram also shows the major sub-blocks in the channel- serdes, serdes bridge, pcs core and the fpga bridge. fpga core interface ctrl1 ctrl2 quad ctrl pcs channel 0 rx + tx pcs channel 2 rx + tx pcs channel 3 rx + tx pcs channel 1 rx + tx aux channel serdes channel 0 rx + tx serdes channel 2 rx + tx serdes channel 3 rx + tx serdes channel 1 rx + tx ctrl0 ctrl3 hdinp_0 hdinn_0 hdoutp_0 hdoutn_0 hdinp_1 hdinn_1 hdoutp_1 hdoutn_1 hdinp_2 hdinn_2 hdoutp_2 hdoutn_2 hdinp_3 hdinn_3 hdoutp_3 hdoutn_3 clocks/resets transm it data receive data control/status 8-5 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-3. latticeecp2m serdes/ pcs detailed channel block diagram a general description of the fpga interface signals follows. clocks and resets a pcs quad supplies per channel locked reference clocks and per channel recovered receive clocks to the fpga logic interface. each pcs quad provides these clocks on both primary and secondary fpga clock routing. the pcs/fpga interface also has ports for the transmit and receive clocks supplied from the fpga fabric for all four channels in each quad. each quad has reset inputs to force reset of both the serdes and pcs logic in a quad or just the serdes. in addition, separate resets dedicated for the pcs logic are provided for each channel for both the transmit and receive directions. transmit data bus the signals for the transmit data path are from the fpga to the fpga bridge in the pcs block. for high-speed standards, the datapath can be geared 2:1 to the internal pcs data path, which is 8 bits wide (+ control/status sig- nals). the highest speed of the interface for pci expre ss x1 is 250mhz in non-geared mode. with gearing (i.e. a 16-bit wide data path), the maximum speed is 156.25mhz (for xaui 4x channel mode). t he serdes and pcs will support data rates up to 3.125gbps data that correspond to an interface speed of 156.25mhz (with 2:1 gearing). receive data bus the signals for the receive path are from the fpga bridge in the pcs block to the fpga. the data path may be geared 2:1 to the internal pcs data path which is 8 bits wide. it is possible to disable the gearing via a software register bit, in which case, the bus widths are halved. when the data is geared, the lower bits (ff_rx_d[9:0]) are the octet that has been received first and the higher bits (ff_rx_d[19:10]) are the octet that has been received second. if the data is not geared, the lower bits ((ff_rx_d[9:0]) are the active bits and the higher bits should not be used. hdoutp0 hdoutn0 wa elastic buffer los lsm bsrpad rx_sdi_en_ch0 ff_rlos_lo_ch0 ffc_sb_inv_rx_ch0 ff_rxdata[23:0]_ch0 ff_rxiclk_ch0 ff_ebrd_clk_ch0 ff_rxfullclk_ch0 ffs_cc_overrun_ch0 ffs_cc_underrun_ch0 ffc_signal_detect_ch0 ffs_ls_sync_status_ch0 enable_cg_align_ch0 tx_gear_bypass ff_txdata[23:0]_ch0 fb_loop tx_sdi_en bstpad ffc_pcie_ct_ch0 ffc_pcie_con_ch0 ffc_pcie_done_ch0 rx_ sb_b ypass scan inv ck d tdrv _da t_sel[1:0] bypass serdes serdes bridge (sb) pcs core fpga bridge (fb) ser 8:1/10:1 8b/10b encoder up sample fifo pcie link detection eq hdinp0 hdinn0 recovered (byte) clock pd/ sampler ck d 8b/10b decoder refclk c l o c k u p / d n inv ff_txiclk_ch0 ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 1/2 1/4 refcl k ff_txqtrclk ff_txhalfclk ff_txfullclk fpga core detect logic oob_out_ch0 ffc_pcie_det_en_ch0 down sample fifo cdr txpll des 1:8/1:10 1/2 1/4 recovered bit clock bit clk byte clk 8-6 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-3. data bus usage by mode data bus pcs cell name 5 g8b10b cpri pci express gige 8bser 10bser sdi ff_tx_d_0_0 ff_txdata_ch0[0] ff_tx_d_0_1 ff_txdata_ch0[1] ff_tx_d_0_2 ff_txdata_ch0[2] ff_tx_d_0_3 ff_txdata_ch0[3] ff_tx_d_0_4 ff_txdata_ch0[4] ff_tx_d_0_5 ff_txdata_ch0[5] ff_tx_d_0_6 ff_txdata_ch0[6] ff_tx_d_0_7 ff_txdata_ch0[7] ff_tx_d_0_8 ff_tx_k_cntrl_ ch0[0] gnd ff_txdata_ch0[8] ff_tx_d_0_9 ff_force_disp_ch0[0] ] 1 gnd ff_txdata_ch0[9] ff_tx_d_0_10 ff_disp_sel_ch0[0] ] 1 ff_xmit_ch0[0] ] 2 gnd ff_tx_d_0_11 gnd ff_pci_ei_en_ch0[0] ff_correct_disp_ch0[0] gnd ff_tx_d_0_12 ff_txdata_ch0[8] ff_txdata_ch0[10] ff_tx_d_0_13 ff_txdata_ch0[9] ff_txdata_ch0[11] ff_tx_d_0_14 ff_txdata_ch0[10] ff_txdata_ch0[12] ff_tx_d_0_15 ff_txdata_ch0[11] ff_txdata_ch0[13] ff_tx_d_0_16 ff_txdata_ch0[12] ff_txdata_ch0[14] ff_tx_d_0_17 ff_txdata_ch0[13] ff_txdata_ch0[15] ff_tx_d_0_18 ff_txdata_ch0[14] ff_txdata_ch0[16] ff_tx_d_0_19 ff_txdata_ch0[15] ff_txdata_ch0[17] ff_tx_d_0_20 ff_tx_k_cntrl_ ch0[1] gnd ff_txdata_ch0[18] ff_tx_d_0_21 ff_force_disp_ch0[1] ] 1 gnd ff_txdata_ch0[19] ff_tx_d_0_22 ff_disp_sel_ch0[1] ] 1 ff_xmit_ch0[1] ] 2 gnd ff_tx_d_0_23 gnd ff_pci_ei_en_ch0[1] ff_correct_disp_ch0[1] gnd ff_rx_d_0_0 ff_rxdata_ch0[0] ff_rx_d_0_1 ff_rxdata_ch0[1] ff_rx_d_0_2 ff_rxdata_ch0[2] ff_rx_d_0_3 ff_rxdata_ch0[3] ff_rx_d_0_4 ff_rxdata_ch0[4] ff_rx_d_0_5 ff_rxdata_ch0[5] ff_rx_d_0_6 ff_rxdata_ch0[6] ff_rx_d_0_7 ff_rxdata_ch0[7] ff_rx_d_0_8 ff_rx_k_cntrl_ch0[0] nc ff_rxdata_ch0[8] ff_rx_d_0_9 ff_disp_err_ch0[0] ff_rxstatus0_ch0[0] ff_disp_e rr_ch0[0] nc ff_rxdata_ch0[9] ff_rx_d_0_10 ff_cv_ch0[0] ] 3 ff_rxstatus1_ch0[0] ff_cv_ch0[0] ] 3 nc ff_rx_d_0_11 nc ff_rxstatus2_ch0[0] ff_rx_even_ch0[0] ] 4 nc ff_rx_d_0_12 ff_rxdata_ch0[8] ff_rxdata_ch0[10] ff_rx_d_0_13 ff_rxdata_ch0[9] ff_rxdata_ch0[11] ff_rx_d_0_14 ff_rxdata_ch0[10] ff_rxdata_ch0[12] ff_rx_d_0_15 ff_rxdata_ch0[11] ff_rxdata_ch0[13] ff_rx_d_0_16 ff_rxdata_ch0[12] ff_rxdata_ch0[14] ff_rx_d_0_17 ff_rxdata_ch0[13] ff_rxdata_ch0[15] 8-7 lattice semiconductor latticeecp 2m serdes/pcs usage guide control each mode has its own set of control signals which allows direct control of various pcs features from the fpga logic. in general, each of these control inputs duplicate the effect of writing to a corresponding control register bit or bits. the isplever ? design tools give the user the option to bring these ports out to the fpga interface. status each mode has its own set of status or alarm signals that can be monitored by the fpga logic. in general, each of these status outputs correspo nd to a specific status regi ster bit or bits. the isplever design tools gi ve the user the option to bring these port out to the pcs fpga interface. refer to the mode specific control/status signals section for detailed information about control and status signals. sci (serdes client interface) bus the serdes client interface (sci) is a soft ip that allow the serdes/pcs quad block to be controlled by regis- ters as oppose to the configuration memory cells. it is a simple register configuration interface. using this technical note the isplever design tools from lattice support all modes of the pcs. mo st modes are dedicate d to applications for a specific industry standard data protocol. other mode s are more general purpose modes which allow a user to define their own custom application settings. isplever design tools allow the user to define the mode for each quad in their design. this document describes operation of the serdes and pcs for all modes supported by isp- lever. if you are using lattice diamond? design software, see appendix e. this document provides a thorough description of the complete functionality of the embedded serdes and asso- ciated pcs logic. electrical and timing characteri stics of the embedded serdes are provided in the latticeecp2/m family data sheet . operation of the pcs logic is provided in the pcs section. a table of all status and control registers associated with the serdes and pc s logic which can be accessed via the sci bus is pro- vided in the memory map section. package pinout information is provided in the architecture section of the latticeecp2/m family data sheet . serdes/pcs the quad contains four channels with both rx and tx circui ts, and an auxiliary channel that contains the tx pll. the reference clock to the tx pll can be provided either by the primary differential reference clock pins or by the fpga core. the quad serdes/pcs macro performs the seria lization and de-serialization function for four lanes ff_rx_d_0_18 ff_rxdata_ch0[14] ff_rxdata_ch0[16] ff_rx_d_0_19 ff_rxdata_ch0[15] ff_rxdata_ch0[17] ff_rx_d_0_20 ff_rx_k_cntrl_ch0[1] nc ff_rxdata_ch0[18] ff_rx_d_0_21 ff_disp_err_ch0[ 1] ff_rxstatus0_ch0[1] ff_disp _err_ch0[1] nc ff_rxdata_ch0[19] ff_rx_d_0_22 ff_cv_ch0[1] ] 3 ff_rxstatus1_ch0[1] ff_cv_ch0[1] ] 3 nc ff_rx_d_0_23 nc ff_rxstatus2_ch0[1] ff_rx_even_ch0[1] ] 4 nc 1. the force_disp signal will force the disparity for the associated data word on bits [7:0] to the column selected by the tx_di sp_sel signal. if disp_sel is a one, the 10-bit code is taken from the 'current rd+' column (positive disparity). if the tx_di sp_sel is a zero, t he 10-bit code is taken from the 'current rd-' (negative disparity) column. 2. the auto-negotiation state machine generates the signal xmit. it is us ed to interact with the gige idle state machine in the hard logic. 3. when there is a code violation, the packet pcs 8b10b decoder will replace the output from the decoder with hex ee and k asser ted (k=1 and d=ee is not part of the 8b10b coding space). 4. rx_even is a signal generated by the gige link state machine fo r the use of the gige auto-negotiation and receive state machi nes (which is part of the ip core). 5. ff_tx_d_0_0: fpga fabric transmit data bus channel 0 bit 0. table 8-3. data bus usage by mode (continued) data bus pcs cell name 5 g8b10b cpri pci express gige 8bser 10bser sdi 8-8 lattice semiconductor latticeecp 2m serdes/pcs usage guide of data. in addition, the pll within the serdes/pcs block provides the system clock for the fpga logic. the quad also supports both full-data-rate and half-data-rate modes of operation on each tx and rx circuit independently. the block level diagram is shown in figure 8-4. figure 8-4. serdes_pcs block signal interface ff_rxfullclk_ch[3:0] ff_rxhalfclk_ch[3:0] ff_rxqtrclk_ch[3:0] ff_txfullclk ff_txhalfclk ff_txqtrclk ff_rxdata_ch0[23:0] ff_rxdata_ch1[23:0] ff_rxdata_ch2[23:0] ff_rxdata_ch3[23:0] ff_txdata_ch0[23:0] ff_txdata_ch1[23:0] ff_txdata_ch2[23:0] ff_txdata_ch3[23:0] core_txrefclk core_rxrefclk ff_ebrd_clk_[3:0] ff_rxiclk_ch[3:0] ff_txiclk_ch[3:0] ffs_ls_sync_status_ch[3:0] ffs_cc_undrerun_ch[3:0] ffs_cc_overrun_ch[3:0] ffs_pcie_done_ch[3:0] ffs_pcie_con_ch[3:0] ffs_rlos_lo_ch[3:0] oob_out[3:0] ffs_rxfbfifo_error_ch[3:0] ffs_txfbfifo_error_ch[3:0] ffs_rlol_ch[3:0] ffs_plol refck2core primary i/o test/ validate serdes client interface control signals from fpga clocks to fpga rx data & in-band status tx data & in-band status clocks from fpga status signals to fpga cin[11:0] cout[19:0] hdinp[3:0] hdinn[3:0] refclkp refclkn hdoutp[3:0] hdoutn[3:0] cyawstn scienaux sciench[3:0] sciwritedata[7:0] sciwstn sciselaux sciselch[3:0] sciaddress[5:0] scird scireaddata[7:0] sciinterrupt ffc_ei_en_ch[3:0] ffc_pcie_det_en_ch[3:0] ffc_pcie_ct_ch[3:0] ffc_fb_loopback_ch[3:0] ffc_sb_pfifo_lp_ch[3:0] ffc_sb_inv_rx_ch[3:0] ffc_lane_rx_rst_ch[3:0] ffc_lane_tx_rst_ch[3:0] ffc_rrst_ch[3:0] ffc_trst ffc_quad_rst ffc_macro_rst ffc_signal_detect_ch[3:0] ffc_enable_cgalign_ch[3:0] ffc_txpwdnb_ch[3:0] ffc_rxpwdnb_ch[3:0] ffc_pfifo_clr[3:0] serdes/pcs quad 8-9 lattice semiconductor latticeecp 2m serdes/pcs usage guide i/o definitions table 8-4 lists all default and optional input and outputs to/from a pcs quad. users can choose optional ports for a pcs quad using the ipexpress? gui. table 8-4. serdes_pcs i/o descriptions signal name i/o type description default/ optional primary i/o, serdes quad hdinp0 i channel high-speed cml input, positive, channel 0 d hdinn0 i channel high-speed cml input, negative, channel 0 d hdinp1 i channel high-speed cml input, positive, channel 1 d hdinn1 i channel high-speed cml input, negative, channel 1 d hdinp2 i channel high-speed cml input, positive, channel 2 d hdinn2 i channel high-speed cml input, negative, channel 2 d hdinp3 i channel high-speed cml input, positive, channel 3 d hdinn3 i channel high-speed cml input, negative, channel 3 d hdoutp0 o channel high-speed cml output, positive, channel 0 d hdoutn0 o channel high-speed cml output, negative, channel 0 d hdoutp1 o channel high-speed cml output, positive, channel 1 d hdoutn1 o channel high-speed cml output, negative, channel 1 d hdoutp2 o channel high-speed cml output, positive, channel 2 d hdoutn2 o channel high-speed cml output, negative, channel 2 d hdoutp3 o channel high-speed cml output, positive, channel 3 d hdoutn3 o channel high-speed cml output, negative, channel 3 d refclkp i quad reference clock input, positive, dedicated cml input d refclkn i quad reference clock inpu t, negative, dedicated cml input d receive / transmit data bus (see table for detailed data bus usage) ff_rxdata_ch0[23:0] o channel data sig nals for the channel 0 receive path d ff_rxdata_ch1[23:0] o channel data sig nals for the channel 1 receive path d ff_rxdata_ch2[23:0] o channel data sig nals for the channel 2 receive path d ff_rxdata_ch3[23:0] o channel data sig nals for the channel 3 receive path d ff_txdata_ch0[ 23:0] i channel data signals for the channel 0 transmit path d ff_txdata_ch1[ 23:0] i channel data signals for the channel 1 transmit path d ff_txdata_ch2[ 23:0] i channel data signals for the channel 2 transmit path d ff_txdata_ch3[ 23:0] i channel data signals for the channel 3 transmit path d control signals ffc_sb_inv_rx_ch[3:0] i channel control the inversion of received data. 1 = invert the data 0 = do not invert the data o ffc_enable_cgalign_ch[3:0] 4 i channel control comma aligner. 1 = enable comma aligner 0 = lock comma aligner at current position. o ffc_signal_detect_ch[3:0] 4 i channel control link state machine 1 = enable link state machine 0 = disable link state machine o ffc_fb_loopback_ch[3:0] i channel fpga bridge loopback. 1 = enable loopback from rx to tx 0 = normal data operation o 8-10 lattice semiconductor latticeecp 2m serdes/pcs usage guide ffc_sb_pfifo_lp_ch[3:0] i channel serdes bridge parallel loopback 1 = enable loopback from rx to tx, 0 = normal data operation o ffc_pfifo_clr_ch[3:0] i channel serdes bridge parallel loopback fifo clear 1 = reset loopback fifo 0 = normal loopback operation d rx_sdi_en i channel these signals are used in bscan mode only. o tx_sdi_en i quad reset signals ffc_lane_rx_rst_ch[3:0] i channel active high, asynchronous input. resets individual rx chan- nel logic only in pcs. d ffc_lane_rx_tst_ch[3:0] i channel active high, asynchronous input. resets individual tx chan- nel logic only in pcs. d ffc_rrst_ch[3:0] i channel active high. resets selected digital logic in the serdes receive channel d ffc_trst i quad active high, resets selected digital logic in all serdes transmit channels. d ffc_quad_rst i quad active high, asynchronous input. resets all serdes chan- nels including the auxiliary channel and pcs. d ffc_macro_rst i quad active high, asynchronous input to serdes quad. resets all serdes channels including the aux channel but not pcs logic. gated with software register bit fpga_reset_enable. by defaul t fpga_reset_enable is ?1?. d ffc_txpwdnb_ch[3:0] i channel active low transmit channel power down. 0 = transmit chan- nel power down. d ffc_rxpwdnb_ch[3:0] i channel active low receive channel power down. 0 = receive chan- nel power down. d status signals ffs_rlos_lo_ch[3:0] o channel loss of signal detection for each channel. register bits rlos_hset[2:0] are used to set the threshold. low threshold is not user accessible. 1 = loss of signal 0 = signal detected d ffs_ls_sync_status_ch[3:0] o channel 1 = lane is synchronous to commas. 0 = lane has not found comma. d ffs_cc_underrun_ch[3:0] 6 o channel 1 = receive clock compensator fifo underrun error, 0 = no ffifo errors. o ffs_cc_overrun_ch[3:0] 6 o channel 1 = receive clock compensator fifo overrun error 0 = no fifo errors. o ffs_rxfbfifo_error_ch[3:0] o channel 1 = receive fpga bridge fifo error 0 = no fifo errors d ffs_txfbfifo_error_ch[3:0] o channel 1 = transmit fpga bridge fifo error 0 = no fifo errors. d ffs_rlol_ch[3:0] o channel 1 = receive cdr loss of lock 0 = lock maintained d ffs_plol o quad 1 = transmit pll loss of lock 0 = lock maintained d oob_out_ch[3:0] 3 o channel single ended outputs to video serdes (in fpga). d refck2core o quad reference clock to fpga core. o table 8-4. serdes_pcs i/o descriptions (continued) signal name i/o type description default/ optional 8-11 lattice semiconductor latticeecp 2m serdes/pcs usage guide clock signals to fpga ff_rxfullclk_ch[3:0] o channel receive channel recovered clock. in user mode, the source is always the channel?s recovered clock. for standards such as gbe, 10 gbe that support clock compensation, the source is the respective transmit channel?s system clock. for pcs bypass modes, it is also the tx system clock, thus requiring raw mode to actually be done using either 8b10b mode with the 8b10b decoder disabled (10-bit or 20-bit data path). d ff_rxhalfclk_ch[3:0] o channel receive channel recovered half clock. in 2:1 gearing mode, it is a divide-by-2 output. d ff_rxqtrclk_ch[3:0] o channel receive channel recovered quarter clock. available for fur- ther 2:1 gearing. o ff_txfullclk o quad tx pll full rate clock. d ff_txhalfclk o quad tx pll half clock. d ff_txqtrclk o quad tx pll quarter clock o clock signals from fpga core_rxrefclk i quad rx reference clock from fpga logic, for cdr pll d core_txrefclk i quad tx reference clock from fpga logic, for tx serdes pll d ff_ebrd_clk_[3:0] i channel receive channel clock input from fpga for ctc fifo (elastic buffer) read d ff_rxiclk_ch[3:0] i channel receive channel clock input from fpga. used to clock the rx fpga interface fifo with a clock synchronous to the reference and/or receive reference clock. d ff_txiclk_ch[3:0] i channel transmit channel clock input from fpga.per channel trans- mit clock inputs from fpga. used to clock the tx fpga. interface fifo with clock synchronous to the reference clock. also used to clock the rx fpga interface fifo with a clock synchronous to the reference clock when ctc is used. d serdes client interface (sci) scienaux i r 1: sciwdata is written to the quad control registers 0: memory data is written to the quad control registers o scien_ch[3:0] i r 1: sciwdata is written to the channel control registers 0: memory data is written to the channel control registers o sciselaux i r 1: select quad registers o scisel_ch[3:0] i r 1: select channel registers o sciaddress[5:0] i r address bus input o scireaddata[7:0] o r read data output o sciwritedata[7:0] i r write data input o scird i r 1: read data select 0: read data not selected o sciwstn i r write strobe o sciinterrupt o r interrupt output o cyawstn 5 ir 1: copy all memory cells to registers if sciwstn = 0 0: default o serdes characterization / test bus cin[11:0] i r characterization test bus logic data input d table 8-4. serdes_pcs i/o descriptions (continued) signal name i/o type description default/ optional 8-12 lattice semiconductor latticeecp 2m serdes/pcs usage guide serdes/pcs functional description devices in the latticeecp2m family have from one to four quads of embedded serdes/pcs logic. each quad, in turn, supports four independent full-duplex data channels. a single channel can support a data link and each quad can support up to four such channels. note that mode selection is done on a per quad basis. for example, the selection of gigabit ethernet mode for a quad dedicates all four channels in that quad to gigabit ethernet mode. the embedded serdes cdr plls and tx plls support data rates which cover a wide range of industry stan- dard protocols. figure describes the major blocks and sub-blocks in a serdes/pcs channel. ? serdes ? equalizer ? cdr (clock and data recovery) ? deserializer ? preemphasis ? serializer ? serial loopback ? serdes bridge (sb) ? inverter: inverts receive data. required by pci express ? serdes bridge parallel loopback ?pcs core ? word alignment ? 8b10b decoder ? 8b10b encoder ? link state machine ? elastic buffer (ctc) ? fpga bridge (fb) ? down-sample fifo ? up-sample fifo ? pcs parallel loopback serdes equalizer as the data rate of digital transmission advances over gbps, frequency-dependent attenuation results in severe intersymbol interference in the received signal and makes it mandatory to use equalizer in the data transceiver to recover data correctly. three pole positions are provided: low, medium and high frequency range. cout[19:0]] o r charact erization test bus logic data output d 1. during configuration, both hdoutp and hdoutn are pulled high to vccob. 2. the generic 8b10b pcs module includes four pci control and stat us signals as options. if not used, the control signals may b e tied to gnd and the status signals may be left float. 3. the only way to get a signal out without using the cdr is to use the oob_out signal. this signal is available in sdi mode on ly. 4. these signals appear in the pcs port list when the external link state machine is selected. refer to figure 8-28. 5. for factory use only. 6. these signals are pulses. in order to properly monitor these status signals, they must be latched. table 8-4. serdes_pcs i/o descriptions (continued) signal name i/o type description default/ optional 8-13 lattice semiconductor latticeecp 2m serdes/pcs usage guide pre-emphasis pre-emphasis refers to a system process designed to increase the magnitude of some frequencies with respect to the magnitude of other frequencies. the goal is to impr ove the overall signal-to-noise ratio by minimizing the adverse effects of such phenomena as attenuation differences or saturation of recording media in subsequent parts of the system. user can select up to 80% of pre-emphasis. reference clock usage one reference clock (refclk) is supported in the latticee cp2m family. the tx pll and the four rx plls all run at the same frequency, which is a multiple of the reference clock frequency. the tx serializer in each channel can be independently programmed to run at this rate (full-data-rate mode) or half of this rate (half-data-rate mode). similarly, the rx deserializer in each channel can be independently programmed to run at this rate (full-data-rate mode) or half of this rate (half-data-rate mode). if all tx and rx are programmed in the same mode (normally this will be full-rate) then all four channels in the quad will run at the same freq uency, both tx and rx. the transmit pll in the serdes is able to lock to either an external reference clock from the pins, or a reference clock provided from the fpga core (cor e_txrefclk). the receive cdrs in the serdes is able to lock to either an external reference clock from the pins, or a reference clock provided by the fpga core (core_rxrefclk). figure 8-5. block diagram, reference clock usage reference clock sources refclkp, refclkn dedicated cml input. this is the first choice unless different clock sources for rx and tx are used. the clock signal may be cml, lvds or l vpecl. refer to tn1114, electrical recommendations for lattice serdes , for example interface circuits. core_rxrefclk, core_txrefclk fpga core data from pcs cdr0/ rx pll hdin0 des0 cdr1/ rx pll hdin1 des1 cdr2/ rx pll hdin2 des2 cdr3/ rx pll hdin3 des3 refclkp refclkn tx pll hdout0 ser0 1/2 hdout3 ser3 1/2 hdout2 ser2 1/2 hdout1 ser1 1/2 data to pcs 1/2 1/2 1/2 1/2 core_rxrefclk core_txrefclk refck2core 8-14 lattice semiconductor latticeecp 2m serdes/pcs usage guide reference clock from fpga logic. the primary clock pad (pclk) should be used as the clock input pin to the fpga. the clock signal may be cml, lvds, lvpecl or single-ended. fpga pll when an fpga pll is used as the reference clock, the reference clock to pll should be assigned to a dedicated pll input pad. the fpga pll output jitter may not meet sy stem specifications at higher data rates. use of an fpga pll is not recommended in jitter-sensitive applications. full-data-rate and half-data-rate each tx serializer and rx deserializer can be split into full-data-rate and half-data-rate, allowing two different data rates in each direction and in each channel. the channel based protocol mode must be selected to use this dual rate feature. example: 1. in the quad tab window of ipexpress (figure 8-22), g8b10b mode, channel based protocol mode, channel 0 (full rate) and channel 1 (half rate) are selected. 2. in the reference clock (cm) window (figure 8-24), under the full rate channel column, enter the fol- lowing: ? serial bit clock rate: 2.5 ghz ? reference clock multiplier: 10x ? leave the other three entries 3. the half rate channel column will display calculated values for half rate: full clock, half clock and quarter clock usage in most cases, txfullclk is used for ff_rxiclk_chx, ff_tx iclk_chx, ff_ebrd_clk_x as illustrated in figure 8-32. the ipexpress gui automatically calculates the fpga in terface clock frequency when reference clock multiplier and fpga interface data bus width is selected. table 8-5 illustrates clock usage examples in all possible combinations of the refclk_multiplier mo des and 8-bit or 16-bit interface data bus widths. full rate channel h alf rate channel serial bit clock rate 2.5 ghz 1.25 ghz reference clock multiplier 10x 5x calculated reference clock rate 250 mhz 250 mhz fpga interface data bus width 8 8 calculated fpga interface clock rate 250 mhz 125 mhz 8-15 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-5. clock usage example ? g8b10b mode, refclk = 120mhz the vco in the full data rate ch annel is the same as the bit clock. in half data rate channel, the bit clock is half of the vco. loss of signal (los) each channel contains a programmable loss-of-signal detector as shown in figure 8-6. the loss-of-signal thresh- old depends on the value of the programmable current source. the current source value is chosen using the rlos_hset[2:0] control bits. figure 8-6. loss-of signal detector loss of lock both the transmit pll and th e individual channel cdrs have digital counte r-based, loss-of-lock detectors. if the transmit pll loses lock, the loss-of-lock for the pll is asserted and remains asserted until the pll reacquires lock. reference clock multiplier 10xh 10x 20xh 20x bit rate 600 mbps 1.2 gbps 1.2 gbps 2.4 gbps 8-bit interface example rxfullclk 1 60 120 120 240 rxhalfclk 30 60 60 120 txfullclk 120 120 240 240 txhalfclk 60 60 120 120 txqtrclk 30 30 60 60 16-bit interface example rxfullclk 60 120 120 240 rxhalfclk 1 30 60 60 120 txfullclk 120 120 240 240 txhalfclk 60 60 120 120 txqtrclk 30 2, 3 30 60 60 1. these recovered clocks are used as the source of rxiclk in ctc byp ass mode. see figures 8-34 and 8-36. 2. the clocks in the shaded cells are used as the fpga interface clocks in each mode. 3. when this mode is selected, the 'pll quarter clock' mu st be checked in the optional port tab window of the configuration gui (see figure 8-28). r2 + - rlos_lo reference voltage on this node is derived from vcm note: rlos_lset[2:0] control bits and associated status bits are internal use only. current source value depends on rlos_hset[2:0] input signal 8-16 lattice semiconductor latticeecp 2m serdes/pcs usage guide if a cdr loses lock, the loss-of-lock for that channel is asse rted and locking to the reference clock retrains the vco in the cdr. when this is achieved, loss -of-lock for that channel is de-asserted and the cdr is switched back over to lock to the incoming data. the cdr will either remain locked to the data, or will go back out of lock again in which case the re-trainin g cycle will repeat. tx lane-to-lane skew a control bit, sync_toggle, has been added to reset all the active tx channels to start serialization with bit0. most multi-channel protocol standards have requirements to ensure that the tx lane-to-lane skew is within a certain specification. this is to ensure that most of the rx de-skew (multi-channel alignment, which is not supported in hard pcs by lattice ecp2m) is for channel (trace) de-skewing. the reset to the tx serializers is generated either by toggling the sync_toggle control bit or by a transition in pll loss of lock. the reset is applied to all active tx serializers. if both these source signals are level, then the tx seri- alizers are operating normally. pcs functional setup the latticeecp2m pcs can be configur ed for use in various applicatio ns. setup is chos en with the isplever ? ipexpress module generation tool which allows the user to select the mode and feature options for the pcs. option selections are saved in an auto-configuration file which is subsequently used by the isplever bitstream generator to write the user selections into the bitstream. to change pcs option selections it is recommended that the user re- run ipexpress to regenerate a pcs module and create a new auto-configuration file. some options can be changed by manually editing the auto-configuration file before running the bitstream generator. after configuration, pcs options can be changed dynamically by writing to pcs registers via the optional serdes client interface (sci) bus. the serdes client interface is soft ip that allows the serdes/pcs quad to be con- trolled by registers as opposed to configuration memory cells. a table of control and status registers accessible through the sci is provided in the memory map section of this document. auto-configuration file initial register setup for each pcs mode can be performed by using the autoconfiguration feature in isplever. the module generator provides an auto-configuration file which contains the quad and channel register settings for the chosen mode. this file can be referred to for front-end simulation and also can be integrated into the bitstream. when an auto-configuration file is inte grated into the bitstream all the quad and channel re gisters will be set to val- ues defined in the auto-configuration file during configur ation. the sci (serdes client interface) is therefore not needed if all quads are to be set via auto-configuration files. however, the sci must be included in a design if the user needs to change control registers or monitor status registers during operation. transmit data the pcs quad transmit data path consists of 8b10b encoder and serializer per channel. 8b10b encoder this module implements an 8b10b encoder as de scribed within the ieee 802. 3ae-2002 1000base-x specifica- tion. the encoder performs the 8-bit to 10-bit code conversion as described in the specification, along with main- taining the running disparity rules as specified. the 8b 10b encoder can be bypassed on a per channel basis by setting the attribute chx_8b10b to ?byp ass? where x is the channel number. serializer the 8b10b encoded data undergoes parallel to serial conversion and is transmitted off chip via the embedded serdes. receive data the pcs quad receive data path consists of the following sub-blocks per channel: deserializer, word aligner, 8b10b decoder, optional link state machine, and opti onal receive clock tolerance compensation (ctc) fifo. deserializer data is brought on-chip to the embedded serdes where it goes from serial to parallel. 8-17 lattice semiconductor latticeecp 2m serdes/pcs usage guide word alignment (byte boundary detect) this module performs the comma codeword detection and alignment operation. the comma character is used by the receive logic to perform 10-bit word alignment upon the incoming data stream. the word aligner can be bypassed on a per channel basis by setting attribute chx_co mma_align to ?bypass? where x is the channel number. the comma description can be found in section 36.2.4.9 of the 80 2.3.2002 1000base-x specification as well as section 48.2.6.3, figure 48-7 of the 10gbase-x specification. a number of programmable options are supported within the word alignment module: ? software enable control (in user configured - uc mode). note: uc_mode refers to 8-bit serdes on ly, 10-bit serdes only, sd-sdi, hd-sdi. ? ability to set two programmable word a lignment characters (typically one fo r positive and one fo r negative dispar- ity) and a programmable per bit mask register for alignment compare. alignment characters and the mask regis- ter is set on a per quad basis. for many protocols, the word alignment charac ters can be set to ?xxx0000011? (jhgfiedcba bits for positive running disparity comma character matching code groups k28.1, k28.5, and k28.7) and ?xxx1111100? (jhgfiedcba bits for negative runn ing disparity comma character matching code groups k28.1, k28.5, and k28.7). however the user can define any bit pattern up to 10 bits long. ? the first alignment character is defined by the 10-bit value assigned to attribute comma_a. this value applies to all channels in a pcs quad. ? the second alignment character is defined by the 10-bit value assigned to attribute comma_b. this value applies to all channels in a pcs quad. ? the mask register defines which word alignment bits to compare (a ?1? in a bit of the mask register means check the corresponding bit in the word ali gnment character register). the mask re gisters defined by the 10-bit value assigned to attribute comma_m. this valu e applies to all cha nnels in a pcs quad. when attribute chx_comma_al ign is set to ?auto?, one of the protoc ol based link state machines will control word alignment. for more information on the operation of the protocol based link state machines, see the protocol specific link state machine description below. 8b10b decoder the 8b10b decoder implements an 8b10b deco der operation as described with the ieee 802.3-2002 specification. the decoder performs the 10-bit to 8-bit code conversion along with verifying the running disparity. the 8b10b decoder can be bypassed on a per ch annel basis by setting attribute chx _8b10b to ?bypass? where x is the channel number. when a code violation is detected, the ff_rxdata receive data is set to 0xee with ff_rx_k_cntrl_ch set to ?1?. protocol specific link state machine the pcs implements link state machines for various protocols that are used in various quad modes. when a protocol specific link state machine is selected, that channel?s link state machine must be enabled by setting the protocol ch(0-3)_comma_align to ?auto?. selection of the specific link state machine that is enabled in each mode is described below and summarized in figure 8-7. the link state machine for gigabit ethernet is selected when attribute protocol is ?gige?. link synchroniza- tion is achieved after the successful detection and alignment of the required number of consecutive aligned code words. the gigabit ethernet link synchronization state machine implements the synchronization state diagram shown in figure 36-9 of the 802. 3- 2002 1000base-x specification. in 'g8b10b' and '10-bit serdes only' protocols, the gigabit ethernet link state machine is used when comma_align is set to 'auto'. 8-18 lattice semiconductor latticeecp 2m serdes/pcs usage guide external link state machine option when attribute chx_comma_align is set to ?dynamic?, the protocol specific link state machines are bypassed. when ffc_enable_cgalign_ch(0 -3) is high, the word aligner will lock alignment and stay locked. it will stop comparing incoming data to the us er-defined word alignment characters and will maintain current alignment on the first successful compare to either the comma_a or comma_b. when word_align_en_ch(0-3)_c is pulsed low, the word aligner will re-lock on the next match to one of the user-defined word alignm ent characters. if desired, ffc_enable_cgalign_ch(0-3) can be controlled by a link state machine implemented externally to the pcs quad to allow a change in word alignment only under specific conditions. figure 8-7 illustrates the link state machine options. figure 8-7. pcs word aligner and link state machine options table 8-6. link state machine and word aligner selection when a link state machine is selected and enabled, for a particular channel, that channel?s ffs_ls_sync_status_ch(0-3) status signal will go high upon successful link synchronization. idle insert for gigabit ethernet mode generic 8b10b mode also has the option to select the link state machine for word alignment. the pcs set to gigabit ethernet mode provides for insertion of /i2/ symbols into the receive data stream for auto-negotiation. giga- bit ethernet auto-negotiation is performed in soft logic. this function inserts a sequence of 8 /i2/ ordered sets every 2048 clock cycles. /i2/ insertion is controlled by the ff_xmit_ch(0-3) input to the pcs which is driven from the auto- negotiation soft logic. the signal ff_rx_even_ch(0-3)[0] from the pcs to the auto-negotiation soft logic is also pro- vided. figure 8-8 shows one channel (channel 0 in this example) of receive logic when the pcs is set to gigabit ethernet mode showing these control/status signals. comma align mo de description auto wa enabled, lsm enabled (gbe lsm: default). dynamic wa enabled, lsm disabled. the cg_align and sig_detec t signals are set to 0 so that the potential external lsm to control both signals. the external link state machine option in the optional port tab of the gui must be also selected. bypass wa bypassed, lsm disabled. users may develop word aligner in the fpga core and provide their own cg_align and sig_detect signals to the logic. en internal link state machine 0 (internal) 1 (external) lsm_sel ch_03[7] word aligner 1:8/1:10 deserializer 8b10b decoder ffc_signal_detect_ch[3:0] (from fpga fabric) internal lsm enable signal_detect ch_03[6] ffc_enable_cgalign_ch[3:0] (from fpga fabric) ch_00[7] enable_cg_align 8-19 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-8. pcs receive path for giga bit ethernet mode (channel 0 example) clock tolerance compensation the clock tolerance compensation module performs clock rate adjustment between the recovered receive clocks and the locked reference clock. clock compensation is performed by inserting or deleting bytes at pre-defined posi- tions, without causing loss of packet data. a 16-byte elasticity fifo is used to transfer data between the two clock domains and will accommodate clock differences of up to the specified ppm tole rance for the latticeecp2m serdes (see dc and switching characteristics section of the latticeecp2/m family data sheet ). a channel has the clock tolerance compensation block enable when that channel?s attribute chx_ctc_byp is set to ?normal?. the ctc is bypassed when that channel?s attribute chx_ct c_byp is set to ?bypass?. a diagram illustrating 1 byte deletion is shown in figure 8-9: figure 8-9. clock tolerance compensation 1 byte deletion example a diagram illustrating 1 byte inse rtion is shown in figure 8-10: pcs channel 0 (gigabit ethernet mode) clock tolerance comp (ctc) ff_rxdata_ch0[7:0] ff_disp_err_ch0[0] ff_cv_ch0[0] word align 8b10b decode de- serial izer hdinp0 hdinn0 ff_rx_k_cntrl_ch0[0] to/from fpga logic from external i/o pads link state machine ffs_ls_sync_status_ch0 gigabit ethernet /i2/ insert ff_xmit_ch0[0] ff_rx_even_ch0[0] ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk = skip s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i i sk i d s e i i i d i d s delete if ctc fifo almost full & sk = cc_match4 ff_rxiclk_ch0 or ff_ebrdclk_ch0 8-20 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-10. clock tolerance compensation 1 byte insertion example a diagram illustrating 2 byte dele tion is shown in figure 8-11: figure 8-11. clock tolerance compensation 2 byte deletion example a diagram illustrating 2 byte inse rtion is shown in figure 8-12: figure 8-12. clock tolerance compensation 2 byte insertion example a diagram illustrating 4 byte dele tion is shown in figure 8-13: ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk = skip s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i i sk i d s e i sk sk s i insert if ctc fifo almost empty & sk = cc_match4 ff_rxiclk_ch0 or ff_ebrdclk_ch0 i i ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk1 = cc_match3 sk2 = cc_match4 s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i i sk1 i d s e i i i d i d s ff_rxiclk_ch0 or ff_ebrdclk_ch0 sk2 i i d d d d d ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk1 = cc_match3 sk2 = cc_match4 s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i i sk1 i d s e i i i i d s ff_rxiclk_ch0 or ff_ebrdclk_ch0 sk2 i i sk1 sk2 sk1 sk2 d d 8-21 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-13. clock tolerance compensation 4 byte deletion example a diagram illustrating 4 byte inse rtion is shown in figure 8-14: figure 8-14. clock tolerance compensation 4 byte insertion example clock compensation values are set on a quad basis. the ctc can be bypassed on a per channel basis by setting attribute chx_ctc_byp to ?bypass? where x is the channel number. setting chx_ctc_byp to ?normal? means the ctc is active. in the ispl ever module generator, defi ning a channel as ?singl e? creates an auto-con- figuration file which enables ctc. defining a channel as ?mca group1? or ?mca group 2? creates an auto-config- uration file which bypasses ctc. when the ctc is used, the following settings for clock compensation must be set as appropriate for the intended application: ? set the insertion/deletion pattern length using the cc_matchmode attribute. this sets the number of skip bytes the ctc compares to before performing an insertion or deletion. values for cc_matchmode are ?match_4? (1 byte insertion/deletion), ?match_3_4? (2 bytes insertion/deletion), and ?match_1_2_3_4? (4 bytes insertion/deletion) to 1. the minimum inter-packet gap must also be set as appropriate for the targeted application. the inter-packet gap is set by assigning values to attribute cc_min_ ipg. allowed values for cc_min_ipg are ?0?, ?1?, ?2?, and ?3?. the minimum allowed inter-packet gap after skip character deletion is per- formed based on these attribute settings is described in table 8-7 below. ? the skip byte or ordered set must be set corresponding to the cc_matchmode chosen. for 4 byte inser- tion/deletion (cc_matchmode = ?match_1_2_3_4?), the first byte must be assigned to attribute match_1, the second byte must be assigned to attribute match_2, the third byte must be assigned to attribute match_3, and the fourth byte must be assigned to attribute match_4. values assigned are 10 bit binary values. for exam- ple, if a 4 byte skip ordered set is /k28.5/d21.4/d21.5/d21.5, then ?match_1? should be ?0110111100?, ?match_2?, = ?0010010101?, and ?match_3? = ?match_4? = ?0010110101?. for 2 byte insertion/deletion (cc_matchmode = ?match_3_4?), the first byte must be assigned to attribute match_3, and the second byte must be assigned to attribute match_4. for 1 byte insertion/deletion ( cc_matchmode = ?match_4?), the skip byte must be assigned to attribute match_4. ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk1 = cc_match1 sk2 = cc_match2 sk3 = cc_match3 sk4 = cc_match4 s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i e i i ff_rxiclk_ch0 or ff_ebrdclk_ch0 i i d s d d s i d d d d d sk1 i i sk2 sk3 i sk4 d d d d ff_rxiclk_ch0 or ff_ebrdclk_ch0 before ctc ff_rxdata_ch0[7:0] e = end of packet i = logical idle sk1 = cc_match1 sk2 = cc_match2 sk3 = cc_match3 sk4 = cc_match4 s = start of packet d = data after ctc ff_rxdata_ch0[7:0] e i i e i i ff_rxiclk_ch0 or ff_ebrdclk_ch0 i i d s s i d sk1 i i sk2 sk3 sk4 sk1 sk2 sk3 sk4 sk1 sk2 sk3 sk4 d d i 8-22 lattice semiconductor latticeecp 2m serdes/pcs usage guide ? the clock compensation fifo high water and low water marks must be set to appropriate values for the targeted protocol. values can range from 0 to 15 although the high water mark must be set to a value higher than or equal to the low water mark. the high water mark is set by assigning a value to attribute cchmark. allowed values for cchmark are hex values ranging from ?0? to ?f?. the low water mark is set by assigning a value to attribute cclmark. allowed values for cclmark are hex values ranging from ?0? to ?f?. ? clock compensation fifo overrun can be monitored on a per channel basis on the pcs/fpga interface port labeled ffs_cc_overrun_ch(0-3) if ?error status ports? is selected when generating the pcs block with the isp- lever module generator. ? clock compensation fifo underrun can be monitored on a per channel basis on the pcs/fpga interface port labeled ffs_cc_underrun_ch(0-3) if ?error status ports? is selected when generating the pcs block with the isp- lever module generator. calculating minimum inter-packet gap table 8-7 shows the relationship between the user-defined values for inter-packet gap (defined by the cc_min_ipg attribute), and the guaranteed minimum number of bytes between packets after a skip character deletion from the pcs. the table shows the inter-packet gap as a multiplier number. the minimum number of bytes between packets is equal to the number of bytes per insertion/deletion times the multiplier number shown in the table. for example, if the number of bytes per insertion/deletion is 4 (cc_matchmode is set to ?match_1_2_3_4?), and the minimum inter-packet gap attribute c_min_ipg is set to ?2?, then the minimum inter- packet gap is equal to 4 (cc_matchmode = ?match_1_2_3_4?) times 3 (table 8-7 with cc_min_ipg = ?2?) or 12 bytes. the pcs will not perform a skip character deleti on until the minimum number of inter-packet bytes have passed through the ctc. table 8-7. minimum inter-packet gap multiplier clock domains figure 8-15 shows the clock domains for both transmit a nd receive directions for a single channel inside the pcs for modes which utilize the clock tole rance compensation (ctc) block. on the transmit side, a clock domain transfer from the ff_txiclk_ch input at the fpga interface to the locked refer- ence clock occurs in the fpga transmit interface fifo. the fpga transmit interface fifo is intended to adjust for phase differences between two clocks which are of the same frequency only. these fifos (one per channel) cannot compensate for frequency variations. on the receive side, a clock domain transfer occurs from the channel recovered clocks to the locked reference clock at the clock tolerance compensator (ctc) block. the ctc can adjust for frequency differences between the recovered receive clock and the reference clock up to the maximum phase difference specification for the latticeecp2m. downstream from the ctc, another clock interface occurs between the locked reference clock and the ff_rxiclk_ch at the fpga receive interface fifo. the fpga receive interface fifo is intended to adjust for phase differences between two clocks which are of the same frequency only. the fpga receive interface fifos (one per channel) cannot compensate for frequency variations. cc_min_ipg insertion/deletion multiplier factor ?0? 1 x ?1? 2 x ?2? 3 x ?3? 4 x 8-23 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-15. pcs clock domain transfers for ctc modes to guarantee a synchronous interface, both the input transmit clocks and input receive clock should be driven from one of the output reference clocks for a pcs quad set to generic 8b10b mo de. figure 8-16 illustrates the possible connections that would result in a synchronous interface. cdr/ deserializer word align 8b10b decode link state machine clock tolerance compensator fpga receive interface fifo write clock read clock write clock read clock fpga transmit interface fifo read clock write clock data clock to serializer reference clock pll hdin(n/p)_0 ff_rxdata_ch0 ff_rxiclk_ch0 data in data out data out data in data in data out 8b10b encoder transmit path receive path ff_txdata_ch0 ff_txiclk_ch0 ff_ebrdclk_ch0 8-24 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-16. synchronous input cl ocks to pcs quad with ctc used figure 8-17 shows the clock domains for both transmit and receive directions for a single channel inside the pcs which do not utilize the clock tole rance compensation (ctc) block. on the transmit side, a clock domain transfer from the ff_txiclk_ch input at the fpga interface to the locked refer- ence clock occurs in the fpga transmit interface fifo. the fpga transmit interface fifo is intended to adjust for phase differences between two clocks which are of the same frequency only. these fifos (one per channel) cannot compensate for frequency variations. on the receive side, a clock domain transfer occurs between the recovered receive clock and the ff_rxiclk_ch at the fpga receive interface fifo. the fpga receive interface fifo is intended to adjust for phase differences between two clocks which are of the same frequency only. the fpga receive interface fifos (one per channel) cannot compensate for frequency variations. receive clocks 4 ff_txfullclk_ch0* ff_txiclk_ch(0-3) trans mit clocks flexipcs quad 4 ff_rxiclk_ch(0-3) 4 ff_ebrdclk_ch(0-3) *ff_txhalfclk_ch0 if in 16/20-bit data bus mode 8-25 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-17. pcs clock domain transfers for non-ctc modes to guarantee a synchronous interface, both the input transmit clocks and input receive clock should be driven from one of the output reference clocks fo r a pcs quad set to generi c 8b10b mode. figure 8-18 illustrates the possible connections that would result in a synchronous interface. cdr/ deserializer word align 8b10b decode link state machine fpga receive interface fifo write clock read clock fpga transmit interface fifo read clock write clock data clock to serializer reference clock pll hdin(n/p)_0 ff_rxdata_ch0 ff_rxiclk_ch0 data in data out data out data in 8b10b encoder transmit path receive path ff_txdata_ch0 ff_txiclk_ch0 8-26 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-18. synchronous input cl ocks to pcs quad without ctc spread spectrum clocking (ssc) support latticeecp2m serdes/pcs does not have a spread spectrum generator but it can receive spread spectrum data. ssc support in latticeecp2m applies to all protocols that require similar support. the ports on the two ends of link must transmit data at a rate that is within 600pm of each other at all times. this is specified to allow bit-rate clock source with a +/- 300ppm tolerance. the data rate can be modulated from +0% to -0.5% of the nominal data rate, at a modulation rate in the range of 30khz to 33khz. along with the +/- 300ppm tolerance limit, both ports require the same bit rate clock when the data is modulated with an ssc. the root complex is responsible for spreading the reference clock. the endpoint then uses that same clock to pass back the spectrum through the tx. thus, there is no need for a separate rxrefclk. a predominant application of this is the add-in card. add-in cards are not required to use the refclk from the connector but must receive and transmit with the same ssc as the pci express connector refclk. serial digital video and out-of-band low speed serdes operation the serdes receiver buffers can be used to input low speed (<250mbps: out-of-band signal, oob) by bypassing the receiver cdr and associated serdes/ pcs logic. this feature is useful fo r applications where the same pin is needed for both high speed and low speed data transfers do wn to the dc rate, as required by serial digital video applications. latticeecp2m serdes/pcs supports the standard definition serial digital interface, sd-sdi(143mbps, 177mbps, 270mbps, 360mbps) and the high definition serial digital interface, hd-sdi (1.485gbps and 1.483.5gbps). it is required that both of these share the same receive and transmit pins. one possible implementation is shown in figure 8-19. the out-of-band (oob) signal port at the pcs/fpga interf ace is used to input a signal slower than 250 mbps. receive clocks 4 ff_txfullclk_ch0* ff_txiclk_ch(0-3) trans mit clocks flexipcs quad 4 ff_rxfullclk_ch(0-3)* 4 ff_rxiclk_ch(0-3) *ff_txhalfclk_ch0 if in 16/20-bit data bus mode *ff_rxhalfclk_ch(0-3) if in 16/20-bit data bus mode 8-27 lattice semiconductor latticeecp 2m serdes/pcs usage guide this port is available when the sd-sdi mode is select ed. the oob_out signal is passed directly from the serdes input buffers to the fpga interface and is not locked to the reference clock (see figure 8-3). when driving a serdes input buffer with a low speed signal, the serdes input buffer should be set to dc mode, which is done on a per-channel basis by selecting 'dc' in the rx i/o coupling drop-down box of the ipexpress pcs configuration gui (see figure 8-25). though the discussion above talks about serial digital video, it should be noted that similar usage is intended for any low bit rate applications that will do rx clock data recovery in the fpga logic and require decimation in the tx direction. the input bscan circuit appears in parallel with the high-s peed serdes and can be used to route input data to a lower-speed deserializer located elsewhere in the device (not in the quad). an enable signal (one per channel) is required to turn on the input bscan circuit independent of the bscan state machine. figure 8-19. one possible implementa tion of serial digi tal video support configuration guis ipexpress is used to create and configure serdes and pcs blocks. designers use the graphical user interface (gui) to select the serdes protocol standard for a particular quad or channel. ipexpress takes the input from this gui and generates a configuration file (.txt file) and hdl netlist. the hdl model is used in the simulation and syn- thesis flow. the configuration file cont ains attribute level map information. th is file is input for simulation and the isplever bitgen program. it is strongly recommended that designers make changes and updates in ipexpress and then regenerate the configuration file. in some exceptional occasions, users can modify the configuration file. figure 8-20 shows the tools flow when using ipexpress to generate the serdes/pcs block for the serdes pro- tocol standard. when a project is saved in a different directory, this config uration file (.txt) should be manually moved to the same directory as the project file. eq hdinp0 hdinn0 oob_outn low rate data output oob_en bsrmode from jtag config logic input data serdes output data hdoutp0 hdoutn0 rx power up tx power up bscan output cell bscan input cell fpga core quad top serdes/pcs block 8-28 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-20. serdes_pcs isplever user flow ipexpress serdes/pcs module gui configuration ipexpress scuba engine cae simulator synthesis isplever (map planner and router: mpar) serdes/pcs behavioral model module netlist (.v or .vhd) module netlist (.v or .vhd) .txt file (autoconfig file: attribute info) bitstream (includes register map memory cell configuration) latticeecp2m device 8-29 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-21 shows the main window when pcs is selected in the ipexpress gui. figure 8-21. ipexpress pcs main window quad setup tab figure 8-22 shows the quad setup tab window when the file name is entered and the customize button is checked in the main window. the first entry required in this window is to select protocol mode from quad based mode or channel based mode. other entries on this screen are channel selection and group selections. there are five additional tabs shown in figures 8-23 through 8-28, listi ng all the user-accessible attributes with default values settings: figure 8-22. configuration gui - quad setup tab 8-30 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-8. serdes_pcs gui attributes - quad tab setup reference clock setup tab in this tab, the attributes of the tx and rx reference cl ock sources are selected. users can select either a refclk or core_rxrefclk as a rx reference clock source and core_txrefclk as a tx reference clock source for the quad. similarly, in a quad all the channels use the same common tx and rx reference sources. further, there is a tool to provide the required clock rate and multiplier settings for a particular data rate. in addition, for a given data bus width the tool provides the required clock rate to interface the quad to the core. figure 8-23. configuration gui - reference clocks setup tab gui text attribute name s range default value protocol setup quad based protocol mode, channel based pro- tocol mode quad based protocol mode quad protocol mode protocol pci express, gigabit ethernet, generic 8b10b, 10-bit serdes only, 8-bit serdes only, ? sd-sdi, hd-sdi 2 generic 8b10b single ch_mode enable the channel disable mca group1 3 ch_mode multi-channel alignment group 1 disable mca group2 3 ch_mode multi-channel alignment group 2 disable disable ch_mode disable the channel disable channel rate 1 ch_mode full rate, half rate full rate 1. channel rate selection is applicable only in the channel based protocol mode. 2. protocol attribute names: pci express = pcie, gigabit ether net = gige, generic 8b10b = g8b10b, 8-bit serdes only = 8bser, 10 -bit serdes only = 10bser, sd-sdi = sdsdi, hd-sdi = hdsdi. 3. multi-channel-alignment is for transmi tter lane-to-lane skew alignment. receiver multi-channel-alignment is not provided in hard pcs. mca group1 and mca group2 set the channels to ctc bypass mode so that users can build the multi-c hannel alignment in the fpga core. the two groups are provided for identificat ion of channels in multi- protocol applications. 8-31 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-10. reference clock multiplier and fpga interface data bus width by protocol table 8-9. serdes_pcs gui attributes (latticeecp2m) - reference clocks setup tab gui text attribute names button/ box type range default value comment tx reference clock source selec- tion pll_src radio refclk, core_txrefclk refclk rx reference clock source selec- tion ch0_cdr_src ch1_cdr_src ch2_cdr_src ch3_cdr_src radio refclk, core_rxrefclk refclk serial bit clock rate (ghz) datarange 1 check box 0.27 to 3.125 2.5 low: medlow: med: medhigh: high: reference clock multiplier ch0_refck_mult ch1_refck_mult ch2_refck_mult ch3_refck_mult drop down see table 8-10 25x calculated reference clock rate (mhz) 2 cp: refclk_rate text box ? not an editable field fpga interface data bus width ch0_data_width ch1_data_width ch2_data_width ch3_data_width drop down see table 8-10 8 calculated fpga interface clock rate (mhz) 2 cp: fpgaintclk_rate text box ? not an editable field 1. datarange: ? for production devices: low ?? 500 mbps, 500 mbps < medlow ? 1.0 gbps, 1.0 gbps < med < 2.0 gbps, 2.0 gbps ? medhigh < 2.5 gbps, 2.5 gbps ? high ? 3.2 gbps for engineering samples: low ? 540 mbps, 540 mbps < medlow ? 1.0 gbps, 1.0 gbps < med < 2.0 gbps, 2.0 gbps ? medhigh < 2.5 gbps, 2.5 gbps ? high ? 3.2 gbps refer to table 8-99 for details on the control bits setting. 2. 8-bit serdes only mode and 10-bit serdes only mode bypass the link align/comma align, 8b10b encoder/decoder and the ctc. it does not bypass the cdr. protocol reference cloc k multiplier fpga interface data bus width pci express 20x, 25x 8, 16 gbe 10xh, 10x, 20x 8, 16 g8b10b 10xh, 10x, 20x 8, 16 10-bit serdes only 10xh, 10x, 20x 10, 20 8-bit serdes only 8hx, 8x, 16x 8, 16 8-32 lattice semiconductor latticeecp 2m serdes/pcs usage guide reference clock setup tab (channel mode) in this tab, the tx reference clock selected is common to all channels but rx reference clocks can be either ref- clk or core_rxrefclk by channel. figure 8-24. configuration gui - reference clocks setup tab (channel mode) when a user selects channel based protocol mode in the quad tab and sets a channel or channels as half rate mode, this tab displays the half rate mode clock data. 8-33 lattice semiconductor latticeecp 2m serdes/pcs usage guide serdes advance setup this tab is used to access the advanced attributes of the transmit and receive serdes for all four channels. trans- mit attributes such as preemphasis, termination, differential output voltage selection are selected. receive attri- butes such as equalization, termination, i/o coupling are selected. attributes for transmit serdes clock and pll are also selected. figure 8-25. configuration gui - serdes advanced setup tab 8-34 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-11. serdes_pcs gui attributes (la tticeecp2m) - serdes advanced setup tab gui text attribute names button/ box type range default value pci express, gige g8b10b, 8bser 10bser differential output voltage latticeecp2m-35 ch0_tdrv_amp ch1_tdrv_amp ch2_tdrv_amp ch3_tdrv_amp drop down 0(1040mv: default), 1(1280mv), 2 (1320mv), 3 (1360mv), 4 (640mv), 5 (760mv), 6 (870mv), 7 (990mv) 0 all other devices 0(990mv: default), 1( 1250mv), 2 (1300mv), 3 (1350mv), 4 (610mv), 5 (730mv), 6 (820mv), 7 (940mv) preemphasis latticeecp2m-35 ch0_tx_pre ch1_tx_pre ch2_tx_pre ch3_tx_pre drop down disable, 0 (0%), 1 (16%), 2 (36%), 3 (40%), 4 (44%), 5 (56%), 6 (80%) disable all other devices disable, 0 (0%), 1 (12%), 2 (26%), 3 (30%), 4 (33%), 5 (40%), 6 (53%) tx i/o termination (ohms) 3 ch0_rterm_tx ch1_rterm_tx ch2_rterm_tx ch3_rterm_tx drop down 50, 75, 5k 50 equalization 1 ch0_rx_eq ch1_rx_eq ch2_rx_eq ch3_rx_eq drop down mid_high, long_high disable mid_low, mid_med mid_high, long_low long_med, long_high disable disable rx i/o termination (ohms) 3 ch0_rterm_rx ch1_rterm_rx ch2_rterm_rx ch3_rterm_rx drop down 50, 60, 75, high 50 rx i/o coupling ch0_rx_dcc ch1_rx_dcc ch2_rx_dcc ch3_rx_dcc drop down ac, dc ac 2 loss of signal threshold los_threshold drop down 0 (default), 1 (+10%), 2 (+15%),3 (+25%) 4 (-10%), 5 (-15%), 6 (-25%), 7 (-30%) 0 tx pll reference clock i/o termination (ohms) 3 pll_term drop down 50, 2k 50 tx pll reference clock i/o coupling pll_dcc drop down ac, dc ac pll loss of lock pll_lol_set drop down lock unlock 0 0 (+/-600ppmx) 1 (+/-300ppm) 2 (+/-1500ppm) 3 (+/-4000ppm) 0 (+/-1200ppm) 1 (+/-2000ppm) 2 (+/-2200ppm) 3 (+/-6000ppm) 1. refer to appendix d for details. 2. the typical capacitor value of the in ternal on-chip ac coupling is 5 pf. 3. termination resistors and their usage rx i/o termination: 50: so far all of the protocols except smtpe use 50 ohms termination resistor. 60: provided for flexibility purpose only. 75: smpte uses 75 ohm termination resistor. high: such as pci express rx detection. tx i/o termination: 50: so far all of the protocols except smtpe use 50 ohms termination resistor. 75: smpte uses 75 ohm termination resistor. 5k: such as pci express electric idle and pci express rx detection. tx pll termination: 50: if there is no 50 ohm termination resistor on pcb board 2k: if there is 50 ohm termination resistor on pcb board 8-35 lattice semiconductor latticeecp 2m serdes/pcs usage guide high speed i/o termination topolo gy is shown in figure 8-26. figure 8-26. high-speed i/o terminations pcs advanced setup this tab is used to access the advanced attributes of the transmit and receive pcs for all four channels. polarity of each individual tx and rx channel can be individually sele cted. the operating mode (e.g. 8b10b) of the individual channels can be selected. in addition, word alignment values such as comma values, comma mask and comma align can be selected. this tab is also used for setting values for the clock tolerance compensation block. figure 8-27. configuration gui - pcs advanced setup tab vccib vccob hdoutni hdoutpi hdinni hdinpi 50/60/75/high 50/75/5k 50/75/5k 50/60/75/high 5pf eq pci detect vccrx 8-36 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-12. serdes/pcs gui - pcs advanced setup tab gui text attribute name 8-bit serdes only 10-bit serdes only g8b10b pci express gige sd-sdi hd-hdi default tx invert chx_tx_sb normal, invert normal rx invert chx_rx_sb normal rx_tx 8b10b mode chx_8b10b bypass normal bypass normal plus comma value comma_a 4 n/a note 1 n/a 1100000101 minus comma value comma_b 4 00111111010 comma mask comma_m 1111111111 comma align 2 chx_comma_align bypass auto, dynamic, bypass auto, dynamic auto bypass auto ctc 3 chx_ctc_byp bypass 5 normal bypass cc_match1 cc_match1 n/a note 3 n/a 0000000000 cc_match2 cc_match2 0000000000 cc_match3 cc_match3 0100011100 cc_match4 cc_match4 0100011100 cc_match_mode cc_match_mode match_3_4 match_4 match_4 rx ctc min ifg rx ctc min ifg 0, 1, 2, 3 0 high watermark cchmark 0, 1, 2, ..., 14, 15 9 low watermark cclmark 7 1. refer to the word alignment section of this document for detailed information. 2. refer to table 8-6. 3. refer to the clock tolerance compensation sect ion of this document for detailed information. 4. by definition, comma_a and comm_b are one set of 8b10b encoded control character with positive and negative running dispariti es. for example, bc(k28.5) and fd(k29.7) cannot be used as the co mma_a and comm_b in a single design. the usage of comma_a and comm_b in 8bit mode and 16bit mode is exactly the same in both modes. users need to follow the rule in order to get the ls_sync . for example, 1 gbe needs k28.5+d5.6 or d16.2 as id le (word alignment and sync state machine). 5. gige or pci express modes may be used if ctc normal mode is preferred. note that the gige and pci express modes are tuned for their specific data rates. 8-37 lattice semiconductor latticeecp 2m serdes/pcs usage guide optional setup this tab allows is used to select the dynamic logic in version and dynamic external link state machine capability per channel. in addition , users can enable the sci, error reporting, pll quarter clock, and loop-back capability. figure 8-28. configuration gui - optional setup tab table 8-13. tab5. serdes_pcs gui attributes (latticeecp2m) - optional setup tab gui text attribute names button/ box type range default value dynamic inversion of receive data check box true, false false external link state machine 1 check box true, false false loopback (rx to tx) check box true, false false loopback type os_sslb os_splbports os_pcslbports radio box serial loopback, serdes parallel loopback, pcs parallel loopback serial loopback reference clock to fpga core os_refck2core check box true, false false pll quarter clock os_pllqclkports check box true, false false sci check box true, false false sci interrupt os_int_all check box true, false false error status check box true, false false 1. when dynamic mode is selected in the comma align option, the external state machine must be also selected. 8-38 lattice semiconductor latticeecp 2m serdes/pcs usage guide configuration file description ipexpress generates this file which contains attribute level map information. this file is input for simulation, synthe- sis and the isplever bitgen program. it is strongly recommend ed that designers make ch anges in the ipexpress and then regenerate the configuration file. in some exceptional occasions, users can modify the configuration file. the configuration file uses ?txt? as the file type extension. below is an example of the configuration file. # this file is used by the simulation model as well as the isplever bitstream # generation process to automatically initialize the pcsc quad to the mode # selected in the ipexpress. this file is expected to be modified by the # end user to adjust the pcsc quad to the final design requirements. device_name "lfe2m35e" protocol "g8b10b" ch0_mode "single" ch1_mode "disable" ch2_mode "disable" ch3_mode "disable" pll_src "refclk" datarange "high" ch0_cdr_src "refclk" ch0_data_width "8" ch0_refck_mult "10x" #refclk_rate 250.0 #fpgaintclk_rate 250.0 ch0_tdrv_amp "0" ch0_tx_pre "disable" ch0_rterm_tx "50" ch0_rx_eq "disable" ch0_rterm_rx "50" ch0_rx_dcc "ac" los_threshold "0" pll_term "50" pll_dcc "ac" pll_lol_set "0" ch0_tx_sb "normal" ch0_rx_sb "normal" ch0_8b10b "normal" comma_a "1100000101" comma_b "0011111010" comma_m "1111111111" ch0_comma_align "auto" ch0_ctc_byp "bypass" cc_match1 "0000000000" cc_match2 "0000000000" cc_match3 "0100011100" cc_match4 "0100011100" cc_match_mode "match_4" cc_min_ipg "0" cchmark "4" cclmark "4" os_refck2core "0" os_pllqclkports "0" 8-39 lattice semiconductor latticeecp 2m serdes/pcs usage guide latticeecp2m pcs in gigabit ethernet mode gigabit ethernet (1000base-x) idle insert idle pattern insertion is required for clock compensation and auto negotiation. auto negotiation is done in fpga logic. this module automatically inserts /i2/ symbols into the receive data stream during auto-negotiation. while auto-negotiating, the link partner will co ntinuously transmit /c1/ and /c2/ ordered sets. the clock-compensator will not delete these ordered sets as it is configured to only insert/delete /i2/ ordered sets. in order to prevent overruns and underruns in the clock-compensator, /i2/ ordered sets must be periodically inserted to provide insertion/dele- tion opportunities for the clock compensator. while performing auto-negotiation, this module will insert a sequence of 8 /i2 / ordered sets (2 bytes each) every 2048 clock cycles. as this module is after the 8b10b decoder, th is operation will not introd uce any running disparity errors. these /i2/ ordered sets will not be passed on to the fpga receive interface as the gmii interface is driven to idle by the rx state machine during auto-negotiation. once auto-negotiation is complete, /i2/ insertion is dis- abled to prevent any corruption of the received data. note that this state machine is active only during au to-negotiation. the auto-negotiation state machine and the gbe receive state machines are implemented in the soft logic. this state machine depends on the signal ff_xmit_ch[3:0] from the auto-negotiation state machine. this signal is provided on the tx data bus. even though this signal is relatively static (especia lly after auto-negotiation) it is included in the tx data bus. it provides the sig- nal rx_even_ch[3:0]. this is sent out on the receive data bus to the fpga logic. gigabit ethernet idle i nsert and ff_correct_disp_c h[3:0] signal usage the ff_correct_disp_ch[3:0] signal is used on the transmit si de of the quadpcs to ensure that an inter-packet gap begins in the negative disparity state. note that at the end of an ethernet frame, the current disparity state of the transmitter can be either positive or negative, depending on the size and data content of the ethernet frame. how- ever, from the fpga soft-logic side of the quadpcs, the current disparity state of the quadpcs transmitter is unknown. this is where the ff_correct_disp_ch[3:0] signal comes into play. if the ff_correct_disp_ch[3:0] signal is asserted for one clock cycle upon entering an interpacket gap, it will force the quadpcs transmitter to insert an idle1 ordered-set into the transmit data stream if the current disparity is positive. however, if the current disparity is negative, then no change is made to the transmit data stream. from the fpga soft-logic side of the quadpcs, the inte rpacket gap is typically characterized by the continuous transmission of the idle2 ordered set which is as follows: ff_tx_k_cntrl_ch[3:0]=1, ff_txdata= 0xbc ff_tx_k_cntrl_ch[3:0]=0, ff_txdata=0x50. note that in the pcs channel, idle2s mean that current disparity is to be preserved. idle1s mean that the current disparity state should be flipped. therefore, it is possible to ensure that the interpacket gap begins in a negative disparity state. if the disparity state before the interpacket gap is negative, then a continuous stream of idle2s are transmitted during the interpacket gap. if the disparity state before the interpacket gap is positive, then a single idle1 is transmitted followed by a continuous stream of idle2s. in the fpga soft-logic side of the quadpcs, the interpacket gap is always driven with idle2s into the quadpcs. the ff_correct_disp_ch[3:0] signal is asserted for one cl ock cycle, k_cntrl=0, data=0x50 when the interpacket gap first begins. if necessary, the quadpcs will convert this idle 2 into an idle1. for the re mainder of the interpacket gap, idle2s should be driven into the quadpcs and th e ff_correct_disparity_chx signal should remain deas- serted. latticeecp2m pcs in pci express mode an latticeecp2m quad set to pci express mode in ipexpress has additional ports at the fpga interface to enable electrical functions required by the pci express specificat ion such as receiver detection. table 8-14 describes the pci express mode specific ports. 8-40 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-14. pci express mode specific ports receiver detection figure 8-29 shows a receiver detection sequence. a receiver detection test can be performed on each channel of a quad independently. before starting a receiver detection test, the transmitter must be put into electrical idle by setting the ff_pci_ei_en_ch input high. the receiver detection test can begin 120 ns after tx_elec_idle is set high by driving the appropriate ffc_pci_det_en_ch high. this puts the corresponding serdes transmit buffer into receiver detect mode by setting the dr iver termination to high impedance and pu lling both different ial outputs to vccob through the high impedance driver termination. setting the serdes transmit buffer into receiver detect state takes up to 120 ns. after 120ns, the receiver detect test can be initiated by driving the channel?s ffc_pcie_ct_ch input high for four byte (word) clock cycles. the corre- sponding channel?s ffc_pcie_done_ch is then cleared asynchronously. after enough time for the receiver detect test to finish has elapsed (determined by the time constant on the transmit side), the ffs_pcie_done_ch receiver detect status port will go hi gh and the receiver detect stat us can be monitored at the ffs_pcie_con_ch port. if at that time the ffs_pcie_con_ch port is high, then a receiver has been detected on that channel. if, however, the ffs_pcie_con_ch port is low, then no receiver has been detected for that channel. once the receiver detect test is complete, ff_pci_ei_en_ch can be deasserted. figure 8-29. pci express mode receiver detection sequence (example for channel 0) signal direction class description ffs_pcie_done_ch[3:0] o channel 1 = far-end receiver detection complete 0 = far-end receiver detection incomplete ffs_pcie_con_ch[3:0] o channel result of far-end receiver detection. 1 = far end receiver detected 0 = far end receiver not detected. ffc_pcie_det_en_ch[3:0] i channel fpga logic (user logic) informs the serdes block that it will be request- ing for a pci express receiver detection operation. 1=enable pci express receiver detect 0 = normal operation ffc_pcie_ct_ch[3:0] i channel 1 = request transmitter to do far-end receiver detection 0 = normal data operation ffc_ei_en_ch[3:0] i channel control transmission of electric al idle by serdes transmitter 1 = force serdes transmitter to output electrical idle 0 = normal operation ffc_pcie_ct_ch0 ffs_pcie_con_ch0 ffs_pci_done_ch0 ff_pci_det_en_ch0 > 120 ns > 2 ns > 2 us* previous receiver detection status invalid during test 1 if receiver detected 0 if receiver not detected ff_pci_ei_en_ch0 4 byte clocks 8-41 lattice semiconductor latticeecp 2m serdes/pcs usage guide pci express beacon support this section highlights how the la tticeecp2m pcs can support beacon detection and transmission. the pci express requirements for beacon detection are presen ted with the pcs support for beacon transmission and beacon detection. ? beacon detection requirements (pci express base specification, rev 1.0a, chapter 4, page 209-210) ? beacon is required for exit from l2 (p2) state. ? beacon is a dc balanced signal of periodic arbitrary da ta, which is required to contain some pulse widths >= 2ns (500mhz) and < 16us (30khz). ? maximum time between pulses should be < 16us. ? dc balance must be restored within < 32us. ? for pulse widths > 500ns, output beacon voltage level must be 6db down from vtx-diffp-p (800mv to 1200mv). ? for pulse widths < 500ns, output beacon voltage level must be <= vtx-diffp-p and >= 3.5db down from vtx-diffp-p. ? pcs beacon detection support ? the signal loss threshold detection circuit senses if th e specified voltage level exists at the receiver buffer. this is indicated by ffs_rlos_lo_ch(0-3) signal. ? this setting can be used both for pci express electric al idle detection and pci express beacon detection (when in power state p2). ? the remote transmitting device can have a beacon output voltage of 6db down from vtx-diffpp (i.e 201mv). if this signal can be detected, it can be stated that beacon is detected. ? pcs beacon transmission support ? sending the k28.5 character (idle) (5 1?s followed by 5 0?s) provides a periodic pulse with of 2ns occurring every 2ns (1.0ui = 400ps, multiplied by 5 = 2ns). this meets the lower requirement. the output beacon volt- age level can then be v tx-diffp-p . this would be valid beacon transmission. pcs loopback modes the latticeecp2m family of devices provides three loopback modes controlled by control signals at the pcs/fpga interface for convenient testing of the exte rnal serdes/board interface and the internal pcs/fpga logic interface. three loopback modes are provided to loop received data back onto the transmit data path. the loopback modes are useful for checking the high speed se rial serdes package pin connections as well as the embedded serdes and/or pcs logic. serial loopback mode loops serial receive clock/da ta back onto the transmit buffer without pa ssing through the cdr or de-serializer. this feature is intended for internal testing purpose but users can also use it. selecting the serial loopback option in the ipexpress gui will set only the lb_c tl[3:0] to '0010' (refer to table 8- 77). the tdrv_dat_sel[1:0] register bits should be also set to '11' via sci to enable serial loopback mode. the lb_ctl[3:0] register bits are also accessible via sci. serdes parallel loopback mode loops parallel receive data back onto the transmit data path without passing through the pcs logic. serdes par- allel loopback can be selected for each channel individually by setting the appropriate ffc_sb_pfifo_lp_ch(0-3) to a ?1?. pcs parallel loopback mode loops parallel receive data back onto the transmit data path without passing across the pcs/fpga interface. input serial data at the serdes hdin package pins passes through the serdes receive logic where it is converted to 8-42 lattice semiconductor latticeecp 2m serdes/pcs usage guide parallel data, passes through the entire pcs receive logic path, is looped back through the entire pcs transmit logic path, is reconverted back to serial data by the serdes transmitter and sent out onto the hdout serdes package pins. pcs parallel loopback can be selected for each channel individually by setting the appropriate ffc_fb_loopback_ch(0-3) port to a ?1?. figure 8-30 illustrates the three lo opback modes for a single channel. figure 8-30. three loopback modes the two parallel loopback modes described above provide not only control signals from the fpga core but also control register bits. when the control register bits are not set for the loopback mode, the data path can switch between loopback mode and normal data flow by control signals from the fpga core. figure 8-31 describes this logic. refer to tables 8-77 and 8-78 for detailed register settings. figure 8-31. loopback enable signals fpga interface clocks usage figure 8-32 shows a conceptual diagram of the later stage of the pcs core and the fpga bridge and the major clocks that cross the boundary between pcs and the fpga. lsm ff_rxdata_ch0[23:0] serdes serdes bridge (sb) pcs core fpga bridge (fb) ser 8:1/10:1 8b10b encoder up sample fifo eq hdinp0 hdinn0 serial parallel loopback pcs parallel loopback hdoutp0 hdoutn0 pd/ sampler 8b10b decoder down sample fifo refclk cdr des 1:8/1:10 serial loopback rx to tx wa elastic buffer inv inv ff_txdata_ch0[23:0] ck data data ck fifo plb_r2t slb_eq2t slb_r2t_ck slb_r2t_d tdrv_dat_sel[1:0] lb_ctl[3:0] serdes plb en pcs plb en fb_loopback sb_pfifo_lp ffc_sb_pfifo_lp_ch[3:0] serdes parallel loopback enable (serdes plb en) pcs parallel loopback enable (pcs plb en) ffc_fb_loopback_ch[3:0] tdrv_dat_sel[1:0] lb_ctl[3:0] serial loopback enable 8-43 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-32. conceptual pcs/fpga clock interface diagram in the above diagram and in the subsequent clock diagrams in this section, note that suffix ?i? indicates the index [0:3] i.e., one for each channel. none of the clock muxes have logic to guard against clock s licing or glitching. it is a requirement that if any of the selectors to the clock muxes are changed by writes to register bits, the software agent will reset the logic clocked by that muxed clock. the pcs outputs 15 clocks. there are three transmit clocks (per quad) and 12 receive clocks (per channel). the three transmit clocks provide full rate, half rate and quarter rate clocks and are all generated from the tx pll. the full rate and half rate transmit clocks need to be send directly via dedicated route to the center clock mux in the fpga. there are also three clocks (full, half and quarter ra tes) per receive channel. all 15 clocks can be used as local (secondary) or global (primary) clocks for the fpga logic as required. divided-by-two clocks are used when the gearing is in 2:1 mode (the gearing is selectable only on a quad basis). the transmit clock is used on the write port of the up sample fifo (or phase shift fifo, depending on the case). one of the two receive clocks is connected to the read clock of the down sample fifo. the other clocks the read port of the elastic buffer fifo and potentially (depending on the case) the write port of the down sample fifo. based on the whether the elastic buffer and the up sample fifo are bypassed or not and whether we are in 8b10b mode or 16b20b mode, four use cases are possible. the active paths are highlighted with weighted lines. it is also indicated how many and what kind of clock trees are required. there are some modes that would more com- monly be preferred by the user. this section describes the operation for the six different cases that are supported. the six cases are outlined in table 8-15. ser 8b/10b encoder up sample fifo recovered clock refclk bypass /2 /4 /2 /4 tx_clk rx fpga aux down sample fifo elastic buffer cdr dec tx pll pcs ff_rxdata_ch0 ff_rxiclk_ch0 ff_rxfullclk_ch0 ff_txqtrclk ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 ff_txiclk_ch0 ff_ebrd_clk_0 ff_txfullclk ff_txhalfclk ff_txdata_ch0 8-44 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-15. six interface cases between serdes/pcs quad and fpga core 2-to-1 gearing for guaranteed performance of the fpga global clock tree , it is recommended to use a 16/20 bit wide interface for serdes line rates greater than 2.5gbps. in this interface, the fpga interface clocks are running at half the byte clock frequency. even though the 16/20 bit wide interface running at half the byte clock frequency can be used with all serdes line rates, the 8/10 bit wide interface is preferred when the sredes line rate is low enough to allow it (2.5gbps and below) because this results in the most efficient implementation of ip in the fpga core. the decision matrix for the six interface cases is explained in table 8-16. table 8-16. decision matrix for six interface cases 1. this case is intended for single-channel links at line rates of 2.5gbps and lower (8/10 bit wide interface) that require cloc k tolerance com- pensation in the quad. ctc is required when bot h ends of the link have separate referenc e clock sources that are within +/- 300 ppm of each other. case i_a is used if the ip in the core requires the rx ph ase-shift fifo. case i_b is used if the ip does not require thi s fifo. 2. this case is intended for single-channel links at line rates of 2.5gbps and lower (8/10 bit wide interface) that do not requ ire clock toler- ance compensation in the quad. ctc is not required when both ends of the link are connected to the same reference clock source. this is often the case for chip-to-chip links on the same circuit board. there is exactly 0ppm differenc e between the reference clocks and so ctc is not required and can be bypassed. ctc is also not required in t he quad when this function is performed by the ip in the core. 3. this case is intended for multi-channel links at line rate s of 2.5gbps and lower (8/10 bit wide interface). multi-channel al ignment must be done by the ip in the core, there is no provision to do mca in the quad. since mca must be done prior to ctc, the ctc fifo in t he quad must be bypassed when mca is required and so both mc a and ctc (if required) are done by the ip in the core. 4. this case is intended for single-channel links at line rates of 3.2gbps and lower that require a 2:1 gearbox between the qua d and the fpga core (16/20 bit wide interface). clock tolerance compensat ion is included in the quad. ctc is required when both ends of t he link have separate reference clock sources that are within +/- 300ppm of each other. 5. this case is intended for single-channel links at line rates of 3.2gbps and lower that require a 2:1 gearbox between the qua d and the fpga core (16/20 bit wide interface). cloc k tolerance compensation is not included in the quad. ctc is not required when both e nds of the link are connected to the same reference cl ock source. this is often the case for ch ip-to-chip links on t he same circuit board. there is exactly 0ppm difference between the reference clocks and so ctc is not required and can be bypassed. ctc is also not required in the qu ad when this function is performed by the ip in the core. 6. this case is intended for multi-channel links at line rate s of 3.2gbps and lower that require a 2:1 gearbox between the quad and the fpga core (16/20 bit wide interface). multi-channel alignment must be don e by the ip in the core, there is no provision to do mca in the quad. since mca must be done prior to ctc, the ctc fifo in the quad must be bypassed when mca is requi red and so both mca and ctc (if required) are done by the ip in the core. interface data width rx ctc fifo rx phase-shift/down- sample fifo tx phase-shift/ up-sample fifo case i-a 1 8b10b yes yes yes case i-b 1 8b10b bypass yes yes case ii-a 1 16b20b yes yes yes case ii-b 1 16b20b bypass yes yes 1. in all cases in which the tx phase-shift (up-sample) fifo is used, it is never by passed. deep inside the serdes/pcs block, th e datapath width is 8/10 bits wide and the byte clock runs at 1/10 of the serdes line rate. for example, if the serdes line rate is 3.125g bps, then the byte clock is 312.5mhz. serdes line rate datapath width mca re quired? ctc required? interface case 2.5 gbps and below 8/10 bit (1:1 gearing) no, single-channel link ye s c a s e i _ a 1 no case i_b 2 yes, multi-channel link must bypass, not available case i_b 3 3.2 gbps and below 16/20 bit (2:1 gearing) no, single-channel link yes case ii_a 4 no case ii_b 5 yes, multi-channel link must bypass, not available case ii_b 6 8-45 lattice semiconductor latticeecp 2m serdes/pcs usage guide case i_a: 8/10bit, eb and ds fifos not bypassed figure 8-33. 8b10b, eb and ds fifos not bypassed 1. the up sample fifo is acting as a phase shift fifo only in this case. 2. the down sample fifo is acting as a phase shift fifo only in this case. 3. the quad level full rate clock from the tx pll (ff_tx_f_clk) has direct access to the fpga center clock mux. this is a relatively higher performance path. a global clock tree out of the center clock mux is used to clock the user?s interface logic in the fpga. some leaf nodes of the clock tree are connected to the fpga transmit input clock (ff_txi_clki), the elastic bu ffer fifo read clock per channel (ff_ebrd_clki) via cib clk input and the fpga receive input clock (ff_rxi_ clki). this case is prob ably the most common sin- gle channel use case. ser 8:1/10:1 8b10b encoder up sample fifo recovered clock (rx_clki) refclk bypass /2 /4 /2 /4 tx_clk tx rx fpga aux down sample fifo elastic buffer fpga clock tree cdr dec tx pll pcs global clock tree ff_rxdata_ch0 ff_rxiclk_ch0 ff_rxfullclk_ch0 ff_txqtrclk ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 ff_txiclk_ch0 ff_ebrd_clk_0 ff_txfullclk ff_txhalfclk ff_txdata_ch0 8-46 lattice semiconductor latticeecp 2m serdes/pcs usage guide case i_b: 8/10bit, eb fifo bypassed figure 8-34. 8b10b, eb fifo bypassed 1. the up sample fifo is acting as a phase shift fifo only in this case. 2. the down sample fifo is acting as a phase shift fifo only in this case. 3. the tx fpga channel input clock is clocked similarly as in the previous case using a clock tree driven by a direct connection of the full rate transmit fpga ou tput clock to the fpga center clock mux once the elastic buffer is bypassed, the recovered clock needs to control the write port of the down sample fifo. the recovered clock of each channel may need to drive a separate local or global clock tree (i.e., up to 4 local or global clock trees per quad ). the clock tree will then drive the fpga receive clock input to control the read port of the down sample fifo. the reason for bypassing the elastic buffer fifo in this case is most likely for doing multi-channel alignment (mca) in the fpga core. it implies that ctc using an elastic buffer will be done in the fpga core. the ctc fifos ca n be written by either the recovered clocks or by a master recovered clock. the read of the ctc fifo will be done using the tx cloc k via the tx clock tree. ser 8:1/10:1 8b/10b encoder up sample fifo recovered clock (rx_clki) refclk bypass /2 /4 /2 /4 tx_clk tx rx fpga aux down sample fifo elastic buffer cdr dec fpga clock tree fpga clock tree tx pll pcs global clock tree upto 4 local or global clock trees ff_rxdata_ch0 ff_rxiclk_ch0 ff_rxfullclk_ch0 ff_txqtrclk ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 ff_txiclk_ch0 ff_ebrd_clk_0 ff_txfullclk ff_txhalfclk ff_txdata_ch0 8-47 lattice semiconductor latticeecp 2m serdes/pcs usage guide case ii_a: 16/20bit, eb and ds fifos not bypassed figure 8-35. 16/20bit, eb and ds fifos not bypassed 1. the up sample fifo is acting both as a phase shift fifo and up sample fifo in this case. 2. the down sample fifo is acting both as a phase shift fifo and down samp le fifo in this case. 3. this is a very common single channel use case when the fpga is unable to keep up with full byte fre- quency. two clock trees are required. these clock trees are driven by direct access of transmit full rate clock and transmit half rate clock to the fpga clock ce nter mux. the full rate clock tree drives the elastic buffer read port and the down sample fifo write port. the half rate clock tree drives the down sample fifo and the fpga logic. ser 8:1/10:1 8b/10b encoder up sample fifo recovered clock (rx_clki) refclk bypass /2 /4 /2 /4 tx_clk tx rx fpga aux down sample fifo elastic buffer cdr dec tx pll pcs 2 global clock trees ff_rxdata_ch0 ff_rxiclk_ch0 ff_rxfullclk_ch0 ff_txqtrclk ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 ff_txiclk_ch0 ff_ebrd_clk_0 ff_txfullclk ff_txhalfclk ff_txdata_ch0 fpga clock tree (half) fpga clock tree (full) 8-48 lattice semiconductor latticeecp 2m serdes/pcs usage guide case ii_b: 16/20bit , ds not bypassed figure 8-36. 16/20 bit, ds fifo not bypassed 1. the up sample fifo is acting both as a phase shift fifo and up sample fifo in this case. 2. the down sample fifo is acting both as a phase shift fifo and down samp le fifo in this case. 3. this is a very common multi-channel alignment (mca) use case when the fpga is unable to keep up with full byte frequency. the receive clock trees (up to 4) can be local or global. they are running half rate clock. the transmit clock tree is driven by direct access of transmit half rate clock to the fpga clock center mux. in this case, in fpga logic after the mca is done , a ctc will be required. the tx clock tree will clock the read port of the ctc and the master channel receive clock the write port of the ctc. it is important to note that both the mca and ctc need to be done across 16/20bits in this use case. ser 8:1/10:1 8b/10b encoder up sample fifo recovered clock (rx_clki) refclk bypass /2 /4 /2 /4 tx_clk tx rx fpga aux down sample fifo elastic buffer cdr dec tx pll pcs global clock tree upto 4 local or global clk trees fpga clock trees fpga clock tree ff_rxdata_ch0 ff_rxiclk_ch0 ff_rxfullclk_ch0 ff_txqtrclk ff_rxqtrclk_ch0 ff_rxhalfclk_ch0 ff_txiclk_ch0 ff_ebrd_clk_0 ff_txfullclk ff_txhalfclk ff_txdata_ch0 8-49 lattice semiconductor latticeecp 2m serdes/pcs usage guide serdes/pcs block latency table 8-17 describes the latency of each functional block in the transmitter and receiver. latency is given in parallel clock cycles. figure 8-37 shows the location of each block. table 8-17. serdes/pcs latency breakdown (parallel clock cycle) 1 figure 8-37. transmitter and receiver block diagram item description min. average max. fixed bypass units transmit data latency t1 fpga bridge transmit 2 135 1word clk t2 8b10b encoder ? ? ? 2 1 word clk t3 serdes bridge transmit ? ? ? 2 1 word clk t4 3 serializer: 8-bit mode ? ? ? 15 + ? 1?ui + ps serializer: 10-bit mode ? ? ? 18 + ? 1?ui + ps receive data latency r1 3 deserializer: 8-bit mode ? ? ? 10 + ? 2?ui + ps deserializer: 10-bit mode ? ? ? 12 + ? 2?ui + ps r2 serdes bridge receive ? ? ? 2 1 word clk r3 word alignment 3.1 ? 4 ? 0 word clk r4 8b10b decoder ? ? ? 1 1 word clk r5 clock tolerance compensation 7 15 23 1 word clk r6 fpga bridge receive 2 135 1word clk 1. pcs internal parallel clock. this clock ra te is same as the rxfullclk in table 8-5. 2. fpga bridge latency varies by up/down sample fifo read/write . these numbers were presented for 8bit/10bit interface. the depth of down sample/up sample fifo is 4. the earliest read can be done after write clock cycle (1 clock) in down sample fifo. the latest read will be done after the fifo is full (4 + 1 = 5). for 16b/20b interface, the numbers become doubled. min = 2, ma x = 10. this latency depends on the internal fifo flag operation. 3. ? 1 = -245ps, ? 2 = 700ps hdoutpi hdoutni deserializer 1:8/1:10 polarity adjust elastic buffer fifo encoder serdes pcs bypass transmitter receiver recovered clock fpga receive clock fpga receive data transmit data cdr refclk hdinpi hdinni eq polarity adjust up sample fifo serdes bridge fpga bridge serializer 8:1/10:1 wa dec fpga ebrd clock transmit clock tx pll refclk fpga core down sample fifo bypass bypass bypass bypass r1 r2 r3 r4 r5 r6 t1 t2 t3 t4 transmit clock 8-50 lattice semiconductor latticeecp 2m serdes/pcs usage guide serdes client interface (sci) the serdes client interface (sci ) consists of both soft ip that resides in the fpga core and permanent logic that is included in the serdes/pcs quad. the sci allows th e serdes/pcs quad to be controlled by registers as opposed to the configuration memory cells. it is a simple register configuration interface. it shows all the major sig- nals required. the block diagram of the soft ip part of the sci that resides in the fpga core is shown in figure 8- 38. figure 8-38. sci interface block diagram the soft ip that resides in the fpga core should be developed by users per their interface scheme. contact the lattice technical support group for example code. the sciaddr bus is six bits wide within the block. the bus width at the block boundary is 11 bits. the upper five bits are used for quad block selection and channel selection. table 8-18 shows the sci address map for the serdes quad. sciwdata[7:0] sciaddr[10:0] sciwstn scird ? sci (soft) read mux sci (soft ip) registers (soft) registers (soft) address decoder (soft) address decoder (soft) quad serdes/pcs (hard) quad serdes/pcs (hard) scirmxdata[7:0] sciint scirdata[7:0] sciaddr[5:0] sciselaux sciselch3 sciselch2 sciselch1 sciselch0 scienaux sciench3 sciench2 sciench1 sciench0 cyawstn sciint sciaddr[5:0] sciselaux sciselch3 sciselch2 sciselch1 sciselch0 scienaux sciench3 sciench2 sciench1 sciench0 cyawstn scirdata[7:0] ? scirdata[7:0] scirdata[7:0] 8-51 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-18. sci address map for up to four serdes/pcs quads read and write operations through th is interface are asynchronous. in th e write cycle the write data and write address need to be setup and held in relation to the falling edge of the sciwstn. in the read cycle the timing has to be in relation with the scird pulse. figures 8-39 and 8-40 shows the write and read cycles respectively. figure 8-39. sci write cycle, critical timing note: to avoid accidental writing to control registers, registers should be used at the sci input ports to drive them low at power-up reset. address bits description sciaddr[5:0] register address bits 000000 = select register 0 000001 = select register 1 ? 111110 = select register 62 111111 = select register 63 sciaddr[8:6] channel address bits 000 = select channel 0 001 = select channel 1 010 = select channel 2 011 = select channel 3 100 = select aux channel 101 = unused 110 = unused 111 = unused sciaddr[10:9] quad address bits 00 = select quad 0 01 = select quad 1 10 = select quad 2 11 = select quad 3 notes : 1) tsu is the setup time for address and write data prior to the falling edge of the write strobe. 2) th is the hold time for address and write data after the falling edge of the write strobe. sciwstn sciaddr[9:0] scisel, scien sciwdata[7:0] tsu th 8-52 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-40. sci read cycle, critical timing table 8-19. timing parameters the sci interface is as simple as memory read/write. here is an example of the pseudo code: write cycle 1 : set sciaddr[5:0], sciwdata[7:0], scien* = 1'b1 scisel* = 1'b1 cycle 2 : set sciwstn from 0 => 1 cycle 3 : set sciwstn from 1 => 0, scien* = 1'b0, scisel* = 1'b0 read cycle 1 : set sciaddr[5:0], scisel* = 1'b1 cycle 2 : set scird from 0 => 1 cycle 3 : obtain reading data from scirdata[7:0] cycle 4 : set scird from 1 => 0 interrupts and status the status bit may be read via the sci, which is a byte wi de and thus reads the status of eight interrupt status sig- nals at a time. the sciint signal goes high to indicate that an interrupt event has occurred. the user is then required to read the qif status register that indicates whether the interrupt came from the quad or one of the chan- nels. this register is not cleared-on-read. it is cleared when all interrupt sources from the quad or channel is cleared. once the aggregated source of interrupt is determined, the user can read the registers in the associated quad or channel to determine the actual source of the interrupt. tables 8-20 and 8-21 list all the sources of interrupt. parameter typical value units tsu, trddv, taddv 1.127 ns th, trdde 0.805 ns notes: 1) trddv is the time from assertion of the read pulse until read data is valid. 2) taddv is the time from address change until data is valid while read pulse is asserted. 3) trdde is the hold time of the read data after the deassertion of the read pulse. sciaddr[9:0] scisel, scien scird scirdata[7:0] trddv taddv trdde taddv 8-53 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-20. quad interrupt sources table 8-21. channel interrupt sources serdes client interface application example lattice semiconductor?s orcastra fpga configuration software is a pc-based graphical user interface (gui) that allows users to configure the operational mode of a lattice fpga by programming control bits in the fpga regis- ters. serdes/pcs status information is displayed on-screen in real time, and any configuration can be saved to control registers for additional testing. use of the gui does not interfere with the programming of the fpga core portion. more information and downloadable files for orcastra can be found on the lattice semiconductor website at www.latticesemi.com/products/designsoftware/orcastra.cfm . for example: users can switch the reference clock multiplier mode between 10x mode and 20x mode by changing refck_mode[1](d7) and refck_mode[0](d6) bits in the quad pcs control register, ser_ctl_3_qd_13. the sci address of the register is 13(h) and orcastra address = 113 (h). the quad reset (qd_18[5]) must be toggled to achieve this transition. the read/write operation can be achieved in two different ways. 1. in the main window, users can read and write the content of control register read status registers. 2. in the sub-windows, users can select pull-down menu options, or check/uncheck on/off options. quad sci_int source description register name int_quad_out quad interrupt. if there is an interrupt event anywhere in the quad this register bit will be active. this register bit gets cleared when all interrupt events have been cleared. pcs quad status register 1 int_cha_out[0:3] channel interrupt. if there is an interrupt event anywhere in the respective channel this register bit will be active. these register bits are cleared when all interrupt sources in the respective channel have been cleared. pcs quad status register 1 ls_sync_statusn_[0:3]_int ls_sync_status_[0:3]_int link status low (out of sync) channel interrupt link status high (in sync) channel interrupt pcs quad status register 3 ~plol, plol interrupt generated on ~plol and plol - pll loss of lock serdes quad status register 2 quad sci_int source description register name fb_tx_fifo_error_int fb_rx_fifo_error_int cc_overrun_int cc_underrun_int fpga bridge up sample tx fifo error interrupt fpga bridge down sample rx fifo error interrupt ctc (elastic buffer) overrun and underrun interrupts pcs channel general interrupt status register 4 pci_det_done_int rlos_lo_int ~rlos_lo_int rlos_hi_int ~rlos_hi_int rlol_int ~rlol_int interrupt generated for pci_det_done interrupt generated for rlos_lo interrupt generated for ~rlos_lo interrupt generated for rlos_hi interrupt generated for ~rlos_hi interrupt generated for rlol interrupt generated for ~rlol serdes channel interrupt sta- tus register 5 8-54 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-22. sci address map dynamic configurati on of serdes/pcs quad the serdes/pcs quad can be controlled either by the configuration memory cells or by registers that are accessed through the optional ? serdes client interface? (sci). the sci consis ts of both a soft ip that resides in the fpga core and permanent logic that is included in the serdes/pcs quad. the sci is only available if the soft ip is present in the fpga core. after configuration is complete, those configuration memory cells that have associated registers are automatically copied into the registers. subs equent changes to the contents of the registers will not affect the value stored in the configuration memory cells but will of course change the opera tion of the serdes/pcs quad. when controlled by the configuration memory cells, it is a requirement that the serdes/pcs quads must reach a functional state after configuration is complete, without further intervention from the user. this means that any spe- cial reset sequences that are required to initialize the serdes/pcs quad must be handled automatically by the hardware. in other words, use of the sci is optional, the serdes/pcs quad must not assume that the soft ip is present in the fpga core. serdes debug capabilities lattice has tools to help in the debug of the serdes/pcs operation in latticeecp2m devices. lattice orcastra software is a pc-based graphical user interface for configuring the operational mode of a latticeecp2m device by programming control bits in the on- chip registers. this helps you quickly explore configu- ration options without going through a lengthy re-compile process or making changes to your board. configurations created in the gui can be saved to memory and re-loaded for later use. to use orcastra, sci ip must be instanti- ated in the user logic. a macro capability is also available to support script-based config uration and testing. the gui can also be used to display system status information in real time. use of the orcastra software does not interfere with the program- ming of the fpga. figure 8-41 shows the orcastra gui top-level window. us ers can read and write in this window without going through the subwindows for each pcs ch annel by read and write data at ad rs cell. when invoked, orcastra will automatically recognize the device type. or, device ty pes can be selected under the device pull-down menu. address bit description sciaddr[5:0] register address bits 000000 = register 0 000001 = register 1 .......... 111110 = register 62 111111 = register 63 sciaddr[8:6] channel address bits 000 = channel 0 001 = channel 1 010 = channel 2 011 = channel 3 100 = aux channel sciaddr[10:9] quad address bits 00 = quad 0 01 = quad 1 10 = quad 2 11 = quad 3 8-55 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-41. orcastra top-level screen shot by default, the data box shown in figure 8-41 follows little endian byte order (i.e., the most significant bit is placed on the right). users can change to big endian order by selecting display data reversed in data box under the options tab. double clicking on the pcs0 (quad 0) button will open the main win dow as shown in figure 8-42. these standard windows menus control the selection of the device and interface. they also support various con- figuration options, including setting up and saving configurations with stored files. figure 8-42. orcastra main window 8-56 lattice semiconductor latticeecp 2m serdes/pcs usage guide control boxes and bu ttons, status boxes and the text window moving the cursor over a control box and clicking the left mouse button sets the control bits. both the bit location and function for the selected box are displayed in the text window and will match those of the register ma p tables in the device's data sheet. only the function is displayed when the cursor is over the bit name. status boxes are simi- lar to control boxes but have an led appearance and a colored background. figure 8-43 shows serdes buffer options window. configuration options can be selected from the pull-down menu. figure 8-43. serdes buffer options window more information and downloadable files for orcastra can be found on the lattice semiconductor website at the following address: www.lat ticesemi.com/products/designsoftware/orcastra.cfm . other design considerations latticeecp2m-35 vs. all ot her lattice ecp2m devices important note: the serdes settings (in the .txt file) for the latticeecp2m-35 are different from all other latticeecp2m devices. the difference includes default setting s that are hidden in the .txt file. when there is device migration from latticeecp2m-35 to all other latticeecp2m devices, users must re-generate the pcs module from the ipexpress gui. engineering samples vs. production devices engineering samples and production devices have their own simulation models and libraries. the library name for the engineering sample is pcsc_ mti_work_reva. simulation of the serdes/pcs serdes/pcs simulation support is provid ed by a pre-compiled model for modelsim ? and nc-verilog ? . the simu- lation model that is pre-compiled is a behavioral model for the serdes and the rtl of the pcs. table 8-23 pro- vides the location for each of the simulation models. 8-57 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-23. simulation model locations models that are distributed in .zip files need to be decompressed before the model can be used. reset usage in simulation if any of the pcs reset signals is not tied to gnd, the de signer must be careful if the same reset signal is used in the fpga core. for example, if one of the reset signals is used to reset both the pcs and a counter in the fpga core, and the counter uses txfullclk, the counter will not work. the counter cannot reset itse lf because txfullck is not running when the reset is active. depending on the reference clock sources, the reset assertion time can vary. for simulation only, it is recommended to use a mini mum active duration of 100ns for pcs reset signals. 16/20-bit word alignment the pcs receiver can not recognize the 16-bit word boundary. with comma_align in 'auto' mode, the pcs can only do byte alignment. the 16-bit word alignment should be done in the fpga fabric and is fairly straight for- ward. the simulation model works in the same way. it can be enhanced if users implement an alignment scheme as described below. for example, if transmit data before at the fpga interface are: yzabcdefghijklm ... (each letter is a byte, 8-bit or 10-bit) then the incoming data in pcs after 8b10b decoder and before rx_gearbox are: yzabcdefghijklm .... after rx_gearbox, they can become: 1. {zy}{ba}{dc}{fe}{hg}{ji}{lk} .... or 2. {az}{cb}{ed}{gf}{ih}{kj}{ml} ... clearly sequence 2 is not aligned. it has one byte offset, but 16/20-bit alignment is needed. let?s say the special character 'a' should be always placed in the lower byte. flopping one 20-bit data combines with the current 16/20-bit data to form 32/40-bit data as shown below: 1. {dcba}{hgfe}{lkji} .... ^ | **found the a in lower 10-bit, set the offset to '0', send out aligned data 'ba' next clock cycle: {fedc}{jihg}{nmlk} .... ^ | **send out aligned data 'dc' etc. simulator model location cadence nc-verilog/vhdl, nc-sim, synposys vcs, mentor graphics modelsim, aldec riviera pro isptools\cae_library\simulation\blackbox note: model file names with ?reva? ar e for latticeecp2m-35 engineering samples only. 8-58 lattice semiconductor latticeecp 2m serdes/pcs usage guide after the 16/20-bit alignment, the output data are: {zy}{ba}{dc}{fe}{hg}{ji}{lk} .... 2. {cbaz}{gfed}{kjih} .... ^ | **found the a in upper 10-bit, set the offset to '10', send out aligned data 'ba' next clock cycle: {edcb}{ihgf}{mlkj} .... ^ | **send out aligned data 'dc' etc. after the 20-bit alignment, the output data are: {zy}{ba}{dc}{fe}{hg}{ji}{lk} .... note: the lsb of a 8/10-bit byte or a 16/20-bit word is always transmitted first and received first. switching between 10xh, 10x and 20x reference clock mult iplier modes using sci designers can change the bit rates between 10xh, 10x and 20x reference clock multiplier modes using the serdes client interface. this is a useful feature in a system where different rates are received at times and the receiver is able to sweep between di fferent rates and lock to one of them . for example, a system can sweep three different rates of 622mbps, 1.244gbps and 2.488gbps and lock to one of them whichever is received. there are a few control register bits associated with different rates. ch_0a[d1]: rate_mode_tx ch_0b[d1]: rate_mode_rx qd_13[d6]: refclk_mode[0] qd_18[d5]: quad_rst switching between 20x to 20xh or 10 x to 10xh mode in 16-bit interface in addition to the control register settings described above, the transmit interface clock(ff_txiclk_chn) input must be switched from txhalfclk to txqtrclk as described in table 8- 5. ff_rxiclk_chn is not affect ed in this case. the cdr pll will automatically tune to the incoming data rate and provide th e correct rxhalfclk as described in table 8-5. contact the lattice semiconductor technical support group for detailed information. off-chip ac coupling when off-chip ac coupling is required, the recommended capacitor values are shown in table 8-24. table 8-24. off-chip ac coupling capacitor values when a dc balanced pattern is used, such as 8b10b en coding, a capacitor of minimum 4.7nf, is required to reduce the edge degradation. data patterns with longer run lengths require larger capacitance values to reduce pattern dependent jitter. protocol min. typ. max. remark units 8b10b 4.7 10 @ 3.125gbps nf pci express rev1.1 75 200 nf 8-59 lattice semiconductor latticeecp 2m serdes/pcs usage guide refer to lattice technical note tn1114, electrical recommendations for lattice serdes , for more information. unused quad/channel and power supply on unused channels, vcctx, vccrx, vccp and vccaux 33 should be powered up. vccib, vccob, hdinp/n, hdoutp/n and refclkp/n should be left floating. unused channel outputs are tristated, with approximately 10 kohm internal resistor connecting between the differential output pair. vccaux33 supplies power to termination resistors. it is recommended to have the pi filter like the other power supplies. vccaux33 noise will directly be coupled to hi gh-speed i/o, hdin/hdout. if vccaux(fpga core power supply) is very clean, it can be connected to vccaux33. also, unused serdes is configured in power down mode by default. reset and power-down control the serdes quad has reset and power-down controls for the whole macro as well as individual reset and power- down controls for each transmitter and receiver as shown in figure 8-44. the reset signals are active high and the power-down signals are active low. the operation of the various reset and power-down controls are described in the following sections. note: when the device is powering up and the chip level power-on-reset is active, the serdes control bits (in the pcs) will be cleared (or will take on thei r default value). this will put the ser des quad into the power-down state. figure 8-44. serdes/pcs quad reset and power-down controls reset generation and distribution is handled by the clocks and resets block. typically, all resets are via hard reset and various fpga fabric resets. reset pulse widths are a function of the source. however, all should be at least a clock wide. the reset logic is shown in figure 8-45 and the corresponding table is in table 8-25. ffc_rpwdnb0 rx ch0 ------------------------------------------- tx ffc_rrst0 ffc_tpwdnb0 ffc_rpwdnb2 rx ch2 ------------------------------------------- tx ffc_rrst2 ffc_tpwdnb2 aux channel ffc_trst0 ffc_rpwdnb1 rx ch1 ------------------------------------------- tx ffc_rrst0 ffc_tpwdnb1 ffc_rpwdnb3 rx ch3 ------------------------------------------- tx ffc_rrst3 ffc_tpwdnb3 ffc_macrorst fpga core serdes/pcs quad 8-60 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-25. serdes/pcs reset table figure 8-45. serdes/ pcs reset diagram reset signals pcs 1 tx pcs 1 rx serdes tx serdes rx pcs ctrl registers tx pll cdr pll fpga control register ffc_lane_tx_rst_ch[3:0] lane_tx_rst[3:0] x ffc_lane_rx_rst_ch[3:0] lane_rx_rst[3:0] x ffc_quad_rst quad_rst xxxx xx ffc_macro_rst macro_rst x x x x ffc_rrst_ch[3:0] 2 rrst[3:0] 2 x ffc_trst_ch[3:0] 3 trst[3:0] 3 x tri_ion (configuration) xxxxx 1. includes sb (serdes bridge), pcs co re and fb (fpga bridge) sub-blocks. 2. for internal use only. this reset should always be tied to '0'. 3. only resets tx pll loss of lock (ffx_plol). ffc_quad_rst quad_rst macro_rst lane_rx_rst_ch[3:0] lane_tx_rst_ch[3:0] tpdwnb_ch[3:0] rpdwnb_ch[3:0] rrst_ch[3:0] trst tri_ion ffc_lane_tx_rst_ch[3:0] ffc_lane_rx_rst_ch[3:0] ffc_rrst_ch[3:0] ffc_trst ffc_macro_rst ffc_rxpdwnb_ch[3:0] ffc_txpdwnb_ch[3:0] configuration register block resets selected digital logic in the serdes 4rx and 4tx pcs channels digital logic resets the complete serdes quad resets all pcs logic sets selected channel to power down mode 8-61 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-26. reset controls description 1, 2, 3 power-down controls description each rx and tx channel can be individually powered-down by a software register bit or a control signal from the fpga. the individual channel power-down control bits will only power down selected blocks within the serdes macro and the high-speed i/o buffers. table 8-27. power-down controls descriptions table 8-28. reset pulse specification table 8-29. power-down/power-up timing specification rest signal description fpga control register ffc_quad_rst quad_rst active high, asynchronous input. resets all serdes channels including the auxiliary channel and pcs. this reset incl udes macro_rst, txpll, cdr, lane_tx_rst, and lane_rx_rst. ffc_macro_rst macro_rst active high, asynchronous input to the serdes quad. gated with software reg- ister bit. this reset is for the serdes block only and txpll and cdrpll are included. ffc_lane_tx/rx_rst_ch[0: 3] lane_tx/rx_rst[0:3] active high, asynchronous input. resets individual tx/rx channel in sb, pcs core and fb blocks. ffc_rrst_ch[0:3] rrst[0:3] resets loss-of-lock (rlol) and loss-of-signal circuits. does not reset cdr pll. ffc_trst trst resets the loss-of-lock of aux pll (plol). 1. for all channels in the quad running in full-data-rate mode, parallel side clocks are guaranteed to be in-phase. 2. for all channels in the quad running in half-data-rate mode, each channel has a separate divide -by-two circuit. since there i s no mechanism in the quad to guarantee that these divide by two circuits are in phase after de-assertion of ?macrorst?, the pcs design should assume that the dividers (and therefore the para llel side clocks) are not in phase. 3. in half-data-rate mode, since there is no guarantee that the parallel side clocks are in phas e, this may add channel-to-chann el skew to both transmit and receive sides of a multi-channel link. signal description fpga register macropdb active low asynchronous input to the serdes quad, acts on all channels including the auxiliary channel. when driven low, it powers down the whole macro including the transmit pll. all clocks are stopped and the macro power dissipation is mini- mized. ffc_txpwdnb_ch[0:3] tpwdnb[0:3] active low transmit channel power down ? powers down the serilizer and output driver. ffc_rxpwdnb_ch[0:3] rpwdnb[0:3] active low receive channel power down ? powers down cdr, input buffer (equalizer and amplifier) and loss-of-signal detector. parameter description min. typ. max. units t macrorst macro reset high time 1 ns t rrst channel rx reset high time 3 ns t trst quad tx reset high time 3 ns parameter description min. typ. max. unit t pwrdn power-down time after macropdb 10 s t pwrup power-up tim after macropdb 100 s 8-62 lattice semiconductor latticeecp 2m serdes/pcs usage guide serdes/pcs reset reset sequence and reset state diagram after power-up and configuration, all serdes resets and fpga resets are applied. lock status signals definitions ffs_plol : 1 = tx pll loss of lock. : 0 = tx pll lock. it takes 1,400,000 ui to declare the lock of the tx pll. ffs_rlol_ch[3:0] : 1 = cdr loss of lock. : 0 = lock maintained. it takes 400,000 reference clock cycles (worst case) to declare the lock of the cdr pll. ffs_rlos_lo_ch[3:0] : 1 = loss of signal detection for each channel. : 0 = signal detected. the ffs_rlol_ch[3:0] status signal is an indicator of the cdr lock status as defined above. however, during the cdr locking process, the cdr pll will lock to the reference clock when there is no input data present. this purpose of this feature is to avoid ignoring the input data when it is restored. in order to ensure the presence of input data during cdr lock status checking, it is recommended to use the ffs_rlos_lo_ch[3:0] signal in conjunction with the ffs_rlol_ch[3:0] signal. in most applications, combin ing the two status signals, ffs_rlol_ch[3:0]_ s and ffs_rlos_lo_ch[3:0], will work as the indicator of loss of cdr lock. but in applications where high-speed traffic is heavily loaded (i.e. multi-channel, multi-quad), ffs_rlos_lo_ch[3:0] may not represent the correct signal status due to the sensitive nature of the detec- tion circuit. it is strongly recommended to use the protocol -level cdr lock status signal in the rx reset sequence instead of ffs_rlol_ch[3:0]. reset sequence 0. quad_reset ? at power up, assert ffc_quad_rst, ffc_lane_tx_rst_ch[ 3:0] and ffc_lane _rx_rst_ch[3:0]. 1. wait_for_timer1 ? start timer1. wait a minimum of 20 ns. 2. check_plol ? release ffc_quad_rst. 3. wait_for_timer2 ? start timer2. if timer2 expires and the tx pll is not locked, go to step 0. 4. check_lol_los ? wait for rx_lol_l os[3:0] to go low. reset timer3. 5. wait_for_timer3 ? wait for both ffs_rlol_ch[3:0] and ffs_rlos_lo_ch[3:0] to go low if there is a transition in rx_lol_los (ffs_rlol_ch[3:0] || ffs_rlos_lo_ch[3:0]), go to step 4. if timer2 expires with rx_lol_los = 1, go to step 0. 6. normal ? release ffc_lane_tx_rst_ch[3:0]. if ffs_plol goes high during normal operation, go to step 0. the reset sequence state diagram is described in figure 8-46. 8-63 lattice semiconductor latticeecp 2m serdes/pcs usage guide figure 8-46. reset state diagram in figure 8-46, rx_lol_los is defined as ffs_rlol_ch[3:0] || ffs_rlos_lo_ch[3:0]. if a protocol-level cdr lock status sig- nal is provided, it can replace the ffs_rlol_ch[3:0] signal. lane_tx_rst_ch[3:0] < = 0 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 0 check lol_los timer3 & rx_lol_los rising edge(rx_lol_los) falling_edge(rx_lol_los) wait for timer3 rx_lol_los || plol timer2 &~plol wait for timer1 timer1 power up quad reset lane_tx_rst_ch[3:0] < = 1 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 1 check plol lane_tx_rst_ch[3:0] < = 0 lane_rx_rst_ch[3:0] < = 0 quad_rst < = 0 timer2 & plol normal wait for timer2 lane_tx_rst_ch[3:0] < = 1 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 1 lane_tx_rst_ch[3:0] < = 1 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 0 lane_tx_rst_ch[3:0] < = 1 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 0 plol plol lane_tx_rst_ch[3:0] < = 0 lane_rx_rst_ch[3:0] < = 1 quad_rst < = 0 timer3 & ~rx_lol_los notes: timer1: ffc_quad_rst asserted for a minimum of 20 ns. timer2: time to declare tx pll lock : 1,400,000 ui. timer 3: time for rx_lol_los signal to stay low (400,000 reference clock cycles). any fpga clock can be used to satisfy the timer requirement. 8-64 lattice semiconductor latticeecp 2m serdes/pcs usage guide power supply sequencing requirements when using the serdes with 1.5v vccib or vccob, the ser des should not be left in a steady state condition with the 1.5v power applied and the 1.2v power not applied. both the 1.2v and the 1.5v power should be applied to the serdes at nominally the same time. the normal variation in ramp_up times of power supplies and voltage regulators is not a concern. references ? technical notes: ? tn1029, fpsc serdes cml buffer interface ? tn1084, latticesc serdes jitter ? tn1114, electrical recommendations for lattice serdes ? tn1159, latticeecp2/m pin assignment recommendations ? hb1003, latticeecp2/m family handbook technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com 8-65 lattice semiconductor latticeecp 2m serdes/pcs usage guide revision history date version change summary september 2006 01.0 initial release. march 2007 02.0 re-formatted and updated majo rity of the document to clarify the serdes functionality in detail. august 2007 02.1 sd-sdi and hd-sdi are added in full-support list. reset sequence, simulation consideration, 16-bit word alignment sec- tions added. plus various updates. september 2007 02.2 updated supported serdes standards table. added simulation of the serdes/pcs section. december 2007 02.3 tdrv_dat_sel tables updated for ecp2m-35 and the rest of ecp2m families. february 2008 02.4 added detailed reset sequence diagram. may 2008 02.5 sci address map updated. clock usage example table updated. control register ch_07[2:0] corrected. august 2008 02.6 updated high speed i/o terminations figure. october 2008 02.7 updated serializer/deserializer blocks latency corrected footnote 5 in the serdes_pcs i/o descriptions table. changed title of per channel register settings for different standards table to k characters recognized for different standards. november 2008 02.8 detailed definitions of reset signals added. january 2009 02.9 removed references to pipe mode. march 2009 03.0 mode-specific control and stat us signals are now arranged in one table (data bus usage by mode table). in all user modes, ctc is bypassed by hardware (serdes/pcs gui - pcs advanced setup tab table). may 2009 03.1 word aligner latency value updated. july 2009 03.2 ffc_txpwdnb description corrected. rlol settling time changed to 4ms. february 2010 03.3 serdes/pcs reset sequence updated. june 2010 03.4 added appendix e. 8-66 lattice semiconductor latticeecp 2m serdes/pcs usage guide appendix a. memory map configuration register definition there are specific quad-level registers and channel-level registers. in each category, there are serdes specific registers and pcs specific registers. within these sub-categories there are: ? control registers ? status registers ? status registers with clear-on-read ? interrupt control registers ? interrupt status registers ? interrupt source registers (clear-on-read) all register bits shown below are with d0 as the least significant bit on the right. the following indications are the nomenclature for what types of register each is: (r/w = read/write, ro = read only, cr = clear on a read). each of these register bits is ?shadowed? with a memory cell. these memory cells are only programmable through bitstream control. after configuration is complete, the configuration memory cells that have associated registers are automatically copied into the registers. subsequ ent changes to th e contents of th e registers will not affect the value stored in the configuration me mory cells but will change the op eration of the serdes/pcs quad. all ?reserved? bits are written to zero. 8-67 lattice semiconductor latticeecp 2m serdes/pcs usage guide per quad regi ster overview table 8-30. quad interface register map ba 1 register name d7 d6 d5 d4 d3 d2 d1 d0 1. per quad control registers (28) per quad pcs control registers (17) 00 qd_00 sync_toggle force_int char_mode xge_mode rio_mode pcie_mode fc_mode uc_mode 5 01 qd_01 bist_rpt_ch_sel[1] 6 bist_rpt_ch_sel[0] bist_res_sel[1] bist_res_sel[0] bist_time_sel[1] bist_time_sel[0] bist_head_sel[1] bist_head_sel[0] 02 qd_02 high_mark[3] high_mark[2] high_mark[1] high_mark[0] low_mark[3] low_mark[2] low_mark[1] low_mark[0] 03 qd_03 min_ipg_cnt[1] min_ipg_cnt[0] match_4_enable m atch_2_enable pfifo_clr_sel asyn_mode sel_test_clk 04 qd_04 cc_match_1[7] cc_match_1[6] cc_match_1[5] cc_match_1 [4] cc_match_1[3] cc_match_1[2] cc_match_1[1] cc_match_1[0] 05 qd_05 cc_match_2[7] cc_match_2[6] cc_match_2[5] cc_match_2 [4] cc_match_2[3] cc_match_2[2] cc_match_2[1] cc_match_2[0] 06 qd_06 cc_match_3[7] cc_match_3[6] cc_match_3[5] cc_match_3 [4] cc_match_3[3] cc_match_3[2] cc_match_3[1] cc_match_3[0] 07 qd_07 cc_match_4[7] cc_match_4[6] cc_match_4[5] cc_match_4 [4] cc_match_4[3] cc_match_4[2] cc_match_4[1] cc_match_4[0] 08 qd_08 cc_match_4[9] cc_match_4[8] cc_match_3[9] cc_match_3 [8] cc_match_2[9] cc_match_2[8] cc_match_1[9] cc_match_1[8] 09 qd_09 udf_comma_mask[7] udf_comma_mask[6] udf_comma_mask[5] udf_comma_mask[4] udf_comma_mask[3] udf_comma_mask[2] udf_comma_mask[1] u df_comma_mask[0] 0a qd_0a udf_comma_a[7] udf_comma_a[6] udf_comma_a[5] udf_comma_a [4] udf_comma_a[3] udf_comma_a[2] udf_comma_a[1] udf_comma_a[0] 0b qd_0b udf_comma_b[7] udf_comma_b[6] udf_comma_b[5] udf_comma_b [4] udf_comma_b[3] udf_comma_b[2] udf_comma_b[1] udf_comma_b[0] 0c qd_0c udf_comma_a[9] udf_comma_a[8] udf_comma_b[9] udf_comma_b[8] udf_comma_mask[9] udf_comma_mask[8] bist_mode bist_en 0d qd_0d bist_udf_def_header [7] bist_udf_def_header [6] bist_udf_def_header [5] bist_udf_def_header [4] bist_udf_def_header [3] bist_udf_def_header [2] bist_udf_def_header [1] bist_udf_def_header [0] 0e qd_0e bist_udf_def_header [15] bist_udf_def_header [14] bist_udf_def_header [13] bist_udf_def_header [12] bist_udf_def_header [11] bist_udf_def_header [10] bist_udf_def_header [9] bist_udf_def_header [8] 0f qd_0f bist_bus8bit_sel bist_ptn_sel[2] bist_ptn_sel[1] bist_ptn_sel[0] bist_udf_def_header [19] bist_udf_def_header [18] bist_udf_def_header [17] bist_udf_def_header [16] 10 qd_int_10 2 ls_sync_status_3_int _ctl ls_sync_status_2_int _ctl ls_sync_status_1_int _ctl ls_sync_status_0_int _ctl ls_sync_statusn_3_ int_ctl ls_sync_statusn_2_ int_ctl ls_sync_statusn_1_ int_ctl ls_sync_statusn_0_ int_ctl per quad serdes control registers (6) 11 qd_11 reserved reserved tx_refck_sel refck_dcc_en refck_rterm refck_out_sel[2] refck_out_sel[1] refck_out_sel[0] 12 qd_12 refck25x bus8bit_sel rlos_hset[2] rlos_hset[1] rlos_hset[0] rlos_lset[2] rlos_lset[1] rlos_lset[0] 13 qd_13 refck_mode[1] refck_mode[0] reserved reserved reserved reserved cdr_lol_set[1] cdr_lol_set[0] 14 qd_14 reserved reserved reserved pll_lol_set[1] pll_lol_set[0] tx_vco_ck_div[2] tx_vco_ck_div[1] tx_vco_ck_div[0] 15 qd_15 reserved reserved reserved reserved reserved reserved reserved reserved 16 qd_int_16 2 plol_int_ctl ~plol_int_ctl reserved reserved reserved reserved reserved reserved per quad clock reset registers (5) 17 qd_17 lane_rx_rst3 lane_rx_rst2 lane_rx_rst1 lane_rx_rst0 lane_tx_rst3 lane_tx_rst2 lane_tx_rst1 lane_tx_rst0 18 qd_18 macropdb macro_rst quad_rst trst rrst[3] rrst[2] rrst[1] rrst[0] 19 qd_19 bist_rx_data_sel bist_bypass_tx_gate bist_sync_head_req [1] bist_sync_head_req [0] sel_sd_rx_clk3 sel_sd_rx_clk2 sel_sd_rx_clk1 sel_sd_rx_clk0 1a qd_1a ff_rx_clk_sel_2[3] ff_rx_clk_sel_2[2] ff_rx_clk_sel_2[1] ff_rx_clk_sel_2[0] ff_rx_clk_sel_1[3] ff_rx_clk_sel_1[2] ff_rx_clk_se l_1[1] ff_rx_clk_sel_1[0] 1b qd_1b ff_tx_clk_sel[2] ff_tx_clk_sel[1] ff_tx_clk_sel[0] reserved ff_rx_clk_sel_0[3] ff_rx_clk_sel_0[2] ff_rx_clk_sel_0[1] ff_rx_clk_ sel_0[0] 2. per quad status registers (9) per quad pcs status registers (5) 20 qd_20 int_qua_out int_cha[3] int_cha[2] int_cha[1] int_cha[0] 21 qd_21 3 ls_sync_status_3 ls_sync_status_2 ls_sync_st atus_1 ls_sync_status_0 ls_sync_statusn_3 ls_ sync_statusn_2 ls_sync_statusn_1 ls_sync_stat usn_0 22 qd_int_22 4 ls_sync_status_3_int ls_sync_status_2_int ls_sync_status_1_int ls_sync_status_0_int ls_sync_statusn_3_ int ls_sync_statusn_2_ int ls_sync_statusn_1_ int ls_sync_statusn_0_ int 23 qd_23 bist_report[7] bist_report[6] bist_report[5] bist_report[4 ] bist_report[3] bist_report[2] bist_report[1] bist_report[0] 24 qd_24 bist_report[15] bist_report[14] bist_report[13] bist_report[12] bist_report[11] bist_report[10] bist_report[9] bist_report[8] per quad serdes status registers (4) 25 qd_25 3 plol ~plol reserved reserved reserved reserved reserved reserved 26 qd_int_26 4 plol_int ~plol_int reserved reserved reserved reserved reserved reserved 27 qd_27 reserved reserved pll_calib_status[5] pll_calib_status[4] p ll_calib_status[3] pll_calib_status[2] pll_calib_status[1] pll_c alib_status[0] 28 qd_28 reserved reserved reserved reserved reserved reserved reserved reserved 1. ba = base address (hex) 2. interrupt control register related to an interruptible status (int_sts_x) register. 3. status register which has an associated interruptible status (int_sts_x) register. 4. interruptible status register; clear on read (has associated control register and status register) 5. uc_mode: 8-bit serdes only and 10-bit serdes only. 6. bist is a built-in prbs generator and checker for internal use only. note: default value is "0", unless otherwise specified. 8-68 lattice semiconductor latticeecp 2m serdes/pcs usage guide per quad pcs contro l register details table 8-31. pcs control register 1 (qd_00) table 8-32. pcs control register 2 (qd_01) table 8-33. pcs control register 3 (qd_02) bit name description type default 7 sync_toggle transition = reset the 4 tx serializer to minimize tx lane-to-lane skew level = normal operation of tx serializers 6 force_int 1 = force to generate interrupt signal 0 = normal operation r/w 0 5 char_mode 1 = enable serdes characterization mode 0 = disable serdes characterization mode r/w 0 4 xge_mode 1 = selects 10gb ethernet 0 = selects 1gb ethernet mode r/w 0 3 rio_mode 1 = selects rapid-io mode 0 = selects other mode (10gbe, 1gbe) r/w 0 2 pcie_mode 1 = pci express mode of operation 0 = selects other mode (rapidio, 10gbe, 1gbe) r/w 0 1fc_mode 1 = select fibre channel mode 0 = selects other mode (pci ex press, rapidio, 10gbe, 1gbe) r/w 0 0 uc_mode 1 = selects user configured mode 0 = selects other mode (pci ex press, rapidio, 10gbe, 1gbe) note: bits 0 to 3 are mutually exclusive. only one of the bits can be set. bit name description type default 7:6 bist_rpt_ch_sel [1:0] 00 = bist report from channel 0 01 = bist report from channel 1 10 = bist report from channel 2 11 = bist report from channel 3 r/w 00 5:4 bist_res_sel [1:0] bist resolution selection 00 = no error 01 < 2 errors 10 < 16 errors 11 < 128 errors r/w 00 3:2 bist_time_sel [1:0] bist time selection: 00 = 5e+8 cycles 01 = 5e+9 cycles 10 = 5e+6 cycles 11 = 100k cycles r/w 00 1:0 bist_head_sel [1:0] bist header selection 00 = k28_5 (k28_5=10?h305 k28_5_=10?h0fa) 01 = a1a2 (ma1=10?h1f6; ma2=10?h128) 10 = 10?h1bc 11 = user defined r/w 0 bit name description type default 7:4 high_mark [3:0] clock compensation fifo high water mark. mean is 4?b1000 r/w 4?b0111 3:0 low_mark [3:0] clock compen sation fifo low water mark. mean is 4?b1000 r/w 4?b1001 8-69 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-34. pcs control register 4 (qd_03) table 8-35. pcs control register 5 - cc match 1 lo (qd_04) table 8-36. pcs control register 6 - cc match 2 lo (qd_05) table 8-37. pcs control register 7 - cc match 3 lo (qd_06) table 8-38. pcs control register 8 - cc match 4 lo (qd_07) table 8-39. pcs control register 9 - cc match hi (qd_08) table 8-40. pcs control register 10 - udf comma mask lo (qd_09) bit name description type default 7:6 min_ipg_cnt [1:0] minimum ipg to enforce r/w 2?b11 5 match_4_enable 1 = enable four character skip matching (using match 4, 3, 2, 1) r/w 0 4 match_2_enable 1 = enable two character skip matching (using match 4,3) r/w 1 3 reserved 2 pfifo_clr_sel 1 = pfifo_clr signal or channel register bit clears the fifo 0 = pfifo_error internal signal self clears the fifo r/w 0 1 asyn_mode for test only, select asynchronous reset r/w 0 0 sel_test_clk for test only, select test clock r/w 0 bit name description type default 7:0 cc_match_1 [7:0] lower bits of user defined clock compensator skip pattern 1 r/w 8?h00 bit name description type default 7:0 cc_match_2 [7:0] lower bits of user defined clock compensator skip pattern 2 r/w 8?h00 bit name description type default 7:0 cc_match_3 [7:0] lower bits of user defin ed clock compensator skip pattern 3 r/w 8?hbc bit name description type default 7:0 cc_match_4 [7:0] lower bits of user defined clock compensator skip pattern 4 r/w 8?h50 bit name description type default 7:6 cc_match_4 [9:8] upper bits of user defined clock compensator skip pattern 4 [9] = disparity error [8] = k control r/w 2?b01 5:4 cc_match_3 [9:8] upper bits of user defined clock compensator skip pattern 3 [9] = disparity error [8] = k control r/w 2?b01 3:2 cc_match_2 [9:8] upper bits of user defined clock compensator skip pattern 2 [9] = disparity error [8] = k control r/w 2?b00 1:0 cc_match_1 [9:8] upper bits of user defined clock compensator skip pattern 1 [9] = disparity error [8] = k control r/w 2?b00 bit name description type default 7:0 udf_comma_mask [7:0] lower bits of user defined comma mask r/w 8?hff 8-70 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-41. pcs control register 11 - udf comma a lo (qd_0a) table 8-42. pcs control register 12 - udf comma b lo (qd_0b) table 8-43. pcs control register 13 - udf comma hi (qd_0c) table 8-44. pcs control register 14 - udf bist header lo (qd_0d) table 8-45. pcs control register 15 - udf bist header md (qd_0e) table 8-46. pcs control register 16 - udf bist header hi (qd_0f) bit name description type default 7:0 udf_comma_a [7:0] lower bits of us er defined comma character ?a? r/w 8?h83 bit name description type default 7:0 udf_comma_b [7:0] lower bits of user defined comma character ?b? r/w 8?h7c bit name description type default 7:6 udf_comma_a [9:8] upper bits of us er defined comma character ?a? r/w 2?b10 5:4 udf_comma_b [9:8] upper bits of us er defined comma character ?b? r/w 2?b01 3:2 udf_comma_mask [9:8] upper bits of user defined comma mask r/w 2?b11 1bist_mode 1 = continuous bist mode 0 = timed bist mode r/w 0 0bist_en 1 = enable pcs bist 0 = normal operation. r/w 0 bit name description type default 7:0 bist_udf_def_header [7:0] lower bits of user defined header for bist r/w 8?h00 bit name description type default 7:0 bist_udf_def_header [15:8] middle bits of user defined header for bist r/w 8?h00 bit name description type default 7 bist_bus8bit_sel 1 = 8 bit data bist 0 = 10 bit data bist r/w 0 6:4 bist_ptn_sel[2:0] bist pattern selection: 000 = prbs11 001 = max data rate 010 = prbs31 011 = prbs21100 = k28_5 101 = a1a2110 = 5150 (repeat) 111 = 2120 (repeat) r/w 0 3:0 bist_udf_def_header [19:16] high bits of user defined header for bist r/w 8?h00 8-71 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-47. pcs interrupt control register 17 (qd_10) per quad serdes cont rol register details note: except indicated, all cha nnels must be reset after writing any serdes control register. table 8-48. serdes control register 1 (qd_11) figure 8-47. reference clock select control bit name description type default 7 ls_sync_status_3_int_ctl 1 = enable interrupt for ls_sync_status_3 (in sync) 0 = disable interrupt for ls_sync_status_3 (in sync) r/w 0 6 ls_sync_status_2_int_ctl 1 = enable interrupt for ls_sync_status_2 (in sync) 0 = disable interrupt for ls_sync_status_2 (in sync) r/w 0 5 ls_sync_status_1_int_ctl 1 = enable interrupt for ls_sync_status_1 (in sync) 0 = disable interrupt for ls_sync_status_1 (in sync) r/w 0 4 ls_sync_statusn_3_int_ctl 1 = enable interrupt for ls_sync_stat us_3 when it goes low (out of sync) 0 = disable interrupt for ls_sync_status_3 when it goes low (out of sync) r/w 0 4 ls_sync_status_0_int_ctl 1 = enable interrupt for ls_sync_status_0 (in sync) 0 = disable interrupt for ls_sync_status_0 (in sync) r/w 0 3 ls_sync_statusn_2_int_ctl 1 = enable interrupt for ls_sync_stat us_2 when it goes low (out of sync) 0 = disable interrupt for ls_sync_status_2 when it goes low (out of sync) r/w 0 1 ls_sync_statusn_1_int_ctl 1 = enable interrupt for ls_sync_stat us_1 when it goes low (out of sync) 0 = disable interrupt for ls_sync_status_1 when it goes low (out of sync) r/w 0 0 ls_sync_statusn_0_int_ctl 1 = enable interrupt for ls_sync_stat us_0 when it goes low (out of sync) 0 = disable interrupt for ls_sync_status_0 when it goes low (out of sync) r/w 0 bit name description type default 7:6 reserved 5 tx_refck_sel txpll reference clock select 0 = refclk (differential input) 1 = core_txrefclk r/w 0 4 refck_dcc_en 1 = reference clock dc coupling enable 0 = reference clock dc coupling disable (default) r/w 0 3 refck_rterm termination at reference clock input buffer 0 = 50 ohm (default) 1 = high impedance r/w 0 2:0 refcl_out_sel[2:0] refck control [0]: 0 = refck buffer enable, 1 = refck buffer disable [1]: 0 = refck2core disable, 1 = refck2core enable [2]: reserved refer to figure 8-47. r/w 3?b000 cdr pll refclkp refclkn tx pll fpga core core_rxrefclk core_txrefclk refck2core tx_refck_sel {qd_11[5]} refck2core_en {qd_11[1]} rx_refck_sel {ch_0b[2]} refck_en {qd_11[0]} 8-72 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-49. serdes control register 2 (qd_12) table 8-50. serdes control register 3 (qd_13) table 8-51. serdes control register 4 (qd_14) table 8-52. serdes control register 5 (qd_15) bit name description type default 7refck25x 1 = internal high speed bit clock is 25x (for reference clock = 100mhz only) 0 = see refck_mode r/w 0 6 bus8bit_sel 1 = select 8-bit bus width 0 = select 10-bit bus width (default) r/w 0 5:3 rlos_hset [2:0] los detector reference current adjustment for larger swing 000 = default 001 = +10% 010 = +15% 011 = +25% 100 = -10% 101 = -15% 110 = -25% 111 = -30% r/w 3?b000 2:0 rlos_lset [2:0] (internal use only) r/w 3?b000 bit name description r/w default 7:6 refck_mode [1:0] 00 = internal high speed bit clock is 20x or 16x 01 = internal high speed bit clock is 10x or 8x 1x = reserved r/w 2?b00 5:2 reserved 1:0 cdr_lol_set [1:0] cdr loss of lock setting: lock unlock 00 = +/-1000ppm x2 +/-1500ppm x2 01 = +/-2000ppm x2 +/-2500ppm x2 10 = +/-4000ppm +/-7000ppm 11 = +/-300ppm +/-450ppm r/w 2?b10 1 1. this is the default value used in isplever 8.1. bit name description r/w default 7:5 reserved 4:3 pll_lol_set [1:0] txpll loss of lock setting lock unlock 00 = +/-300ppm x2 +/-600ppm x2 01 = +/-300ppm +/-2000ppm 10 = +/-1500ppm +/-2200ppm 11 = +/-4000ppm +/-6000ppm r/w 2?b00 2:0 tx_vco_ck_div[2:0] vco output frequency select: 000 = divided by 1 001 = reserved 010 = divided by 2 011 = reserved 100 = divided by 4 101 = divided by 8 110 = divided by 16 111 = divided by 32 r/w 3?b000 bit name description r/w default 7:0 reserved 8-73 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-53. serdes interrupt control register 6 (qd_16) per quad reset and clock c ontrol register details table 8-54. reset and clock control register 1 (qd_17) table 8-55. reset and clock control register 2 (qd_18) table 8-56. reset and clock control register 3 (qd_19) bit name description r/w default 7 plol_int_ctl 1 = interrupt enabled for loss of lock on plol. 0 = interrupt not enabled for loss of lock plol. ro cr 0 6~plol_int_ctl 1 = interrupt enabled for obtaining lock on plol. 0 = interrupt not enabled for obtaining lock plol. ro cr 0 5:0 reserved bit name description r/w default 7 lane_rx_rst3 1 = assert reset signal to channel 3 receive logic r/w 0 6 lane_rx_rst2 1 = assert reset signal to channel 2 receive logic r/w 0 5 lane_rx_rst1 1 = assert reset signal to channel 1 receive logic r/w 0 4 lane_rx_rst0 1 = assert reset signal to channel 0 receive logic r/w 0 3 lane_tx_rst3 1 = assert reset signal to channel 3 transmit logic r/w 0 2 lane_tx_rst2 1 = assert reset signal to channel 2 transmit logic r/w 0 1 lane_tx_rst1 1 = assert reset signal to channel 1 transmit logic r/w 0 0 lane_tx_rst0 1 = assert reset signal to channel 0 transmit logic r/w 0 bit name description r/w default 7 macropdb 0 = assert power down r/w 1 6 macro_rst 1 = assert macro reset r/w 0 5 quad_rst 1 = assert quad reset r/w 0 4 trst 1 = tx reset r/w 0 3:0 rrst [3:0] 1 = rx channel-based reset r/w 0 bit name description r/w default 7 bist_rx_data_sel 0 = data from serdes 1 = data from after 8b10b decoder r/w 0 6 bist_bypass_tx_gate 0 = start to send bist data after finding the head 1 = force to send bist data whether the head is found or not r/w 0 5:4 bist_sync_head_req [1:0] bist sync header counter selection 00 = 5?d5 01 = 5?d8 10 = 5?d14 11 = 5?d24 r/w 00 3 sel_sd_rx_clk3 1 = select rx_clk3 1 for ds fifo write clock 0 = select ff_ebrd_clk_3 for ds fifo write clock r/w 0 2 sel_sd_rx_clk2 1 = select rx_clk2 for ds fifo write clock 0 = select ff_ebrd_clk_2 for ds fifo write clock r/w 0 1 sel_sd_rx_clk1 1 = select rx_clk1 for ds fifo write clock 0 = select ff_ebrd_clk_1 for ds fifo write clock r/w 0 0 sel_sd_rx_clk0 1 = select rx_clk0 for ds fifo write clock 0 = select ff_ebrd_clk_0 for ds fifo write clock r/w 0 1. rx_clk3 is channel3 recovered clock. 8-74 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-57. reset and clock control register 4 (qd_1a) table 8-58. reset and clock control register 5 (qd_1b) per quad pcs status register details table 8-59. pcs status register 1 (qd_20) bit name description r/w default 7 ff_rx_clk_sel3_2 1 = disable ff_rx_f_clk for channel 3 r/w 0 6 ff_rx_clk_sel2_2 1 = disable ff_rx_f_clk for channel 2 r/w 0 5 ff_rx_clk_sel1_2 1 = disable ff_rx_f_clk for channel 1 r/w 0 4 ff_rx_clk_sel0_2 1 = disable ff_rx_f_clk for channel 0 r/w 0 3 ff_rx_clk_sel3_1 1 = enable ff_rx_h_clk for channel 3 r/w 0 2 ff_rx_clk_sel2_1 1 = enable ff_rx_h_clk for channel 2 r/w 0 1 ff_rx_clk_sel1_1 1 = enable ff_rx_h_clk for channel 1 r/w 0 0 ff_rx_clk_sel0_1 1 = enable ff_rx_h_clk for channel 0 r/w 0 bit name description r/w default 7 ff_tx_clk_sel2 1 = disable ff_tx_f_clk for quad r/w 0 6 ff_tx_clk_sel1 1 = enable ff_tx_h_clk for quad r/w 1 5 ff_tx_clk_sel0 1 = enable ff_tx_q_clk for quad r/w 0 4reserved 3 ff_rx_clk_sel3_0 1 = enable ff_rx_q_clk for channel 3 r/w 0 2 ff_rx_clk_sel2_0 1 = enable ff_rx_q_clk for channel 2 r/w 0 1 ff_rx_clk_sel1_0 1 = enable ff_rx_q_clk for channel 1 r/w 0 0 ff_rx_clk_sel0_0 1 = enable ff_rx_q_clk for channel 0 r/w 0 bit name description r/w int? 7:6 reserved 5 ion_delay delayed global resetn from tri_ion ro n 4 int_qua_out per quad interrupt status ro n 3:0 int_cha_out [3:0] per channel interrupt status ro n 8-75 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-60. pcs status register 2 (qd_21) table 8-61. packet interrupt status register 3 (qd_22) table 8-62. pcs bist status register 4 (qd_23) bit name description r/w int? 7 ls_sync_status_3 1 = alarm generated on sync_status_3. 0 = alarm not generated on sync_status_3. ro y 6 ls_sync_status_2 1 = alarm generated on sync_status_2. 0 = alarm not generated on sync_status_2. ro y 5 ls_sync_status_1 1 = alarm generated on sync_status_1. 0 = alarm not generated on sync_status_1. ro y 4 ls_sync_status_0 1 = alarm generated on sync_status_0. 0 = alarm not generated on sync_status_0. ro y 3 ls_sync_statusn_3 1 = alarm generated on sync_status_3 when it goes low (out of sync) 0 = alarm not generated on sync_stat us_3 when it goes low (out of sync) ro y 2 ls_sync_statusn_2 1 = alarm generated on sync_status_2 when it goes low (out of sync) 0 = alarm not generated on sync_stat us_2 when it goes low (out of sync) ro y 1 ls_sync_statusn_1 1 = alarm generated on sync_status_1 when it goes low (out of sync) 0 = alarm not generated on sync_stat us_1 when it goes low (out of sync) ro y 0 ls_sync_statusn_0 1 = alarm generated on sync_status_0 when it goes low (out of sync) 0 = alarm not generated on sync_stat us_0 when it goes low (out of sync) ro y bit name description r/w int? 7 ls_sync_status_3_int 1 = interrupt generated on sync_status_0 (in sync) 0 = interrupt not generated on sync_status_0 (in sync) ro cr y 6 ls_sync_status_2_int 1 = interrupt generated on sync_status_1 (in sync) 0 = interrupt not generated on sync_status_1 (in sync) ro cr y 5 ls_sync_status_1_int 1 = interrupt generated on sync_status_2 (in sync) 0 = interrupt not generated on sync_status_2 (in sync) ro cr y 4 ls_sync_status_0_int 1 = interrupt generated on sync_status_3 (in sync) 0 = interrupt not generated on sync_status_3 (in sync) ro cr y 3 ls_sync_statusn_3_int 1 = interrupt generated on sync_status_3 when it goes low (out of sync) 0 = interrupt not generated on sync_status_3 when it goes low (out of sync) ro cr y 2 ls_sync_statusn_2_int 1 = interrupt generated on sync_status_2 when it goes low (out of sync) 0 = interrupt not generated on sync_status_2 when it goes low (out of sync) ro cr y 1 ls_sync_statusn_1_int 1 = interrupt generated on sync_status_1 when it goes low (out of sync) 0 = interrupt not generated on sync_status_1 when it goes low (out of sync) ro cr y 0 ls_sync_statusn_0_int 1 = interrupt generated on sync_status_0 when it goes low (out of sync) 0 = interrupt not generated on sync_status_0 when it goes low (out of sync) ro cr y bit name description r/w int? 7:0 bist_report [7:0] lower bits of bist report ro n 8-76 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-63. pcs bist status register 5 (qd_24) per quad serdes status register details table 8-64. serdes status register 1 (qd_25) table 8-65. serdes interrupt status register 2 (qd_26) table 8-66. serdes status register 3 (qd_27) table 8-67. serdes status register 4 (qd_28) bit name description r/w int? 7:0 bist_report [15:8] higher bits of bist report ro n bit name description r/w int? 7 plol 1 = pll loss of lock ro y 6 ~plol 1 = pll lock obtained ro y 5:0 reserved bit name description r/w int? 7plol_int 1 = interrupt generated on plol. 0 = interrupt not generated plol. ro cr y 6 ~plol_int 1 = interrupt generated on ~plol. 0 = interrupt not generated ~plol. ro cr y 5:0 reserved bit name description r/w int? 7:6 reserved 5:0 pll_calib_ status[5:0] txpll vco calibration status output ro n bit name description r/w int? 7:0 reserved 8-77 lattice semiconductor latticeecp 2m serdes/pcs usage guide per channel register overview table 8-68. channel interface register map ba 1 register name d7 d6 d5 d4 d3 d2 d1 d0 1. control registers (13) per channel general registers (7) 00 ch_00 enable_cg_align prbs_enable 6 prbs_lock ge_an_enable invert_tx invert_rx 01 ch_01 pfifo_clr pcie_ei_en pcs_det_time_sel[1] pcs_det_time_sel[0] rx_gear_mode tx_gear_mode rx_ch tx_ch 02 ch_02 bus_width8 sb_bypass sb_pfifo_lp sb_bist_sel enc_bypass sel_bist_txd4enc tx_gear_bypass fb_loopback 03 ch_03 lsm_sel signal_detect rx_gear_bypass ctc_bypass dec_bypass wa_bypass rx_sb_bypass sb_loopback 04 ch_int_04 2 cc_underrun_int_ ctl cc_overrun_int_ctl fb_rx_fifo_error_int_ ctl fb_tx_fifo_error_int_ ctl 05 ch_05 los_hi_sel 06 ch_06 per channel serdes registers (6) 07 ch_07 req_en req_lvl_set rcv_dcc_en rate_sel[1] rate_sel[0] rx_dco_ck_div[2] rx_dco_ck_div[1] rx_dco_ck_div[0] 08 ch_08 lb_ctl[3] lb_ctl[2] lb_ctl[1] lb_ctl[0] rterm_rxadj[1] rterm_rxadj[0] rterm_rx[1] rterm_rx[0] 09 ch_09 tdrv_amp[2] tdrv_amp[1] tdrv_amp[0] tdrv_pre_set[2] tdrv_pre_set[1] tdrv_pre_set[0] tdrv_dat_sel[1] tdrv_dat_sel[0] 0a ch_0a tdrv_pre_en rterm_tx[1] rterm_tx[0] rate_mode_tx tpwdnb 0b ch_0b oob_en rx_refck_sel[1] rx_refck_sel[0] rate_mode_rx rpwdnb 0c ch_int_0c 2 pci_det_done_int_ ctl rlos_lo_int_ctl ~rlos_lo_int_ctl rlos_hi_int_ct l ~rlos_hi_int_ctl rlol_int_ctl ~rlol_int_ctl 2. status registers (13) per channel general registers (6) 20 ch_20 3 cc_underrun cc_overrun fb_rx_fifo_error fb_tx_fifo_error 21 ch_21 5 prbs_error_cnt[7] prbs_error_cnt[6] prbs_error_count[5] prbs_error_ cnt[4] prbs_error_cnt[3] prbs_erro r_cnt[2] prbs_erro r_cnt[1] prbs_e rror_cnt[0] 22 ch_22 23 ch_int_23 fb_tx_fifo_error_int fb_rx_fifo_error_int cc_underrun_int cc_overrun_int fb_rx_fifo_error_int fb_tx_fifo_error_int 24 ch_24 ffs_ls_sync_status fb_rxrst_o fb_txrst_o cc_re_o cc_we_o 25 ch_25 per channel serdes registers (7) 26 ch_26 3 pci_det_done rlos_lo ~rlos_lo rlos_hi ~rlos_hi rlol ~rlol 27 ch_27 dco_calib_err dco_calib_done dco_facq_err dco_facq_done pci_connect 28 ch_28 dco_status[7] dco_status[6] dco_status[5] dco_status[4] dco_status[3] dco_status[2] dco_status[1] dco_status[0] 29 ch_29 dco_status[15] dco_status[14] dco_status[13] dco_status [12] dco_status[11] dco_status[10] dco_status[9] dco_status[8] 2a ch_int_2a 4 pci_det_done_int rlos_lo_int ~rlos_lo_int rlos_hi_int ~rlos_hi_int rlol_int ~rlol_int 2b ch_2b 2c ch_2c 1. ba = base address (hex) 2. interrupt control register related to an interruptible status (int_sts_x) register. 3. status register which has an associated interruptible status (int_sts_x) register. 4. interruptible status register; clear on read (has associated control register and status register). 5. status register with clear on read. 6. prbs is generated by built-in logic and is for internal test only. note: default value is ?0?, unless otherwise specified. 8-78 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-69. pcs control register 1 (ch_00) table 8-70. pcs control register 2 (ch_01) bit name description r/w default 7 enable_cg_align only valid when operating in uc_mode 1 = enable continuous comma alignment 0 = disable continuous comma alignment r/w 0 6 prbs_enable 1 = enable prbs generator & checker 0 = normal operational mode. r/w 0 5prbs_lock 1 = lock receive prbs checker 0 = unlock receive prbs checker r/w 0 4 ge_an_enable 1 = enable gige auto negotiation 0 = disable gige auto negotiation r/w 0 3:2 reserved 1 invert_tx 1 = invert transmitted data 0 = do not invert transmitted data. r/w 0 0invert_rx 1 = invert received data 0 = do not invert received data. r/w 0 bit name description r/w default 7 pfifo_clr 1 = clears pfifo if quad register bit pfifo_clr_sel is set to 1. this signal is ored with interface signal pfifo_clr. 0 = normal operation r/w 0 6 pcie_ei_en 1 = pci express electrical idle 0 = normal operation r/w 0 5:4 pcs_det_time_sel[1:0] pcs connection detection time 11 = 16us 10 = 4us 01 = 2us 00 = 8us r/w 0 3 rx_gear_mode 1 = enable 2:1 gearing for receive path on all channels 0 = disable 2:1 gearing for receive path on all channels (no gear- ing) r/w 0 2 tx_gear_mode 1 = enable 2:1 gearing for transmit path on all channels 0 = disable 2:1 gearing for transmit path on all channels (no gear- ing) r/w 0 1 rx_ch 1 = receive outputs can be monitored on the test characterization pins. the test characterization mode (bit 6 in pcs_ctl_4_qd_03) should be set to ?1?. r/w 0 0 tx_ch 1 = transmit pcs inputs are sourced from test characterization ports. the test characterization mode should be enabled. r/w 0 8-79 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-71. pcs control register 3 (ch_02) table 8-72. pcs control register 4 (ch_03) table 8-73. pcs interrupt control register 5 (ch_04) bit name description r/w default 7 bus_width8 1 = 8-bit bus between pcs and ser 0 = 10-bit bus between pcs and ser. r/w 0 6sb_bypass 1 = bypass tx serdes bridge 0 = normal operation r/w 0 5 sb_pfifo_lp 1 = enable parallel loopback from rx to tx via parallel fifo 0 = normal data operation r/w 0 4 sb_bist_sel 1 = select bist data 0 = select normal data r/w 0 3 enc_bypass 1 = bypass 8b10b encoder 0 = normal operation r/w 0 2 sel_bist_txd4enc 1 = enable bist data to tx before 8b10b enc 0 = normal operation r/w 0 1 tx_gear_bypass 1 = bypass pcs tx gear box 0 = normal operation r/w 0 0 fb_loopback 1 = enable loopback in the pcs just before fpga bridge from rx to tx. 0 = normal data operation. r/w 0 bit name description r/w default 7 lsm_sel 1 = selects external lsm for word alignment 0 = selects internal lsm for word alignment r/w 0 6 signal_detect 1 = force enabling the rx link state machine 0 = dependent of ffc_signal_detec t to enable the rx link state machine r/w 0 5 rx_gear_bypass 1 = bypass pcs rx gear box 0 = normal operation r/w 0 4 ctc_bypass 1 = bypass clock toleration compensation 0 = normal operation r/w 0 3 dec_bypass 1 = bypass 8b10b decoder 0 = normal operation r/w 0 2wa_bypass 1 = bypass word alignment 0 = normal operation r/w 0 1 rx_sb_bypass 1 = bypass rx serdes bridge 0 = normal operation r/w 0 0 sb_loopback 1 = enable loopback in the pcs from tx to rx in serdes bridge. 0 = normal data operation. r/w 0 bit name description r/w default 7:4 reserved 3 cc_underrun_int_ctl 1 = enable interrupt for cc_underrun 0 = disable interrupt for cc_underrun. rw 0 2 cc_overrun_int_ctl 1 = enable interrupt for cc_overrun 0 = disable interrupt for cc_overrun. rw 0 1 fb_rx_fifo_error_int_ctl 1 = enable interrupt on empty/full condition in the receive fpga bridge fifo. r/w 0 0 fb_tx_fifo_error_int_ctl 1 = enable interrupt on empty/full condition in the transmit fpga bridge fifo. r/w 0 8-80 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-74. pcs control register 6 (ch_05) table 8-75. pcs control register 7 (ch_06) per channel serdes contro l register details note: except indicated, all cha nnels must be reset after writing any serdes control register. table 8-76. serdes control register 1 (ch_07) table 8-77. serdes control register 2 (ch_08) bit name description r/w default 7:1 reserved 0 low_hi_sel 1 = select rlos_hi 0 = select rlos_lo (this option is for internal use only) r/w 0 bit name description r/w default 7:0 reserved bit name description r/w default 7req_en 1 = receiver equalization enable 0 = receiver equalization disable r/w 0 6 req_lvl_set level setting for equalization 1 = long-reach equalization 0 = mid-length route equalization r/w 0 5 rcv_dcc_en 1 = receiver dc coupling enable. 0 = ac coupling (default) r/w 0 4:3 rate_sel [1:0] equalizer pole position select: 00 = pole position for high frequency range 01 = pole position for medium frequency range 10 = pole position for low frequency range 11 = not used r/w 2?b00 2:0 rx_dco_ck_div[2:0] vco output frequency select: 000 = divided by 1 001 = reserved 010 = divided by 2 011 = reserved 100 = divided by 4 101 = divided by 8 110 = divided by 16 111 = divided by 32 r/w 3?b000 bit name description r/w default 7:4 lb_ctl [3:0] loop back control: [3] = slb_r2t_dat_en, serial rx to tx lb enable(cdr data) [2] = slb_r2t_ck_en, serial rx to tx lb enable(cdr clock) [1] = slb_eq2t_en, serial lb from equalizer to driver enable [0] = slb_t2r_en, serial tx_to rx lb enable r/w 4?h0 3:2 rterm_rxadj [1:0] termination resistor compensation 00 = default 01= -7% 10= -14% 11= -20% r/w 2?b00 1:0 rterm_rx [1:0] 00 = 50 ohm 01 = 75 ohm 10 = 2k ohm 11 = 60 ohm r/w 2?b00 8-81 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-78. serdes control register 3 (ch_09) bit name description r/w default serdes control register 3(ch_09) for latticeecp2m-35 7:5 tdrv_amp[2:0] cml driver amplitude setting (mv), vccob = 1.2v 000 = 1040(default) 001 = 1280 010 = 1320 011 = 1360 100 = 640 101 = 760 110 = 870 111 = 990 r/w 0 4:2 tdrv_pre_set[2:0] tx_driver pre-emphasis level setting 0 1 2 3 4 5 6 % 0 16 36 40 44 56 80 r/w 0 1:0 tdrv_dat_sel[1:0] driver output select: 00 = data from serializer muxed to driver (normal operation) 01 = data rate clock from serializer muxed to driver 10 = serial rx to tx lb (data) if slb_r2t_dat_en='1' 10 = serial rx to tx lb (clock) if slb_r2t_ck_en='1' 11 = serial lb from equalizer to driver if slb_eq2t_en='1' r/w 0 serdes control register 3(ch_09 ) for latticeecp2m-20/50/70/100 7:5 tdrv_amp[2:0] see table 8-81 r/w 0 4.0 tdrv_pre_set[4:0] tx_driver pre-emphasis level setting r/w 0 3-bit setting in gui 0 1 2 3 4 5 6 5-bit setting in register 00000 00001 00010 01010 10010 00011 00100 % 0 12 26 30 33 40 53 8-82 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-79. serdes control register 4 (ch_0a) table 8-80. serdes control register 4 (ch_0b) table 8-81. tdrv_amp setting for latticeecp2m-20/50/70/100 bit name description r/w default 7 reserved 6:5 tdrv_dat_sel[1:0] 1 driver output select: 00 = data from serializer muxed to driver (normal operation) 01 = data rate clock from serialzer muxed to driver 10 = serial rx to tx lb (data) if slb_r2t_data_en='1' 10 = serial rx to tx lb (clock) if slb_r2t_ck_en='1' 11 = serial lb from equalizer to driver if slb_eq2t_en='1' r/w 0 4 tdrv_pre_en 1 = tx driver pre-emphasis enable 0 = tx driver pre-emphasis disable. r/w 0 3:2 rterm_tx [1:0] tx resistor termination select. disabled when pci express fea- ture is enabled 00 = 50 ohm (default) 01 = 75 ohm 10 = 5k ohm r/w 2?b00 1rate_mode_tx 0 = full rate selection for transmit 1 = half rate selection for transmit r/w 0 0tpwdnb 0 = power down transmit channel 1= power up transmit channel r/w 0 1. for latticeecp2m-20/50/70/100. bit name description r/w default tdrv_amp setting for latticeecp2m-35 7:6 tdrv_amp[4:3] see table 8-81. r/w 0 7:5 reserved for latticeecp2m-35 only 4 oob_en 1=enables boundary scan input path for routing the high speed receive inputs to a lower speed serdes in the fpga (for out of band application). r/w 0 3:2 rx_refck_sel [1:0] rx cdr reference clock select 00 = refclk (differential input) 01 = core_rxrefclk 1x = reserved r/w 2?b00 1rate_mode_rx 0 = full rate selection for receive 1 = half rate selection for receive r/w 0 0 rpwdnb 0 = power down receive channel. 1= power up receive channel r/w 0 bit name description r/w default ch_0b [7:6] tdrv_amp[4:3] tx_driver pre-emphasis level setting r/w 0 ch_09 [7:5] tdrv_amp[2:0] 3-bit setting in gui 0 1 2 3 4 5 6 7 5-bit setting in register 00101 00001 00010 00011 11100 10100 10110 01110 mv 990 1250 1300 1350 610 730 820 940 8-83 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-82. serdes interrupt control register 1 (ch_0c) per channel pcs status register details table 8-83. pcs status register 1 (ch_20) table 8-84. pcs status register 2 (ch_21) table 8-85. pcs status register 3 (ch_22) bit name description r/w default 7 reserved 6 pci_det_done_int_ctl 1 = enable interrupt for detection of far-end receiver for pci express r/w 0 5 rlos_lo_int_ctl 1 = enable interrupt for rx loss of signal when input levels fall below the programmed low threshold (using rlos_lset) rw 0 4 ~rlos_lo_int_ctl 1 = enable interrupt for receiver rx loss of signal when input level meets or is greater than programmed low threshold rw 0 3 rlos_hi_int_ctl 1 = enable interrupt for rx loss of signal when input levels fall below the programmed high threshold (using rlos_lset) rw 0 2 ~rlos_hi_int_ctl 1 = enable interrupt for rx loss of signal when input level meets or is greater than programmed high threshold rw 0 1 rlol_int_ctl 1= enable interrupt for receiver loss of lock r/w 0 0 ~rlol_int_ctl 1= enable interrupt when receiver recovers from loss of lock r/w 0 bit name description r/w int? 7:5 reserved 4 pfifo_error 1 = parallel fifo error 0 = no parallel fifo error ro y 3 cc_underrun 1 = cc fifo underrun 0 = cc fifo not underrun ro y 2 cc_overrun 1 = cc fifo overrun 0 = cc fifo not overrun ro y 1 fb_rx_fifo_error 1 = fpga bridge (fb) rx fifo overrun 0 = fb rx fifo not overrun ro y 0 fb_tx_fifo_error 1 = fpga bridge (fb) tx fifo overrun 0 = fb tx fifo not overrun ro y bit name description r/w int? 7:0 prbs_errors count of the number of prbs errors. clears to zero on read. sticks at ff. ro cr n bit name description r/w int? 7:0 reserved 8-84 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-86. pcs general interrupt status register 4 (ch_23) table 8-87. pcs status register 5 (ch_24) table 8-88. pcs status register 6 (ch_25) per channel serdes stat us register details table 8-89. serdes status register 1 (ch_26) bit name description r/w int? 7:4 reserved 3 cc_underrun_int 1 = interrupt generated on cc_underrun 0 = interrupt not generated on cc_underrun ro cr y 2 cc_overrun_int 1 = interrupt generated on cc_overrun 0 = interrupt not generated on cc_overrun ro cr y 1 fb_rx_fifo_error_int 1 = interrupt generated on fb_rx_fifo_error. 0 = interrupt not generated fb_rx_fifo_error. ro cr y 0 fb_tx_fifo_error_int 1 = interrupt generated on fb_tx_fifo_error 0 = interrupt not generated fb_tx_fifo_error. ro cr y bit name description r/w int? 7 reserved 6 ffs_ls_sync_status 1 = sync in the link state machine. 0 = not sync in the lsm. ro n 5 fb_rxrst_o 1 = normal operation 0 = fpga bridge rx reset ro n 4 fb_txrst_o 1 = normal operation 0 = fpga bridge tx reset ro n 3 reserved 2 reserved 1 cc_re_o 1 = elastic fifo read enable 0 = elastic fifo read disable ro n 0 cc_we_o 1 = elastic fifo write enable 0 = elastic fifo write disable ro n bit name description r/w int? 7:0 reserved bit name description r/w int? 7 reserved 6 pci_det_done 1 = receiver detection process completed by serdes transmitter. 0 = receiver detection process not completed by serdes transmitter. ro cr y 5 rlos_lo 1= indicates that the input signal detected by receiver is below the pro- grammed low threshold ro cr y 4 ~rlos_lo 1= indicates that the input signal detected by receiver is greater than or equal to the programmed low threshold ro cr y 3rlos_hi 1= indicates that the input signal detected by receiver is below the pro- grammed high threshold ro cr y 2 ~rlos_hi 1= indicates that the input signal detected by receiver is greater than or equal to the programmed high threshold ro cr y 1 rlol 1=indicates cdr loss of lock to data. cdr is locked to reference clock. ro y 0 ~rlol 1 = indicates that cdr has locked to data. ro y 8-85 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-90. serdes status register 2 (ch_27) table 8-91. serdes status register 3 (ch_28) table 8-92. serdes status register 4 (ch_29) table 8-93. serdes interrupt status register 5 (ch_2a) table 8-94. serdes status register 6 (ch_2b) table 8-95. serdes status register 7 (ch_2c) bit name description r/w int? 7 dco_calib_err 1 = indicates dco calibration might be wrong (l/h boundary band selected) ro n 6 dco_calib_done 1 = indicates dco calibration done ro n 5 dco_facq_err 1 = indicates dco frequency acquisition error (>300ppm) ro n 4 dco_facq_done 1 = indicates dco frequency acquisition done ro n 3:1 reserved 0 pci_connect 1 = receiver detected by serdes transmitter (at the transmitter device). 0 = receiver not detected by serdes transmitter (at the transmitter device). ro n bit name description r/w int? 7:0 dco_status[7:0] setdcoidac[7:0] ro n bit name description r/w int? 7:0 dco_status[15:8] [1:0] = setdcoidac[9:8][ 7:2] = setdcoband[5:0] ro n bit name description r/w int? 7 reserved 6 pci_det_done_int 1 = interrupt generated for pci_det_done ro cr y 5 rlos_lo_int 1 = interrupt generated for rlos_lo ro cr y 4 ~rlos_lo_int 1 = interrupt generated for ~rlos_lo ro cr y 3 rlos_hi_int 1 = interrupt generated for rlos_hi co cr y 2 ~rlos_hi_int 1 = interrupt generated for ~rlos_hi co cr y 1 rlol_int 1 = interrupt generated for rlol co cr y 0 ~rlol_int 1 = interrupt generated for ~rlol co cr y bit name description r/w default 7:0 reserved bit name description r/w default 7:0 reserved 8-86 lattice semiconductor latticeecp 2m serdes/pcs usage guide table 8-96. k characters recognized for different standards character gbe xaui 1xfc pci express rapidio k23.7 (f7) carrier extend pad k27.7 (fb) sop st start tlp a (align) k28.0 (1c) skip r skip sc k28.1 (3c) fts k28.2 (5c) sos start dllp k28.3 (7c) align a idle pd k28.4 (9c) seq k28.5 (bc) +d5.6 or d16.2 = idle sync k +d21.4 +d21.5 +d21.5 = idle comma (used for alignment) k k28.6 (dc) k28.7 (fc) k29.7 (fd) eop t end r (skip) k30.7 (fe) err err end bad note: refer to each standard specification for detailed information. 8-87 lattice semiconductor latticeecp 2m serdes/pcs usage guide appendix b. 8b10b symbol codes table 8-97. 8b10b symbol codes table 8-98. lattice mask for symbol code symbol name (mode combination table) symbol code (8b10b code) 10-bit gui representation k28.0 8`b000_11100 0100011100 k28.5 8`b101_11100 0110111100 k29.7 8`b111_11101 0011111101 d16.2 8`b010_10000 0001010000 d21.4 8`b100_10101 0010010101 d21.5 8`b101_10101 0010110101 k28.5+ 10`b110000_0101 1100000101 k28.5- 10`b001111_1010 0011111010 symbol name (mode combination table) symbol code (8b10b code) 10-bit gui representation 28.5 (mask) 10`b111111_1111 1111111111 8-88 lattice semiconductor latticeecp 2m serdes/pcs usage guide appendix c. attribute cross-reference table table 8-99. attribute cross-reference table independent attribute name dependent attribute names attribute value register map 3 protocol [qaud_mode, chn_rx_det, chn_oob_en, chn_ge_an_en] gige : [00000,00,0,1] pcie : [00100,00.0,0] g8b10b : [00001,00,0,0] 10bser : [00001,00,0,0] 8bser : [00001,00,0,0] sdsdi :[00001,00,1,0] hdsdi :[00001,00,0,0] {qd_00[4:0], ch_01[5:4], ch_0b[4], ch_00[4]} ch[0,1,2,3]_mode [chn_txpwdnb, chn_rxpwdnb] single : [11] group1 : [11] group2 : [11] disable: [00] {ch_0a[0], ch_0b[0]} datarange (ecp2m35 es device) [pll_div, chn_cdr_div] low : [101,101] medlow : [100,100] med : [010,010] medhigh : [010,000] high : [000,000] {qd_14[2:0], ch_07[2:0]} datarange (all other devices) low : [101,101] medlow : [100,100] med : [010,010] medhigh : [000,000] high : [000,000] ch[0,1,2,3]_refck_mult [bus8bit_sel, refck25x, refck_mode, chn_rate_mode_rx, chn_rate_mode_tx] 8x : [1,0,1,0,0] 8xh : [1,0,1,1,1] 10x : [0,0,1,0,0] 10xh : [0,0,1,1,1] 16x : [1,0,0,0,0] 16xh : [1,0,0,1,1] 20x : [0,0,0,0,0] 20xh : [0,0,0,1,1] 25x : [0,1,0,0,0] 25xh : [0,1,0,1,1] {qd_12[6], qd_12[7], qd_13[6], ch_0b[1], ch_0a[1]} ch[0,1,2,3]_data_width [txclkf, txclkh, chn_rxclkf, chn_rxclkh, chn_tx_gear, chn_rx_gear, chn_bus_width8] 8,bypass :[0,1,0000,0000,0,0,1] 8, normal; 10, bypass; 10, normal :[0,1,0000.0000,0,0,0] 16,bypass :[01,1111,1111,1,1,1] 16,normal;20,bypass;20,normal :[0,1,1111,1111,1,1,0] {qd_1b[7], qd_1b[6], qd_1a[7:4], qd_1a[3:0], ch_01[2], ch_01[3], ch_02[7]} pll_src refclk :[0] core_txrefclk :[1] {qd_11[5]} ch[0,1,2,3]_cdr_src refclk :[00] core_rxrefclk :[01] {ch_0b[3:2]} 8-89 lattice semiconductor latticeecp 2m serdes/pcs usage guide ch_[0,1,2,3]_trdv_amp (ecp2m35 all device) 0:[000] 1:[001] 2:[010] 3:[011] 4:[100] 5:[101] 6:[110] 7:[111] ch_09[7:5] ch_[0,1,2,3]_trdv_amp (all other devices) 0:[00101] 1:[00001] 2:[00010] 3:[00011] 4:[11100] 5:[10100] 6:[10110] 7:[01110] ch_0b[7:6] ch_09[7:5] ch_[0,1,2,3]_tx_pre 5 (ecp2m35 es device) [chn_trdv_pre_en, chn_trdv_pre_set] disable:[0,000] 0:[1,000] 1:[1,001] 2:[1,010] 3:[1,011] 4:[1,100] 5:[1,101] {ch_0a[4], ch_09[4:2]} ch_[0,1,2,3]_tx_pre 6 (ecp2m35 non-es device) disable:[0,000] 0:[1,000] 1:[1,001] 2:[1,010] 3:[1,011] 4:[1,100] 5:[1,101] 6:[1,110] ch_[0,1,2,3]_tx_pre 6 (all other devices) disable:[0,00000] 0:[1,00000] 1:[1,00001] 2:[1,00010] 3:[1,01010] 4:[1,10010] 5:[1,00011] 6:[1,00100] {ch_0a[4], ch_09[4:0]} ch[0,1,2,3]_rterm_tx 50:[00] 75:[01] 5k:[10] {ch_0a[3:2]} ch[0,1,2,3]_rx_eq [chn_req_en, chn_req_lvl_set, chn_rate_sel] disable :[0,0,00] mid_low :[1,0,10] mid_med :[1,0,01] mid_high :[1,0,00] long_low :[1,1,10] long_med :[1,1,01] long_high :[1,1,00] {ch_07[7], ch_07[6], ch_07[4:3]} ch[0,1,2,3]_rterm_rx [chn_rx_rterm] 50 :[00] 60 :[11] 75 :[01] high 4 :[10] {ch_08[1:0]} ch[0,1,2,3]_rx_dcc ac:[0] dc:[1] {ch_07[5]} table 8-99. attribute cross-reference table (continued) independent attribute name dependent attribute names attribute value register map 3 8-90 lattice semiconductor latticeecp 2m serdes/pcs usage guide los_threshold (ecp2m35 es device) [rlos_lo, rlos_hi] 0:[000,000] 1:[001,000] 2:[010,000] 3:[011,000] 4:[100,000] 5:[101,000] 6:[110,000] 7:[111,000] {qd_12[2:0], qd_12[5:3]} los_threshold (all other devices) [los_hi_sel, rlos_lo, rlos_hi] 0:[1111,000,000] 1:[1111,000,001] 2:[1111,000,010] 3:[1111,000,011] 4:[1111,000,100] 5:[1111,000,101] 6:[1111,000,110] 7:[1111,000,111] {ch_05[0], qd_12[2:0], qd_12[5:3]} pll_term 50:[0] 2k:[1] {qd_11[3]} pll_dcc ac:[0] dc:[1] {qd_11[4]} pll_lol_set 0:[00] 1:[01] 2:[10] 3:[11] {qd_14[4:3]} ch[0,1,2,3]_tx_sb [chn_txpol, chn_txsbbyp] normal: [0,0] inv : [1,0] {ch_00[1], ch_02[6]} ch[0,1,2,3]_rx_sb [chn_rxpol, chn_rxwsbbyp] normal: [0,0] inv : [1,0] {ch_00[0], ch_03[1]} ch[0,1,2,3]_8b10b [chn_txenc, chn_rxdec] normal: [0,0] bypass: [1,1] {ch_02[3], ch_03[3]} comma_a note 1 {qd_0a[0:7], qd_0c[6:7]} comma_b note 1 {qd_0b[0:7], qd_0c[4:5]} comma_m note 1 {qd_09[0:7], qd_0c[2:3]} ch[0,1,2,3]_comma_alig n [chn_rxwa, chn_lsm_sel, chn_c_align, chn_sig_det] auto : [0,0,0,1] dynamic : [0,1,0,0] bypass : [1,1,0,0] {ch_03[2], ch_03[7], ch_00[7], ch_03[6]} ch[0,1,2,3]_ctc_byp [chn_rxrecclk] normal : [0,0,0,0,0] bypass : [1,1,1,1,1] {qd_19[3:0], ch_03[4]} cc_match1 {qd_04[7:0], qd_08[1:0]} cc_match2 {qd_05[7:0], qd_08[3:2]} cc_match3 {qd_06[7:0], qd_08[5:4]} cc_match4 {qd_07[7:0], qd_08[7:6]} cc_match_mode [match_2_en, match_4_en] match_3_4 : [1,0] match_4 : [0,0] match_1_2_3_4 : [0,1] {qd_03[4], qd_03[5]} table 8-99. attribute cross-reference table (continued) independent attribute name dependent attribute names attribute value register map 3 8-91 lattice semiconductor latticeecp 2m serdes/pcs usage guide cc_min_ipg 0: [00] 1: [01] 2: [10] 3: [11] {qd_03[7:6]} cchmark 0:[0000] 1:[0001] 2:[0010] 3:[0011] 4:[0100] 5:[0101] 6:[0110] 7:[0111] 8:[1000] 9:[1001] 10:[1010] 11:[1011] 12:[1100] 13:[1101] 14:[1110] 15:[1111] {qd_02[7:4]} cclmark 0:[0000] 1:[0001] 2:[0010] 3:[0011] 4:[0100] 5:[0101] 6:[0110] 7:[0111] 8:[1000] 9:[1001] 10:[1010] 11:[1011] 12:[1100] 13:[1101] 14:[1110] 15:[1111] {qd_02[3:0]} [pll_src, chn_cdr_src] [refcklocal] [core_txrefclk, core_rxrefclk, core_rxrefclk, core_rxrefclk, core_rxrefclk]:[1] [refclk,x,x,x,x]:[0]note2 [x,refclk,x,x,x]:[0] [x,x,refclk,x,x]:[0] [x,x,x,refclk,x]:[0] [x,x,x,x,refclk]:[0] {qd_11[0]} os_sslb [chn_eq2t_en] 0:[0] 1:[1] {ch_08[5]} os_splbports [pfifo_clr_sel, chn_sb_pfifo_lp] 0:[0,0] 1:[1,1] {qd_03[2], ch_02[5]} os_pcslbports [fb_loopback] 0:[0] 1:[1] {ch_02[0]} os_refck2core [refck2core] 0:[0] 1:[1] {qd_11[1]} os_pllqclkports [txclkq, chn_rxclkq] 0:[0,0000] 1:[1,1111] {qd_qb[5], qd_1b[3:0]} table 8-99. attribute cross-reference table (continued) independent attribute name dependent attribute names attribute value register map 3 8-92 lattice semiconductor latticeecp 2m serdes/pcs usage guide os_int_all [plol_int, ploln_int, chn_pcidetint, chn_rloslint, chn_rloslnint, chn_rloshint, chn_rloshnint, chn-rlolint, chn_rlolnint, chn_lssyncint, chn_lssyncnint, chn_txfifoint, chn_rxfifoint, chn_ccorunint, chn_ccurunint] 0:[0,0,0,0,0,0,0,0,0,0000, 0000,0,0,0,0] 1:[1,1,1,1,1,1,1,1,1,1111, 1111,1,1,1,1] {qd_16[7], qd_16[6], qd_0c[1], qd_0c[2], qd_0c[3], qd_0c[4], qd_0c[5], qd_0c[6], qd_0c[7], qd_10[7:4], qd_10[3:0], ch_04[0], ch_04[1], ch_04[2], ch_04[3]} 1. 10-bit symbol code default value or specified by user in the ?pcs advanced setup? configurat ion gui. since the 10-bit symbol code repre- sentation in the gui is lsb to msb, the bit r epresentation is swapped appropriately in the table. 2. x = don?t care. 3. qd_xx : quad register with base address = xx ch_yy : channel register with base address = yy 4. high = 2k for latticeecp2m35 es devices and infinity for all other devices. 5. 0: 0%; 1: 16%; 2: 32%; 3:48%; 4:64%; 5:80%. 6. 0: 0%; 1: 16%; 2: 36%; 3:40%; 4:44%; 5:56%; 6:80%. table 8-99. attribute cross-reference table (continued) independent attribute name dependent attribute names attribute value register map 3 8-93 lattice semiconductor latticeecp 2m serdes/pcs usage guide appendix d. protocol sp ecific serdes setup options table 8-100. protocol specific serdes setup options protocol datarate datarate range refck multiplier data width rx equalization 1 gbe 1.25 med 20x, 10x, 5x 8, 16 disable, mid_med, long_med pci express 2.5 high 25x, 20x disable, mid_high, long_high xaui 3.125 high 20x 16 generic 8b10b any_value low, medlow, med, medhigh, high 20x, 10x, 5x 8, 16 disable, mid_low, mid_med, mid_high, long_low, long_med, long_high 8-bit serdes_only 16x, 8x, 4x 10-bit serdes_only 20x, 10x, 5x 10, 20 1. mid: about 20" in length ? long: about 40" in length low: less than 1.2 gbps med: between 1.2 gbps and 2 gbps high: over 2 gbps 8-94 lattice semiconductor latticeecp 2m serdes/pcs usage guide appendix e. lattice diamond usage overview this appendix discusses the use of lattice diamond design software for projects that include the latticeecp2m serdes/pcs module . for general information about the use of lattice diamond, refer to the lattice diamond tutorial. if you have been using isplever software for your fpga design projects, lattice diamond may look like a big change. but if you look closer, you will find many similariti es because lattice diamond is based on the same toolset and work flow as isplever. the changes are intended to provide a simpler, more integrated, and more enhanced user interface. converting an isplever pr oject to lattice diamond design projects created in isplever can easily be imported into la ttice diamond. the pr ocess is automatic except for the isplever process properties, which are similar to the diamond strategy settings, and pcs modules. after importing a project, you need to set up a strategy for it and regenerate any pcs modules. importing an isple ver design project make a backup copy of the isplever project or make a new copy that will become the diamond project. 1. in diamond, choose file > open > import isplever project . 2. in the isplever project dialog box, browse to the project?s .syn file and open it. 3. if desired, change the base file name or location for the diamond project. if you change the location, the new diamond files will go into the ne w location, but the original source files will not move or be copied. the diamond project will refere nce the source files in the original location . the project files are converted to diamond format with the default strategy settings. adjusting pcs modules pcs modules created with ipexpress have an unusual file structure and need additional adjustment when import- ing a project from isplever. there are two ways to do this adjustment. the preferred method is to regenerate the module in diamond. however this may upgrade the module to a more recent version. an upgrade is usually desir- able but if, for some reason, you do not want to upgrade the pcs module, you can manually adjust the module by copying its .txt file into the implementation folder. if you use this method, you must remember to copy the .txt file into any future implementation folders. regenerate pcs modules 1. find the pcs module in the input files folder of file list view. the module may be represented by an .lpc, .v, or .vhd file. 2. if the file list view shows the verilog or vhdl file for the module, and you want to regenerate the module, import the module?s .lpc file: a. in the file list view, right-click the implementation folder ( ) and choose add > existing file . b. browse for the module?s .lpc file, 8-95 lattice semiconductor latticeecp 2m serdes/pcs usage guide in file list, the .lpc file is replaced with an .ipx file. the ipexpress manifest (.ipx) file is new with diamond. the .ipx file keeps track of the files needed for complex modules. using ipexpress wi th lattice diamond using ipexpress with lattice diamond is essentially same as with isplever. the configuration gui tabs are all the same except for the generation options tab. figure 8-48 shows the genera- tion options tab window. figure 8-48. generation options tab table 8-101. serdes_pcs gui attrib utes ? generation options tab gui text description automatic automatically generates the hdl and configuration(.txt) files as needed. some changes do not require regenerating both files. force module and settings generation generates both the hdl and configuration files. force settings generation only generates only the attributes file. you ge t an error message if the hdl file also needs to be generated. force place & route process reset resets the place & route design process, forcing it to be run again with the newly generated pcs module. force place & route trace process reset resets the place & route trace process, fo rcing it to be run again with the newly generated pcs module. note: automatic is set as the default option. if either automatic or forc e settings generation only and no sub-options (process rese t options) are checked and the hdl module is not generated, the reset pointer is set to bitstream generation automatically. after the generation is finished, the reset marks in the process window will be reset accordingly. 8-96 lattice semiconductor latticeecp 2m serdes/pcs usage guide creating a new simulation proj ect using simulation wizard this section describes how to use the simulation wizard to create a simulation project (.spf) file so you can import it into a standalone simulator. 1. in project navigator, click tools > simulation wizard . the simulation wizard opens. 2. in the preparing the simulator interface page click next . 3. in the simulator project name page, enter the name of your project in the project name text box and browse to the file path location where you want to put your simulation projec t using the project location text box and browse button. when you designate a project name in this wizard page, a corresponding folder will be created in the file path you choose. click yes in the popup dialog that asks you if you wish to create a new folder. 4. click either the active-hdl ? or modelsim ? simulator check box and click next . 5. in the process stage page choose which type of process stage of simulation project you wish to create valid types are rtl, post-synthesis gate-level, post-map gate-level, and post-route gate-level+timing. only those process stages that are available are activated. note that you can make a new selection for the current strategy if you have more than one defined in your project. the software supports multiple strategies per project implementation which allow you to experiment with alternative optimization options across a common set of source files. since each strategy may have been processed to different stages, this dialog allo ws you to specify which stage you wish to load. 6. in the add source page, select from the source files listed in the source files list box or use the browse button on the right to choose another desired source file. note that if you wish to keep the source files in the local simulation project directory you just created, check the copy source to simulation directory option. 7. click next and a summary page appears and provides information on the project selections including the simulation libraries. by default, the run simulator chec k box is enabled and will launch the simulation tool you chose earlier in the wizard in the simulator project name page. 8. click finish . the simulation wizard project (.spf) file and a simulation script do file are generated after running the wizard. you can import the do file into your current project if de sired. if you are using active -hdl, the wizard will generate an .ado file and if you are using modelsim, it creates and .mdo file. note: pcs configuration file, (.txt) must be added in step 6. www.latticesemi.com 9-1 tn1102_01.8 june 2010 technical note tn1102 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction the latticeecp2? and latticeecp2m? sysio? buffers give the designer the ability to ea sily interface with other devices using advanced system i/o standards. this technical note describes the sysio standards available and how they can be implemen ted using lattice?s isplever ? design software. sysio buffer overview latticeecp2/m sysio interface contains multiple programm able i/o cells (pic) blocks. each pic contains two pro- grammable i/os (pio), pioa and piob, connected to their respective sysio buffers. two adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?). each programmable i/o (pio) includes a sysio buffer and i/o logic (iologic). the latticeecp2/m sysio buffers supports a variety of single-ended and differential signaling standards. the sysio buffer also supports the dqs strobe signal that is required for interfacing with the ddr memory. one of every 16/18 pios in the latticeecp2/m contains a delay element to facilitate th e generation of dqs signals. the dqs sign al from the bus is used to strobe the ddr data from the memory into input register blocks. for more inform ation on the architecture of the sysio buf- fer please refer to the latticeecp2/m family data sheet . the iologic includes input, output and tristate registers that implement both single data rate (sdr) and double data rate (ddr) applications along with the necessary clock and data selection logic. programmable delay lines and dedicated logic within the iologic are used to provide the required shift to incoming clock and data signals and the delay required by dqs inpu ts in ddr memory. the ddr implemen tation in the iologic and the ddr memory interface support are discussed in more detail in tn1105, latticeecp2/m high-speed i/o interface . supported sysio standards the latticeecp2/m sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into internally ratioed standard such as lvcmos, lvttl and pci; and externally refer- enced standards such as hstl and sstl. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). other single-ended standards supported include sstl and hstl. differential st andards supported include lvds, rs ds, blvds, lvpecl, differential sstl and differential hstl. tables 1 and 2 list the sysio standards supported in latticeecp2/m devices. table 9-1. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lv t t l ? ? lv c m o s 3 3 ? ? lv c m o s 2 5 ? ? lv c m o s 1 8 ? 1 . 8 lv c m o s 1 5 ? 1 . 5 lv c m o s 1 2 ? ? pci 33 ? 3.3 hstl18 class i, ii 0.9 ? hstl15 class i 0.75 ? sstl3 class i, ii 1.5 ? latticeecp2/m sysio usage guide 9-2 latticeecp2/m sysio lattice semiconduct or usage guide sstl2 class i, ii 1.25 ? sstl18 class i, ii 0.9 ? differential interfaces differential sstl18 class i, ii ? ? differential sstl2 class i, ii ? ? differential sstl3 class i, ii ? ? differential hstl15 class i ? ? differential hstl18 class i, ii ? ? lvds, mlvds, lvpecl, blvds, rsds ? ? 1 when not specified, v ccio can be set anywhere in the valid operating range. table 9-2. supported output standards output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma, 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos18, open drain 4ma, 8ma, 12ma 16ma ? lvcmos15, open drain 4ma, 8ma ? lvcmos12, open drain 2ma, 6ma ? pci33/pcix n/a 3.3 hstl18 class i 8ma, 12ma 1.8 hstl18 class ii n/a 1.8 hstl15 class i 4ma, 8ma 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i 8ma, 12ma 2.5 sstl2 class ii 16ma, 20ma 2.5 sstl18 class i n/a 1.8 sstl18 class ii 8ma, 12ma 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i 8ma, 12ma 2.5 differential sstl2, class ii 16ma, 20ma 2.5 differential sstl18, class i n/a 1.8 differential sstl18, class ii 8ma, 12ma 1.8 differential hstl18, class i 8ma, 12ma 1.8 differential hstl18, class ii n/a 1.8 differential hstl15, class i 4ma, 8ma 1.5 lvds n/a 2.5 table 9-1. supported input standards (continued) input standard v ref (nom.) v ccio 1 (nom.) 9-3 latticeecp2/m sysio lattice semiconduct or usage guide sysio banking scheme latticeecp2/m devices have eight general purpose prog rammable sysio banks and a ninth configuration bank. each of the eight general purpose sysio banks has a v ccio supply voltage, and two reference voltages, v ref1 and v ref2 . figure 9-1 shows the eight general purpose banks and the configuration bank with associated supplies. bank 8 is a bank dedicated to configuration logic and has seven dedicated configuration i/os and 14 multiplexed configuration i/os. bank 8 does have the power supply pads (v ccio and v ccaux ) but does not have any indepen- dent v ref pads. the i/os in bank 8 are connected to v ref from bank 3. on the top and bottom banks, the sysio buffer pair consis ts of two single-ended output drivers and two sets of sin- gle-ended input buffers (both ratioed and referenced). the left and right sysio buffer pair consists of two single- ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be configured as a differential input. in 50% of the pairs there is also one differential output driver. the two pads in the pair are described as ?true? and ?comp? , where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differ- ential input buffer. figure 9-1. latticeecp2m sysio banking mlvds 1 n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 rsds 1 n/a 2.5 1. emulated with external resistors. table 9-2. supported output standards (continued) output standard drive v ccio (nom.) note: urc = upper right corner, lrc = lower right corner, ulc = upper left corner and llc = lower left corner. bank 0 bank 1 urc serdes lrc serdes only ecp2m50 & bigger devices llc serdes only ecp2m70 & ecp2m100 ulc serdes only ecp2m70 & ecp2m100 bank 5 bank 4 bank 7 bank 2 bank 3 bank 8 (dedicated & shared config.) bank 6 9-4 latticeecp2/m sysio lattice semiconduct or usage guide v ccio (1.2v/1.5v/1.8v/2.5v/3.3v) there are a total of eight v ccio supplies, v ccio0 - v ccio7 . each bank has a separate v ccio supply that powers the single-ended output drivers and the ratioed input buffers such as lvttl, lvcmos, and pci. lvttl, lvcmos3.3, lvcmos2.5 and lvcmos1.2 also have fixed threshold options allowing them to be placed in any bank. the v ccio voltage applied to the bank determines the ratioed input standards that can be supported in that bank. it is also used to power the differential output drivers. in addition, v ccio8 is used to supply power to the sysconfig? sig- nals. v ccaux (3.3v) in addition to the bank v ccio supplies, devices have a v cc core logic power supply and a v ccaux auxiliary supply that powers the differential and referenced input buffers. v ccaux is used to supply i/o reference voltage requiring 3.3v to satisfy the common-mode range of the drivers and input buffers. v ccj (1.2v/1.5v/1.8v/2.5v/3.3v) the jtag pins have a separate v ccj power supply that is independent of the bank v ccio supplies. v ccj deter- mines the electrical characteristics of the lvcmos jtag pins, both the output high level and the input threshold. table 9-3 shows a summary of all the required power supplies. table 9-3. power supplies input reference voltage (v ref1, v ref2 ) each bank can support up to two separate v ref input voltages, v ref1 and v ref2 , that are used to set the thresh- old for the referenced input buffers. the locations of these v ref pins are pre-determined within the bank. these pins can be used as regular i/os if the bank does not require a v ref voltage. v ref1 for ddr memory interface when interfacing to ddr memory, the v ref1 input must be used as the reference voltage for the dqs and dq input from the memory. a voltage divider between v ref1 and gnd is used to generate an on-chip reference volt- age that is used by the dqs transition detector circuit. this voltage divider is only present on v ref1 it is not avail- able on v ref2 . for more information on the dqs transition detect logic and its implementation, please refer to tn1105, latticeecp2/m high-speed i/o interface . ddr1 follows the sstl25_ii signaling specification and ddr2 follows the sstl18_ii si gnaling specification. mixed voltage support in a bank the latticeecp2/m sysio buffer is connected to three parallel ratioed input buffers. these three parallel buffers are connected to v ccio , v ccaux and v cc , giving support for thresholds that track with v ccio as well as fixed thresh- olds for 3.3v (v ccaux ) and 1.2v (v cc ) inputs. this allows the input threshold for ratioed buffers to be assigned on a pin-by-pin basis rather than tracking with v ccio . this option is available for all 1.2v, 2.5v and 3.3v ratioed inputs and is independent of the bank v ccio voltage. for example, if the bank v ccio is 1.8v, it is possible to have 1.2v and 3.3v ratioed input buffers with fixed thresholds, as well as 2.5v ratioed inputs with tracking thresholds. prior to device configuration, the ratioed input thresholds always tracks the bank v ccio . this option only takes effect after configuration. output standards within a bank are always set by v ccio . table 9-4 shows the sysio stan- dards that can be mixed in the same bank. power supply description value 1 v cc core power supply 1.2v v ccio power supply for the i/o and configur ation banks 1.2v/1.5v/1.8v/2.5v/3.3v v ccaux auxiliary power supply 3.3v v ccj power supply for jtag pins 1.2v/1.5v/1.8v/2.5v/3.3v 1. refer to latticeecp2/m family data sheet for recommended min. and max. values. 9-5 latticeecp2/m sysio lattice semiconduct or usage guide table 9-4. mixed voltage support sysio standards supported by bank table 9-5. i/o standards supported by bank v ccio input sysio standards output sysio standards 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v yes yes yes yes 1.5v yes yes yes yes yes 1 . 8 v ye s ye s ye s ye s ye s 2 . 5 v ye s ye s ye s ye s 3.3v yes yes yes yes description top side banks 0-1 right side banks 2-3 bottom side banks 4-5 left side banks 6-7 i/o buffers single-ended single-ended and differential single-ended single-ended and differential output standards supported lv t t l lv c m o s 3 3 lv c m o s 2 5 lv c m o s 1 8 lv c m o s 1 5 lv c m o s 1 2 sstl18 class i, ii sstl25 class i, ii sstl33 class i, ii hstl15 class i hstl18_i, ii sstl18d class i, ii sstl25d class i, ii sstl33d class i, ii hstl15d class i hstl18d class i, ii lv d s 2 5 e 1 lvpecl 1 blvds 1 rsds 1 lv t t l lv c m o s 3 3 lv c m o s 2 5 lv c m o s 1 8 lv c m o s 1 5 lv c m o s 1 2 sstl18 class i, ii sstl25 class i, ii sstl33 class i, ii hstl15 class i hstl18 class i, ii sstl18d class i, ii sstl25d class i, ii sstl33d class i, ii hstl15d class i hstl18d class i, ii lv d s lv d s 2 5 e 1 lvpecl 1 blvds 1 rsds 1 lvttl lv c m o s 3 3 lv c m o s 2 5 lv c m o s 1 8 lv c m o s 1 5 lv c m o s 1 2 sstl18 class i, ii sstl2 class i, ii sstl3 class i, ii hstl15 class i hstl18 class i, ii sstl18d class i, ii sstl25d class i, ii, sstl33d class i, ii hstl15d class i hstl18d class i, ii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lv t t l lv c m o s 3 3 lv c m o s 2 5 lv c m o s 1 8 lv c m o s 1 5 lv c m o s 1 2 sstl18 class i, ii sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, ii sstl25d class i, ii, sstl33d_i, ii hstl15d class i hstl18d class i, ii lv d s lvds25e 1 lv p e c l 1 blvds 1 rsds 1 inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential clock inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential pci support pci33 without clamp pci33 withou t clamp pci33 with clamp pci33 without clamp pci33 with clamp (ecp2m) lvds output buffers lvds (3.5ma) buffers 2 lvds (3.5ma) buffers 2 1. these differential standards are implemented by using a co mplementary lvcmos driver with external resistor pack. 2. available only on 50% of the i/os in the bank. 9-6 latticeecp2/m sysio lattice semiconduct or usage guide lvcmos buffer configurations all lvcmos buffer have programmable pull, programmable drive and programmable slew configurations that can be set in the software. bus maintenance circuit each pad has a weak pull-up, weak pu ll-down and weak buskeeper capability. the pull-up and pull-down settings offer a fixed characteristic, which is useful in creating wired logic such as wired ors. however, current can be slightly higher than other options, depending on the signal state. the bus-keeper option latches the signal in the last driven state, holding it at a valid level with minimal power dissipation. users can also choose to turn off the bus maintenance circuitry, minimizing power dissipation and inpu t leakage. note that in this case, it is important to ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer. programmable drive each lvcmos or lvttl, as well as some of the referenced (sstl and hstl) output buffers, has a programmable drive strength option. this option can be set for each i/o independently. the drive strength settings available are 2ma, 4ma, 6ma, 8ma, 12ma, 16ma and 20ma. actual options available vary by the i/o voltage. the user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength. table 9-6 shows the available drive settings for each out the output standards. table 9-6. programmable drive values for single-ended buffers programmable slew rate each lvcmos or lvttl output buffer pin also has a programmable output slew rate control that can be configured for either low noise or high-speed performance. each i/o pin has an individual slew rate control. this allows designers to specify slew rate control on a pin-by-pin basis. this slew rate control affects both the rising and falling edges. open-drain control all lvcmos and lvttl output buffers can be configured to function as open drain outputs. the user can imple- ment an open drain output by turning on the opendrain attribute in the software. differential sstl and hstl support the single-ended driver associated wit h the complementary ?c? pad can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. this allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. this is used for driv- ing complementary sstl and hstl signals (as required by the differential sstl and hstl clock inputs on syn- chronous dram and synchronous sram de vices respectively). this capability is also used in conjunction with off- chip resistors to emulate lvpec l, and blvds output drivers. single ended i/o standards programmable drive (ma) hstl15_i/ hstl15d_i 4, 8 hstl18_i/ hstl18d_i 8, 12 sstl25_i/ sstl25d_i 8, 12 sstl25_ii/ sstl25d_ii 16, 20 sstl18_ii/sstl18d_ii 8, 12 lv c m o s 1 2 2 , 6 lv c m o s 1 5 4 , 8 lvcmos18 4, 8, 12, 16 lvcmos25 4, 8, 12, 16, 20 lvcmos33 4, 8, 12, 16, 20 lvttl 4, 8, 12, 16, 20 9-7 latticeecp2/m sysio lattice semiconduct or usage guide pci support with programmable pciclamp each sysio buffer can be configured to support pci33. the buffers on the bottom of the device (for latticeecp2) or on the left and bottom sides of the device (for latticeecp 2m) have an optional pci clamp diode that may optionally be specified in the isplever design tools. programmable pciclamp can be turned on or off. this option is available on each i/o independently on the bottom side banks (for latticeecp2) or on the left and bottom side banks (for latticeecp2m). programmable input delay each input can optionally be delayed before it is passed to the core logic or input registers. the primary use for the input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. to arrive at zero hold time, the input delay will dela y the data by at least as much as th e primary clock injection delay. this option can be turned on or off for each i/o independently in the software using the fixeddelay attribute. this attribute is described in more detail in the software sysio attribute section. appendix a shows how this feature can be enabled in the software using hdl attributes. software sysio attributes sysio attributes can be specified in the hdl, using the preference editor gui or in the ascii preference file (.prf) file directly. appendices a, b and c list examples of how these can be assigned using each of these methods. this section describes each of these attributes in detail. io_type this is used to set the sysio standard for an i/o. the v ccio required to set these i/o standards are embedded in the attribute names itself. there is no separate attribute to set the v ccio requirements. table 9-7 lists the available i/o types. 9-8 latticeecp2/m sysio lattice semiconduct or usage guide table 9-7. io_type attribute values opendrain lvcmos and lvttl i/o standards can be set to open drain configuration by using the opendrain attribute. values: on, off default: off drive the drive attribute will set the programma ble drive strength for the output st andards that have programmable drive capability sysio signaling standard io_type default lvcmos25 lv d s 2 . 5 v lv d s 2 5 rsds rsds emulated lvds 2.5v lvds25e 1 bus lvds 2.5v blvds25 1 lvpecl 3.3v lvpecl33 1 hstl18 class i and ii hstl18_i, htsl18_ii differential hstl 18 class i and ii hstl18d_i, hstl18d_ii hstl 15 class i hstl15_i differential hstl 15 class i hstl15d_i sstl 33 class i and ii sstl33_i, sstl33_ii differential sstl 33 class i and ii sstl33d_i, sstl3d_ii sstl 25 class i and ii sstl25_i,sstl25_ii differential sstl 25 class i and ii sstl25d_i, sstl25d_ii sstl 18 class i and ii sstl18_i, sstl18_ii differential sstl 18 class i sstl18d_i,sstl18d_ii lvttl lvttl33 3.3v lvcmos lvcmos33 2.5v lvcmos lvcmos25 1.8v lvcmos lvcmos18 1.5v lvcmos lvcmos15 1.2v lvcmos lvcmos12 3.3v pci pci33 1. these differential standards are im plemented by using a complementary ? lvcmos driver with external resistor pack. 9-9 latticeecp2/m sysio lattice semiconduct or usage guide table 9-8. drive settings pullmode the pullmode attribute is available for all the lvtll and lvcmos inputs and outputs. this attribute can be enabled for each i/o independently. values: up, down, none, keeper default: up table 9-9. pullmode values pciclamp pci33 inputs on the bottom of the device (for latticeecp2) or on the left and bottom sides of the device (for latticeecp2m) have an optional pci clamp that is enable d via the pciclamp attribute. the pciclamp is also available for all lvcmos33 and lvttl inputs. values: on, off default: off table 9-10. pciclamp values slewrate the slewrate attribute is available for all lvttl and lvcmos output drivers. each i/o pin has an individual slew rate control. this allows a designer to specify slew rate control on a pin-by-pin basis. values: fast, slow default: fast output standard drive (ma) default (ma) hstl15_i/ hstl15d_i 4, 8 8 hstl18_i/ hstl18d_i 8, 12 12 sstl25_i/ sstl25d_i 8, 12 8 sstl25_ii/ sstl25d_ii 16, 20 16 sstl18_ii/sstl18d_ii 8, 12 12 lvcmos12 2, 6 6 lvcmos15 4, 8 8 lvcmos18 4, 8, 12, 16 12 lvcmos25 4, 8, 12, 16, 20 12 lvcmos33 4, 8, 12, 16, 20 12 lvttl 4, 8, 12, 16, 20 12 pull options pullmode value pull-up (default) up pull-down down bus keeper keeper pull off none input type pciclamp value pci33 on lvcmos33 off (default), on lvttl off (default), on 9-10 latticeecp2/m sysio lattice semiconduct or usage guide fixeddelay the fixeddelay attribute is available to each input pin. this attribute, when enabled, is used to achieve zero hold time for the input registers when using global clock. this attribute can only be assigned in the hdl source. values: true, false default: false inbuf by default, all the unused input buffers are disabled. the inbuf attribute is used to enable the unused input buffers when performing a boundary scan test. this is a global attribute and can be globally set to on or off. values: on, off default: off din/dout this attribute can be used to assign i/o registers. using din will assert an i nput register and using the dout attri- bute will assert an output register. by def ault, the software will try to assign the i/o registers, if a pplicable. the user can turn this off by using the synthe sis attribute or by using the preferen ce editor of the isplever software. these attributes can only be applied to registers. loc this attribute can be used to make pin assignments to the i/o ports in the design. this attributes is only used when the pin assignments are made in hdl source. designers can al so assign pins directly using the gui in the prefer- ence editor of the isplever software. the appendices explain this in further detail. design considerations and usage this section discusses some of the design rules and considerations that must be taken into account when design- ing with the latticeecp2/m sysio buffer banking rules ?if v ccio or v ccj for any bank is set to 3.3 v, it is recommended that it be connected to the same power supply as v ccaux, thus minimizing leakage. ?if v ccio or v ccj for any bank is set to 1.2v, it is recommended that it be connected to the same power supply as v cc , thus minimizing leakage. ? when implementing ddr memory interfaces, the v ref1 of the bank is used to provide reference to the interface pins and cannot be used to power any other referenced inputs. ? only the bottom banks for latticeecp2 (banks 4 and 5) or left and bottom banks for latticeecp2m (banks 4, 5, 6 and 7) will support pci clamps. ? all legal input buffers should be independent of bank v ccio, except for 1.8v and 1.5v buffers, which require a bank v ccio of 1.8v and 1.5v. differential i/o rules ? all banks can support lvds input buffers. only the bank s on the right and left side s (banks 2, 3, 6 and 7) will support true differential output buffer s. the banks on the top and bottom will support the lvds input buffers but will not support true lvds outputs. the user can use emulated lvds output buffers on these banks. ? all banks support emulated differential buffers using external resistor pack and complementary lvcmos drivers. ? only 50% of the i/os on the left and right sides can pr ovide lvds output buffer capability. lvds can only be assigned to the true pad. the ispl ever design tool will automatically assign the other i/os of the differential pair to the complementary pad. refer to the device data sheet to see the pin listings for all lvds pairs. 9-11 latticeecp2/m sysio lattice semiconduct or usage guide assigning v ref1 / v ref2 groups for referenced inputs each bank has two dedicated v ref input pins, v ref1 and v ref2 . designers can group buffers to a particular v ref rail, v ref1 or v ref2 . this grouping is done by assigning a pgroup vref preference along with the locate pgroup preference. preference syntax pgroup 9-12 latticeecp2/m sysio lattice semiconduct or usage guide lvpecl all the sysio buffers will support lvpec l inputs. lvpecl outputs are supp orted using comple mentary lvcmos driver with external resistors. please refer to the latticeecp2/m family data sheet for a detailed explanation of lvpecl implementation. differential sstl and hstl all single-ended sysio buffers pairs support differential sstl and hstl. please refer to the latticeecp2/m family data sheet for a detailed explanation of differential hstl and sstl implementation. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com revision history date version change summary february 2006 01.0 initial release. september 2006 01.1 updated to include latticeecp2m support. april 2007 01.2 updated support ed output standards table. june 2007 01.3 updated v ref1 for ddr memory interface section. june 2007 01.4 updated sysio standards supported by bank table. updated banking rules bullet list. june 2007 01.5 updated power supplies table. april 2008 01.6 updat ed latticeecp2m sysio banking diagram. february 2009 01.7 updated i/o standards supported by bank table. june 2010 01.8 updated screen shots in appendix b. updated document for lattice diam ond design software support. 9-13 latticeecp2/m sysio lattice semiconduct or usage guide appendix a. hdl attributes for synplicity ? and precision ? rtl synthesis using these hdl attributes, designers can assign the sysio attributes directly in their source. the attribute defini- tion and syntax for the appropriate synthesis vendor must be used. below are a list of all the sysio attributes, syn- tax and examples for precision rtl synthesis and synplicity. this section only lists the sysio buffer attributes for these devices. you can refer to the precision rtl synthesi s and synplicity user manuals for a complete list of syn- thesis attributes. these manuals are available through the isplever software help system. vhdl synplicity/precis ion rtl synthesis this section lists syntax and examples for all the sysio at tributes in vhdl when using the precision rtl synthesis or synplicity synthesis tools. syntax table 9-11. vhdl attribute syntax for synplicity and precision rtl synthesis examples io_type --***attribute declaration*** attribute io_type: string; --***io_type assignment for i/o pin*** attribute io_type of porta: signal is ?pci33?; attribute io_type of portb: signal is ?lvcmos33?; attribute io_type of portc: signal is ?lvds25?; opendrain --***attribute declaration*** attribute opendrain: string; --***drive assignment for i/o pin*** attribute opendrain of portb: signal is ?on?; attribute syntax io_type attribute io_type: string; attribute io_type of pinname : signal is ?io_type value?; opendrain attribute opendrain: string; attribute opendrain of pinname: signal is ?opendrain value?; drive attribute drive: string; attribute drive of pinname: signal is ?drive value?; pullmode attribute pullmode: string; attribute pullmode of pinname: signal is ?pullmode value?; pciclamp attribute pciclamp: string; attribute pciclamp of pinname: signal is ?pciclamp value?; slewrate attribute pullmode: string; attribute pullmode of pinname: signal is ?slewrate value?; fixeddelay attribute fixeddelay: string; attribute fixeddelay of pinname: signal is ? fixeddelay value ?; din attribute din: string; attribute din of pinname : signal is ? ?; dout attribute dout: string; attribute dout of pinname: signal is ? ?; loc attribute loc: string; attribute loc of pinname: signal is ?pin_locations?; 9-14 latticeecp2/m sysio lattice semiconduct or usage guide drive --***attribute declaration*** attribute drive: string; --***drive assignment for i/o pin*** attribute drive of portb: signal is ?20?; pullmode --***attribute declaration*** attribute pullmode : string; --***pullmode assignment for i/o pin*** attribute pullmode of porta: signal is ?down?; attribute pullmode of portb: signal is ?up?; pciclamp --***attribute declaration*** attribute pciclamp: string; --***pullmode assignment for i/o pin*** attribute pciclamp of porta: signal is ?on?; slewrate --***attribute declaration*** attribute slewrate : string; --*** slewrate assignment for i/o pin*** attribute slewrate of portb: signal is ?fast?; fixeddelay --***attribute declaration*** attribute fixeddelay: string; --*** slewrate assignment for i/o pin*** attribute fixeddelay of portb: signal is ?true?; din/dout --***attribute declaration*** attribute din : string; attribute dout : string; --*** din/dout assignment for i/o pin*** attribute din of input_vector: signal is ? ?; attribute dout of output_vector: signal is ? ?; loc --***attribute declaration*** attribute loc : string; --*** loc assignment for i/o pin*** attribute loc of input_vector: signal is ?e3,b3,c3 ?; 9-15 latticeecp2/m sysio lattice semiconduct or usage guide verilog synplicity this section lists syntax and examples for all the sysio attributes in verilog using the synplicity synthesis tool. syntax table 9-12. verilog synplicity attribute syntax examples //io_type, pullmode, slewrate and drive assignment output portb /*synthesis io_type=?lvcmos33? pullmode =?up? slewrate =?fast? drive =?20?*/; output portc /*synthesis io_type=?lvds25? */; //opendrain output porta /*synthesis opendrain =?on?*/; //pciclamp output porta /*synthesis io_type=?pci33? pullmode =?pciclamp?*/; // fixeddelay input load /* synthesis fixeddelay=?true? */; // place the flip-flops near the load input input load /* synthesis din=?? */; // place the flip-flops near the outload output output outload /* synthesis dout=?? */; //i/o pin location input [3:0] data0 /* synthesis loc=?e3,b1,f3?*/; //register pin location reg data_in_ch1_buf_reg3 /* synthesis loc=?r40c47? */; //vectored internal bus reg [3:0] data_in_ch1_reg /*synthesis loc =?r40c47,r40c46,r40c45,r40c44? */; attribute syntax io_type pintype pinname /* synthesis io_type=?io_type value?*/; opendrain pintype pinname /* synthesis opendrain =?opendrain value?*/; drive pintype pinname /* synthesis drive=?drive value?*/; pullmode pintype pinname /* synthesis pullmode=?pullmode value?*/; pciclamp pintype pinname /* synthesis pciclamp =? pciclamp value?*/; slewrate pintype pinname /* synthesis slewrate=?slewrate value?*/; fixeddelay pintype pinname /* synthesis fixeddelay=?fixeddelay value?*/; din pintype pinname /* synthesis din=? ?*/; dout pintype pinname /* synthesis dout=? ?*/; loc pintype pinname /* synthesis loc=?pin_locations ?*/; 9-16 latticeecp2/m sysio lattice semiconduct or usage guide verilog precision this section lists syntax and examples for all the sysio attributes in verilog using the precision rtl synthesis tool. syntax table 9-13. verilog precision attribute syntax examples //****io_type *** //pragma attribute porta io_type pci33 //pragma attribute portb io_type lvcmos33 //pragma attribute portc io_type sstl25_ii //*** opendrain *** //pragma attribute portb opendrain on //pragma attribute portd opendrain off //*** drive *** //pragma attribute portb drive 20 //pragma attribute portd drive 8 //*** pullmode*** //pragma attribute portb pullmode up //*** pciclamp*** //pragma attribute portb pciclamp on //*** slewrate *** //pragma attribute portb slewrate fast //pragma attribute portd slewrate slow // ***fixeddelay*** // pragma attribute load fixeddelay true //***loc*** //pragma attribute portb loc e3 attribute syntax io_type //pragma attribute pinname io_type io_type value opendrain // pragma attribute pinname opendrain opendrain value drive // pragma attribute pinname drive drive value pullmode // pragma attribute pinname io_type pullmode value pciclamp // pragma attribute pinname pciclamp pciclamp value slewrate // pragma attribute pinname io_type slewrate value fixeddelay // pragma attribute pinname io_type fixeddelay value loc // pragma attribute pinname loc pin_location 9-17 latticeecp2/m sysio lattice semiconduct or usage guide appendix b. sysio attributes using the isplever design planner user interface designers can assign sysio buffer attributes using the de sign planner spreadsheet view gui available in the isp- lever design tool. if you are using lattice diamond? design software, refer to appendix d. the pin attribute sheet list all the ports in a design and all the available sysio attributes as preferences. by clicking on each of these cells, a list of all the valid i/o preference for that port is displayed. each column takes precedence over the next. therefore, when a particular io_t ype is chosen, the drive, pullmode and slewrate columns will only list the valid combinations for that io_type. the pin locations can be locked using the pin location column of the pin attribute sheet. right-clicking on a ce ll will list the available pin locations. th e preference editor will also conduct a drc check to search for any incorrect pin assignments. designers can enter din/dout preferences using the cell attributes sheet of the preference editor. all the prefer- ences assigned using the preference editor are written into the preference file (.prf). figures 2 and 3 show the pin attribute sheet and the cell attribute sheet views of the preference editor. for further information on how to use the preference editor, refer to the isplever help documentation in the help menu option of the software. figure 9-2. pin attributes tab figure 9-3. cell attributes tab 9-18 latticeecp2/m sysio lattice semiconduct or usage guide appendix c. sysio attributes us ing preference file (ascii file) designers can enter sysio attributes directly in the preference (.prf) file as sysio buffer preferences. the prf file is an ascii file containing two separate sections: a schematic section for those preferences created by the mapper or translator, and a user section for preferences entered by t he user. user preferences can be written directly into this file. the synthesis attributes appear between the schematic start and schematic end of the file. the sysio buffer preferences can be entered after the schematic end line using the preference file syntax. below are a list of sysio buffer preference syntax and examples. iobuf this preference is used to assign the attribute io_type, pullmode, slewrate and drive. syntax iobuf [allports | port 9-19 latticeecp2/m sysio lattice semiconduct or usage guide this command places the component pfu1 on the site named r1c7: locate comp ?pfu1? site ?r1c7?; this command places bus1 on row 3 and bus2 on col4 locate bus ?bus1? row 3; locate bus ?bus2? col 4; use din cell this preference specifies the given register to be used as an input flip-flop. syntax use din cell 9-20 latticeecp2/m sysio lattice semiconduct or usage guide locate pgroup ? vref_pg1? bank 2; locate pgroup ? vref_pg2? bank 2; 9-21 latticeecp2/m sysio lattice semiconduct or usage guide appendix d. assigning sysio attrib utes using lattice diamond spread - sheet view sysio buffer attributes can be assigned using the spreadsheet view available in the lattice diamond design soft- ware. the port assignments sheet lists all the ports in a des ign and all the available sysio attributes in multiple col- umns. click on each of these cells for a list of all the valid i/o preferences for that port. each column takes precedence over the next. therefore, when you choose a particular io_type, the columns for the drive, pull- mode, slewrate and other attributes will only list the valid entries for that io_type. pin locations can be locked using the pin column of the port assignments sheet or using the pin assignments sheet. you can right-click on a cell and go to assign pins to see a list of available pins. the spreadsheet view also has an option to run a drc check to check for any incorrect pin assignments. you can enter the din/ dout preferences using the cell mapping tab. all the preferences assigned using the spreadsheet view are written into the logical preference file (.lpf). figure 9-4 shows the port assignments sheet of the spreadsheet view. for further information on how to use the spreadsheet view, refer to the diamond help documentation, available in the help menu option of the software. figure 9-4. port attributes tab of the spreadsheet view users can create a vref pin using the spreadsheet view as shown in figure 9-5 and then assign vref for a bank using the vref column in the ports assignment ta b of the spreadsheet view as shown in figure 9-6. see the diamond online help for a detailed description of this setting. 9-22 latticeecp2/m sysio lattice semiconduct or usage guide figure 9-5. creating a vref in spreadsheet view figure 9-6. assigning vref for an input port in spreadsheet view www.latticesemi.com 10-1 tn1103_02.1 june 2010 technical note tn1103 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction this user?s guide describes the cloc k resources available in the latticeecp2? and latticeecp2m? device archi- tectures. details are provided for primary clocks, secondary clocks and edge clocks, as well as clock elements such as plls, dlls, clo ck dividers and more. the number of plls and dlls for each package can be found in tables 10-1 and 10-2. table 10-1. number of plls and dlls: latticeecp2 family table 10-2. number of plls, dlls and serdes: latticeecp2m family clock/control distribution network the latticeecp2/m family provides global clock distributi on in the form of eight quadrant-based primary clocks and flexible secondary clocks. the devices also provide tw o edge clocks on each edge of the device. other clock sources include clock input pins, internal nodes, plls, dlls, slave delay lines and clock dividers. device description ecp2-6 ecp2-12 ecp2-20 ecp2-35 ecp2-50 ecp2-70 number of spllsstandard pll (subset of gpll)000024 number of gpllsgeneral purpose pll 222222 number of dllsgeneral purpose dll 222222 number of dqsdlls dll for ddr applications 222222 device description ecp2m-20 ecp2m-35 ecp2m-50 ecp2m-70 ecp2m-100 number of spllsstandard pll (subset of gpll)66666 number of gpllsgeneral purpose pll 22222 number of dllsgeneral purpose dll 22222 number of dqsdlls dll for ddr applications 22222 serdes 4-channel quad serdes 11244 latticeecp2/m sysclock pll/dll design and usage guide 10-2 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide latticeecp2/m top level view figure 10-1 shows the primary clocking structure of the latticeecp2-50 device. figure 10-1. latticeecp2-50 clocking structure figure 8-2 illustrates the primary cloc king structure of the latticeecp2m-50 device. the figure shows two serdes blocks. the edge clocks on the top and bottom sides stop when they reach the serdes block boundary. other members of the latticeecp2m family have a similar structure, except for the number of serdes blocks. figure 10-2. latticeecp2m-50 clocking structure gpll sysio bank 5 sysio bank 4 sysio bank 0 sysio bank 1 sysio bank 6 sysio bank 7 sysio bank 3 sysio bank 2 spll dll dll quadrant tl quadrant tr quadrant br quadrant bl spll gpll primary clocks eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 dqsdll clkdiv clkdiv dqsdll eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 clkdiv clkdiv gpll spll dll dqsdll spll serdes pcs serdes pcs quadrant tl quadrant tr quadrant br quadrant bl primary clocks sysio bank 6 sysio bank 7 sysio bank 5 sysio bank 4 sysio bank 0 sysio bank 1 sysio bank 3 sysio bank 2 spll gpll spll dll dqsdll spll spll 10-3 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide primary clocks each quadrant receives up to eight primary clocks. two of these clocks provide the dynamic clock selection (dcs) feature. the six primary clocks without dcs can be spec ified in the spreadsheet vi ew in the isplever design planner (or tools > spreadsheet view in the lattice diamond? design software) as ?primary pure? and the two dcs clocks as ?primary-dcs?. the sources of the primary clocks are: ? pll outputs ? dll outputs ? clkdiv outputs ? dedicated clock pins ? internal nodes ? serdes tx_h_clk (latticeecp2m only) secondary clocks the latticeecp2/m secondary clocks are a flexible region-based clocking resource. each region can have four independent clock inputs. as a regional resource, it can cross the primary clock quadrant boundaries. there are eight secondary clock muxes per region. each mux has inputs from four different sources. three of these are from internal nodes. the fourth input comes from a primary clock pin. the input sources are not necessarily located in the same region as the mux. this structure enables global usage of secondary clocks. the sources of secondary clocks are: ? dedicated clock pins on right and left sides of device (pclkt2, pclkt3, pclkt6, pclkt7) ? internal nodes edge clocks the latticeecp2/m has two edge clocks per side. these clocks, which have low injection times and skew, are used to clock i/o registers. the edge clock (e clk) resources are designed for high speed i/o interfaces with high fanout capability. refer to appendix b fo r detailed connectivity information. the sources of the edge clocks are: ? left and right edge clocks ? dedicated clock pins ? pll outputs ? dll outputs ? internal nodes ? top and bottom edge clocks ? dedicated clock pins ? internal nodes eclk can directly drive the secondary clock resources an d general routing resources. this means that an eclk source clock can also route to the primary clock net through general routing at the same time. figure 10-3 describes the secondary clock and edge clock structure. 10-4 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-3. latticeecp2-50 secondary clocks and edge clocks figure 10-4. latticeecp2m-50 secondary clocks and edge clocks note on primary clocks the clkop must be used as the feedback source to optimize the pll performance. gpll sysio bank 5 sysio bank 4 sysio bank 0 sysio bank 1 sysio bank 6 sysio bank 7 sysio bank 3 sysio bank 2 spll dll dll spll gpll eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 eclk2 eclk1 dqsdll dqsdll secondary clock secondary clock region 2 secondary clock region 5 region 1 secondary clock region 6 secondary clock region 3 secondary clock region 4 secondary clock region 7 secondary clock region 8 dsp row dsp row ebr row sysio bank 5 sysio bank 4 sysio bank 0 sysio bank 1 sysio bank 6 sysio bank 7 sysio bank 3 sysio bank 2 spll dqsdll spll spll gpll dll spll serdes pcs dqsdll spll spll gpll dll eclk2 eclk1 serdes pcs eclk1 eclk2 eclk2 eclk1 eclk2 eclk1 secondary clock secondary clock region 2 secondary clock region 5 region 1 secondary clock region 6 secondary clock region 3 secondary clock region 4 secondary clock region 7 secondary clock region 8 dsp row dsp row ebr row 10-5 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide most designers use pll for clock tree injection removal mode and the clkop should be assigned to the primary clock. this is done automatically by the software unless the user specifies otherwise. clkop can route to clk0 to clk5 only and clkos/clkok can route to all primary clocks (clk0 to clk7). when clk6 or clk7 is used as a primary clock and there is only one clock input to the dcs, the dcs is assigned as a buffer mode by the software. see the dcs section of this document for further information. specifying clocks in the design tools if desired, designers can specify the clock resources, primary, secondary or edge to be used to distribute a given clock source. figure 10-4 illustrates ho w this can be done in t he spreadsheet view in the isplever design plan- ner (or tools > spreadsheet view in diamond). alternatively the prefer ence file can be used, as discussed in appendix c. primary-pure and primary-dcs primary clock net can be assigned to either primary-pure (clk0 to clk5) or primary-dcs (clk6 and clk7). global primary clock and quadrant primary clock global primary clock if a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock. there are six global primary/pure clocks an d two global primary/dcs clocks available. quadrant primary clock any primary clock may be assigned to a quadrant clock. the clock may be assigned to a single quadrant or to two adjacent quadrants (not diagonally adjacent). when a quadrant clock net is used, the user must ensure that the registers each clock drives can be assigned in that quadrant without any routing issues. in the quadrant primary clocking scheme, the maximum number of primary clocks is 32, as long as all the pri- mary clock sources are available. figure 10-5. design planner spreadsheet view (see appendix d figure 10-39 for diamond equivalent) note on edge clocks refer to appendix a for detailed clock network diagrams. 10-6 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide sysclock pll the latticeecp2/m pll provides features such as clock injection delay removal, frequency synthesis, phase/duty cycle adjustment, and dynamic delay adjustment. figure 10-6 shows the block diagram of the pll. figure 10-6. pll block diagram functional description pll divider and delay blocks input clock (clki) divider the clki divider is used to control the input clock frequency into the pll block. the divider setting directly corre- sponds to the divisor of the output clock. the input and output of the input divider must be within the input and out- put frequency ranges specified in the device data sheet. feedback loop (clkfb) divider the clkfb divider is used to divide the feedback signal. effectively, this multiplies the output clock, because the divided feedback must speed up to match the input frequency into the pll block. the pll block increases the out- put frequency until the divided feedback frequency equals the input frequency. the input and output of the feed- back divider must be within the input and output frequency ranges specified in the device data sheet. delay adjustment the delay adjust circuit provides programmable clock delay. the programmable clock delay allows for step delays in increments of 130ps (nominal) for a total of 1.04ns, lagging or leading. the time delay setting has a tolerance. see the device data sheet for details. under this mode, clkop, clkos and clkok are identically affected. the delay adjustment has two modes of operation: ? static delay adjustment : in this mode, the user-selected delay is configured at power-up. ? dynamic delay adjustment (dda) : in this mode, a simple bus is used to configure the delay. the bus signals are available to the general purpose fpga. output clock (clkop) divider the clkop divider serves the dual purposes of squaring the duty cycle of the vco output and scaling up the vco frequency into the 640mhz to 1280mhz range to minimize jitter. the clkop divider values are the same whether or not clkos is used. clkok divider the clkok divider acts as a source for the global clock nets. it divides the clkop signal of the pll by the value of the divider to produce a lower frequency clock. phase adjustment and duty cycle select dda control ports clki divider clkfb divider lock detect rst pfd delay adjust vco/ loop filter clkfb clki lock clkop clkop divider clkos clkok rstk phase/duty select clkok divider dphase/ dduty control ports pllcap* internal feedback 10-7 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide users can program clkos with phase and duty cycle options. phase adjustment can be done in 22.5 o steps. the duty cycle resolution is 1/16th of a period. however, 1/16th and 15/16th duty cycle options are not supported to avoid minimum pulse violation. dynamic phase adjustment (dphase) a nd dynamic duty cycle (dduty) select with latticeecp2/m device families, users can control t he phase adjustment and duty cycle select in dynamic mode. when this mode is selected, both the phase adjust ment and duty cycle select must be in dynamic mode. if only one of the features is to be used in dynamic mode, the other control inputs can be set with the fixed logic lev- els desired. external capacitor an optional external capacitor can be used with pl ls to accommodate low frequency input clocks. see the optional external capacitor section of this document for further information. pll inputs and outputs clki input the clki signal is the reference clock for the pll. it must conform to the specifications in the latticeecp2/m fam- ily data sheet for the pll to operate correctly. the clki can be derived from a dedicated dual-purpose pin or from routing. rst input the pll reset occurs under two conditions. at power-up an internal power-up reset signal from the configuration block resets the pll. the user-controlled pll reset signal rst is provided as part of the pll module that can be driven by an internally generated reset function or a pin. this rst signal resets all internal pll counters, flip-flops (including m-dividers), and the charge pump. the m-divider reset synchronizes the m-divider output to the input clock. when rst goes inactive, the pll will st art the lock-in process, and will take the t lock time to complete the pll lock. figure 10-7 shows the timing diagram of the rst input. rst is active high. the reset signal is optional. figure 10-7. rst input timing diagram figure 10-8 shows the timing relationship between rst and the clki divider output. figure 10-8. rst input and clki divider ou tput timing diagram (example: clki_div = 4) t lock t rst pll_rst lock 1.5 ns min. t rst clki 1 cycle clki divider output rstrec 10-8 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide rstk input rstk is the reset input for the k-divider. the k-divider reset is used to synchronize the k-divider output clock to the input clock. the latticeecp2/m has an optional gearbox in the i/o cell for both outputs and inputs. the k- divider reset is useful for the gearbox implementation. rstk is active high. figure 10-9 shows the timing relationship between rstk and clkok (example: clkok_div = 4) figure 10-9. rstk input and clkok divider ou tput timing diagram (example: clkok_div = 4) clkfb input the feedback signal to the pll, which is fed through the feedback divider, can be derived from the primary clock net (clkop), a preferred pin, directly from the clkop divider (internal feedback) or from general routing. external feedback allows the designer to compensate for board-level clock alignment. clkop output the sysclock pll main clock output, clkop, is a signal available for selection as a primary clock and an edge clock. this clock signal is available at the clk_out pin. clkos output with phase and duty cycle select the sysclock pll auxiliary clock output, clkos, is a signal available for selection as a primary clock and an edge clock. the clkos is used when phase shift and/or duty cycle adjustment is desired. the programmable phase shift allows for different phases in increments of 22.5. the duty select feature provides duty selection in 1/16th of the clock period. this feature is also supported in dynamic control mode. clkok output with lower frequency the clkok is used when a lower frequency is desired. this signal is available for selection as a primary clock. dynamic delay control/dynamic phase adjustment/dynamic duty cycle detailed information about these features are described later in this document. the i/o ports for these features are illustrated in table 10-3. table 10-3. dynamic delay adjust and dynamic phase and duty cycle adjust ports lock output the lock output provides information about the status of the pll. after the device is powered up and the input clock is valid, the pll will achieve lock within the specified lo ck time. once lock is achieved, the pll lock signal will parameter i/o description ddamode i dda (dynamic delay adjust) mode. 1": pin control (dynamic), ?0?: fuse control (static) ddaizr i dda delay zero. ?1?: delay = 0, ?0?: delay = on ddailag i dda lag/lead. ?1?: lead, ?0?: lag ddaidel[2:0} i dda delay step value dpamode i dpa (dynamic phase adjust/duty cycle select) mode. 1": pin pin control (dynamic), ? ?0?: fuse c ontrol (static) dphase[3:0] i dpa phase adjust inputs dduty[3:0] i dpa duty cycle select inputs rstk clki 1 cycle clkok divider output t rstrec 10-9 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide be asserted. if, during operation, the input clock or feed back signals to the pll become invalid, the pll will lose lock. however, when the input clock completely stops, the lo ck output will remain in its la st state, since it is inter- nally registered by this clock. it is recommended to assert pll rst to re-synchronize the pll to the reference clock. the lock signal is available to the fpga routing to implement generation of rst. simulation models take several reference clock cycles fr om rst release to lock high. pllcap this port is not included in the software module. instead, it is hard-wired to the pllcap pin of the device. see the optional external capacitor section of this document for further information. pll attributes the pll utilizes several attributes that allow the configuration of the pll th rough source constraints and prefer- ence files. the following section details these attributes and their usage. fin the input frequency can be any value within the specified frequency range based on the divider settings. clki_div, clkfb_div, clkop_div, clkok_div these dividers determine the output frequencies of each output clock. the user is not allowed to input an invalid combination. this is determined by the input frequency, the divi ders and the pll specifications. note: unlike plls in the latticeecp?, latticeec?, la tticexp? and macoxo? devices, the clkop divider val- ues are the same whether or not clkos is used. the clkop_div value is calculated to maximize the f vco within the specified range based on fin and clkop_freq in conjunction with clki_div and clkfb_div values. these value settings are designed so that the output clock duty cycle is as close to 50% as possible. frequency_pin_clki, frequency_pin_clkop, frequency_pin_clkok these input and output clock frequencies determine the divider values. clkop frequency tolerance when the desired output frequency is not achievable, the frequency tolerance of the clock output may be entered. phaseadj (phase shift adjust) the phaseadj attribute is used to select phase shift for the clkos output. the phase adjustment is program- mable in 22.5 increments. duty (duty cycle) the duty attribute is used to select the duty cycle for clkos output. the duty cycle is programmable at 1/16th of the period increment. steps 2 to 14 are supported. 1/16th and 15/16th duty cycles are not supported to avoid the minimum pulse width violation. fb_mode there are three sources of feedback signals that can drive the clkfb divider: internal, clkop (clock tree) and user clock. clkop (clock tree) feedback is used by default. internal feedback takes the clkop output at the clkop divider output (clkintfb) before the clock tree to minimize the feedback path delay. user clock feed- back is driven from the dedicated pin, clock pin or user specified internal logic. delay_cntl this attribute is designed to select the delay adjustment mode. if the attribute is set to ?dynamic? the delay con- trol switches between dynamic and static, depending upon the input logic of the ddamode pin. if the attribute is set to ?static?, dynamic delay in puts are ignored in this mode. 10-10 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide phase/duty_cntl this attribute is designed to select the phase adjustment/duty cycle select mode. if the attribute is set to ?dynamic? the phase adjustment/duty cycle select control switches between dynamic and static, depending upon the input logic of the dpamode pin. if the attribute is set to ?static?, dynamic phase adjustment/duty cycle select inputs are ignored in this mode. clkos/clkok select users select these output clocks onl y when they are used in the design. clkop/clkos/clkok bypass these bypasses are enabled if set. the clki is routed directly to the corresponding output clock. reset/rstk select users select these reset signals only when they are used in the design. latticeecp2/m pll modules when the user creates a pll module using ipexpress, the module will consis t of a wrapper aroun d the pll library element and any additional logic required for the module. figure 10-10 shows a diagram of a typical pll module. the module port names can be different than the library el ement is some cases. the user will see the module port names in the ipexpress window and also in the source code file for the generated module. these are the ports that will be connected in the user's design. ip express also creates an instantiation te mplate file that shows the user how to instantiate the pll module in their design. the user can import the *.lpc (or *.ipx for diamond) file into their project or the generated source code file. figure 10-10. latticeecp2/m typical pll module generated by ipexpress the pll module shown in figure 10-10 represents an ex ample where the user has chosen to use the clkop and clkos ports, with a pll reset signal, pll lock signal, and dynamic phase and dynami c duty cycle. it also uses clkop feedback so the software will connect the clkop signal to the clkfb po rt and use the primary clock tree to route this signal. the user would connect thei r signals to the clki, rst, dpamode, dphase[3:0], dduty[3:0], clkop, clkos, and lock signals. latticeecp2/m pll li brary definitions all latticeecp2/m devices support two general purpose p lls (gplls) which are full-featured plls. in addition, some of the larger devices have two to six standard plls (splls) that have a subset of the gpll functionalities. two pll library elements are defined for latticeecp2/m pll implementation. figure 10-11 shows the latticeecp2/m pll library symbols. the gpll may be configured as either eplld or ehxplld. the spll can be configured as eplld only. rst clkop rstk clkos clki clkok clkfb lock dpamode clkintfb drpai[3:0] dfpai[3:0] additional logic rst clki dpamode dphase[3:0] clkop clkos lock eplld dduty[3:0] 10-11 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-11. latticeecp 2/m pll library symbols dynamic delay adjustm ent (ehxplld only) the dynamic delay adjustment is cont rolled by the ddamode input. when th e ddamode input is set to ?1?, the delay control is done through the inputs, ddaizr, ddailag and ddaidel(2:0). for this mode, the attribute ?delay_cntl? must be set to ?dynamic?. table 10-4 shows the delay adjustment values based on the attri- bute/input settings. in this mode, the pll may come out of lock due to the abrupt change of phase. rst must be asserted to re-lock the pll. upon de-assertion of rst, the pll will start the lock-in process and will take the t lock time to complete the pll lock. table 10-4. delay adjustment dynamic phase/duty mode this mode sets both dynamic phase adjustment and dynamic duty select at the same time. there are two modes, ?dynamic phase and dynami c duty? and ?dynamic phase and 50% duty?. ddamode = 1: dynamic delay adjustment delay 1 tdly = 130 ps (nominal) ddamode = 0 ddaizr ddailag ddaidel[2:0] equivalent fdel value 0 1 111 lead 8 tdly -8 0 1 110 lead 7 tdly -7 0 1 101 lead 6 tdly -6 0 1 100 lead 5 tdly -5 0 1 011 lead 4 tdly -4 0 1 010 lead 3 tdly -3 0 1 001 lead 2 tdly -2 0 1 000 lead 1 tdly -1 1 don?t care don?t care no delay 0 0 0 000 lag 1 tdly 1 0 0 001 lag 2 tdly 2 0 0 010 lag 3 tdly 3 0 0 011 lag 4 tdly 4 0 0 100 lag 5 tdly 5 0 0 101 lag 6 tdly 6 0 0 110 lag 7 tdly 7 0 0 111 lag 8 tdly 8 ehxplld rst rstk clki clkfb dpamode drpai[3:0] dfpai[3:0] ddamode ddaizr ddailag ddaidel[2:0] clkop clkos clkok lock eplld rst rstk clki clkfb dpamode drpai[3:0] dfpai[3:0] clkop clkos clkok lock clkintfb clkintfb 10-12 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide to use dynamic phase adjustment with a fixed duty cycle, simply set the dduty[3:0] inputs to the desired duty cycle value. figure 10-12 illustrates an example circuit. this example assumes the user-desired duty cycle is 3/16. figure 10-12. example dynamic phase adjustment set-up with duty cycle fixed to 3/16 dynamic phase adjustment /duty cycle select phase adjustment settings are described in table 10-5. table 10-5. dynamic phase adjustment settings duty cycle select settings are described in table 10-6. dphase[3:0] equivalent to phaseadj in static mode 0000 0 0001 22.5 0010 45 0011 67.5 0100 90 0101 112.5 0110 135 0111 157.5 1000 180 1001 202.5 1010 225 1011 247.5 1100 270 1101 292.5 1110 315 1111 337.5 dphase[3] dphase[2] dphase[1] dphase[0] dpamode pll dduty[3] dduty[2] dduty[1] dduty[0] dphase[3:0] 10-13 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide table 10-6. dynamic duty cycle select settings optional external capacitor an optional external capacitor can be used with both the ehxplld and the eplld to change the frequency response of the on-chip loop filter. when an external capacitor is used, the frequency at the phase detector inputs (fpd) can be as low as 2mhz, allowing the plls to extend the low-end of their operating ranges. using the external capacitor will limit the high end of the pll operating range as shown in the latticeecp2/m family data sheet . ipexpress? checks the phase detector frequency to determine if an external capacitor is required. the allowable ranges for the pll parameters with and without the external capacitor are described in the latticeecp2/m family data sheet . recommended optional external capacitor specifications value: 5.6 nf, +/- 20% type: ceramic chip capacitor, npo dielectric package: 1206 or smaller each device has two external capacitor pins, one for the left side plls and one for the right side plls. these pins are in fixed locations. they are dedicated function pins that are not shared with user i/os. when an external capacitor pin is used by a pll on one side of the device, it cannot be used by any other plls on the same side of the device. this means that a maximum of two plls per device, one on the left side and one on the right side, can have external capacitors attached. dduty[3:0] equivalent to duty in static mode (1/16 of period) comment 0000 0 not supported 0001 1 not supported 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 not supported 10-14 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-13. external capacitor usage pll usage in ipexpress ipexpress is used to create and configure a pll. designers use the graphical user interface to select parameters for the pll. the result is an hdl model to be used in the simulation and synthesis flow. figure 10-14 shows the main window when pll is selected. the only entry required in this window is the module name. other entries are set to the project settings. these entries may be changed if desired. after entering the module name, click on customize to open the configuration tab window as shown in figure 10-15. figure 10-14. ipexpress main window (see appendix d figure 10-40 for diamond equivalent) configuration tab the configuration tab lists all user-accessible attribut es with default values set. upon completion, click generate to generate source and constraint files. the user may choose to use the *.lpc file (or *.ipx file for diamond proj- ects) to load parameters. vco phase & frequency detector loop filter pllcap low pass filter external capacitor 10-15 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide modes there are two modes for configuring the pll in the configuration tab: frequency mode and divider mode. frequency mode in this mode, the user enters input and output clock frequencies and the software calculates the divider settings. if the output frequency entered is not achiev able, the nearest frequency will be displa yed in the ?actual? text box. after input and output frequencies are entered, clicking the calculate button will display the divider values. divider mode in this mode, the user sets the divider settings with th e input frequency. the user must choose the clkop divider value in order to maximize the f vco and achieve optimum pll performance. after setting the input frequency and divider settings, click calculate to display the frequencies. figure 10-15 shows the configuration tab. figure 10-15. latticeecp 2/m pll configuration tab note: in the external capacitor pin, th e grayed out text will automatically indi cate the requirement for the external loop capacitor based upon the pll settings. this is used to alert the user that the external loop capacitor may be required. the auto setting indica tes that the software will dete rmine if the external loop capacitor is required after the pll is placed into an spll or gpll by the place a nd route (par) step. other grayed-out sections of this dia- log box turn on as their sections are enabled. table 10-7 describes all user parameters in the ipexpress gui. 10-16 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide table 10-7. user parameters in the configuration gui user parameters description range default frequency mode desired input/output frequency on/off on divider mode desired input frequency and divider settings on/off off clki frequency without external capacitor 25 (33 1 ) mhz to 420 mhz 100 mhz with external capacitor 2 mhz to 420 mhz 2 ? divider without external capacitor 1 to 16(12 1 ) 1 with external capacitor 1 to 64 ? clkfb feedback mode feedback mode internal, clkop, user clock clkop divider without external capacitor 1 to 16 (12 1 ) 1 with external capacitor 1 to 10 - clkop bypass bypass pll: clkop = clki on/off off desired frequency without external capacitor 25(331) mhz to 420 mhz 100 mhz with external capacitor 5 mhz to 50 mhz 3 ? divider clkop divider setting (divider mode) 2,4,8,16,32,48, 64,80,96,112,128 8 tolerance clkop tolerance users can tolerate 0.0, 0.1, 0. 2, 0.5, 1.0, 2.0, 5.0, 10.0 0.0 actual frequency actual frequency achievable, read only ? ? clkos enable enable clkos output clock on/off off bypass bypass pll: clkos = clki on/off off phase - static clkos static phase shift 0, 22.5, 45, .... , 337.5 ? duty - static clkos static duty cycle select 2 to 14 8 dynamic phase with 50% duty dynamic phase and 50% duty cycle on/off on dynamic phase with dynamic duty dynamic phase and dynamic duty cycle on/off on clkok enable enable clkok output clock on/off off bypass bypass pll: clkok = clki on/off off desired frequency without external capacitor 0.195 mhz to 210 mhz 50 mhz with external capacitor 0.016 mhz to 25 mhz 3 ? divider clkok divider setting (divider mode) 2 to 128 (all even numbers) 2 tolerance clkok tolerance users can tolerate 0.0, 0.1, 0. 2, 0.5, 1.0, 2.0, 5.0, 10.0 0.0 actual frequency actual frequency achievable, read only ? ? pll phase & duty option dynamic/static mode se lection dynamic mode/st atic mode static mode delay adjust dynamic/static/no delay selection dynamic/static/no delay no delay 4 provide pll reset provide pll reset port on/off off provide clkok divider reset provi de clkok reset port on/off off import lpc to isplever project import .lpc file to isplever project on/off off 1. these values apply to spll. all other values apply to both gpll and spll. 2. phase detector input frequency range 2 mhz to 50mhz. 3. for f in < 5mhz, f out_max = 10 * f in . 4. ipexpress gives the user the ability to select the gpll, spll, or to let the software choose, based upon the settings in the delay adjust section. 10-17 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide frequency calculation table 10-8 illustrates the frequency limit s at the phase detector inputs. users must se lect clki divider and clkfb divider values so that the phase detector frequency falls within the range. let m = clki divider value n = clkfb divider value v = clkop divider value the basic equations are: clkop frequency = clki frequency * n/m f vco (vco frequency) = clkop frequency * v f pfd (pfd frequency) = clki frequency / m = clkfb frequency (= clkop frequency) / n example: if clki frequency is 25 mhz without extern al capacitor, the clki divider value can be only 1. table 10-8. phase detector frequency (f pfd ) range pll modes of operation plls have many uses within logic design. the two most popular are clock injection removal and clock phase adjustment. these two modes of operation are described below. pll clock injection removal in this mode, the plls are used to reduce clock injection delay. clock injection delay is the delay from the input pin of the device to a destination element such as a flip-flop. the phase detector of the pll aligns the clki with clkfb. if the clkfb signal comes from the clock tree (clkop), then the pll delay and the clock tree delay is removed. figure 10-16 illustrates an example block diagram and waveform. pll type external capacitor frequency range gpll without external capacitor 25 mhz to 420 mhz with external capacitor 2 mhz to 50 mhz 1 spll without external capacitor 33 mhz to 420 mhz with external capacitor 2 mhz to 50 mhz 1 1. for f in < 5mhz, f out_max = 10 * f in . 10-18 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-16. clock injection delay removal application pll clock phase adjustment in this mode, the plls are used to create fixed phase relationships in 22.5 o increments. creating fixed phase rela- tionships are useful for forward clock interfaces where a specific relationship between the clock and data is required. the fixed phase relationship can be used between clki and clkos or between clkop and clkos. figure 10-17. clkos phase adjustment from clkop sysclock dll the latticeecp2/m dll provides features such as clock injection delay removal, delay match, time reference delay (90 o phase delay), and output phase adjustment. the dll performs clock manipulation by adding delay to the clki input signal to create specific phase relationships. there ar e two types of outputs of the dll. the first are clock sig- nals similar to the pll clkop and clko s. the other type of output is a de lay control vector (dcntl[8:0]). the delay control vector is connected to a slave delay line (dlldel) element located in the i/o logic which matches the delay cells in the dll. this delay vector allows th e dll to dynamically delay an input signal by a specific amount. figure 10-18 provides a block diagram of the latticeecp2/m dll. clki clock at clock tree without pll clkop/clkos at clock tree with pll clock injection delay pll clki clkfb clkop clock tree clki clkop clkos with 90 o phase shift pll clki clkfb clkop clkos 10-19 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-18. latticee cp2/m dll block diagram both clock injection delay removal and output phase adjustment use only the clock outputs of the dll. time refer- ence delay and delay match modes use the delay control ve ctor output. specific examples of these features are discussed later in this document. dll overview the latticeecp2/m dll is created and configured by ipex press. the following is a list of port names and descrip- tions for the dll. there are two library elements used to implement the dll: ciddlla (clock injection delay), and trddlla (time reference delay). ipexpress will wrap one of these library elements to create a customized dll module based on user selections. dll inputs and outputs clki input the clki signal is the reference clock for the dll. the cl ki input can be sourced from any type of fpga routing and pin. the dll clki input has a preferred pin per dll which provides the lowest latency and best case perfor- mance. clkfb input the clkfb input is available only if the user chooses to use a user clock signal for the feedback or in clock delay match mode. if internal feedback or clkos/clkop is us ed for the feedback, this c onnection will be made inside the module. in clock inject ion delay removal mode, the dll will align the input clock phase with the feedback clock phase by delaying the input clock. in clock injection delay match mode, the dll will calculate the delta between the clki and clkfb signals. this delay value is then output on the dcntl vector. the dll clkfb input has a preferred pin per dll which is dis- cussed later in this document. the preferred pin provides the lowest latency and best case performance. clkop output an output of the dll based on the clki rate. the clkop output can drive primary and edge clock routing. clkos output an output of the pll based on the clki rate which can be divided and/or phase shifted. the clkos output can drive the primary and edge clock routing. dcntl[8:0] output this output of the dll is used to delay a signal by a specific amount. the dcntl[8:0] vector connects to a slave delay line element. the dll can then control multiple input delays from a single dll. clkop clkos lock rstn clkfb clki aluhold dcntl[8:0] uddcntl dcntl control alu delay chain duty 50 d4 d2 pfd phase adjust duty 50 d4 d2 10-20 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide uddcntl input this input is used to enable or disable updating of the dcntl[8:0]. to ensure that the signal is captured by the syn- chronizer in the dll block, it must be driven high for a time equal to at least two clock cycles when an update is required. if the signal is driven high and held in that state, the dcntl[8:0] outputs are continuously updated. aluhold input this active high input stops the dll from adding and subtracting delays to the clki signal. the dcntl[8:0], clkop, and clkos outputs will st ill be valid, but will not change fr om the current delay setting. lock output active high lock indicator output. t he lock output will be high wh en the clki and clkfb si gnal are in phase. if the clki input stops the lock output will remain asserted. the clock is stoppe d so there is no clock to de-assert the lock output. note that this is different from the operation of the pll where the vco continues to run when the input clock stops. rstn active low reset input to reset the dll. the dll can option ally be reset by the gsrn as well. it is recommended that if the dll requires a reset, the reset should not be th e same as the fpga logic reset. typically, logic requires that a clock is running during a reset condition. if the data path reset also resets the dll, the source of the logic clock will stop and this may cause problems in the logic. dll attributes the latticeecp2/m dll utilizes several attributes that allow the configuration of the dll through source con- straints, ipexpress and preference files. the following section details these attributes and their usage. dll lock on divide by 2 or divide by 4 clkos output usually, the dll is a ?times one? device, allowing ne ither frequency multiplicat ion or division. but the latticeecp2/m dll allows ?divide by 2? or ?divide by 4? cl kos outputs. two optional ?divide by 2? and ?divide by 4? blocks are placed at the clki input as well as the clkos and this enables the use of divided clkos in the dll feedback path. this allows the dll to perform clock injection removal on a ?divide by 2? or ?divide by 4? clock, which is useful for ddrx2 and ddrx4 modes of i/o buffer operation. when this optional clock divider is used only in the clkos output path, it allows the dll to output two time-aligned clocks at different frequencies. when the divider is set to divi de by 2 or divide by 4, a ?dummy? delay is inserted in the clkop output path to match the clock to q delay of the clkos divider. optional clock fine phase shift the optional fine phase shift in the clkos output path is built from a delay block that matches the other four blocks in the main delay chain. this delay block allows the clkos output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. gsr the dll can be reset by the gsr, if enabled. the gs r keyword can be set to en abled/disabled. this option is provided in the ipexpress gui. below is an example of the use of this preference. asic ?dll/dll_0_0? type ?ciddlla? gsr=disabled; dll lock time control the dll will lock when the clki and clkfb phases are alig ned. in a simulation environmen t, the lock time is fixed to 100s (default). this value can be changed through an hdl parameter or preference (for the back annotation simulation). the dll contains a parameter named lock_delay which accepts an integer value for the total time in s until the lock output goes high. below is an example of how to set this value for front-end simulation. 10-21 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide verilog: defparam mydll.mypll_0_0.lock_delay=500; mydll dll_inst(.clki(clkin), .clkop(clk1), .clkos(clk2), vhdl: not supported. for back annotation simulation lock_delay needs to be set in the preference file. below is an example for the pll. asic ?pll/pll_0_0? type ?ehxplla? lock_delay=200; dll library symbols figure 10-19. dll library symbols dll library definitions the lattice library contains library elements to allow de signers to utilize the dll. th ese library elements use the dll attributes defined in the ?dll attributes? section. the two modes of operation are presented as library elements as listed below. table 10-9. dll library elements dll library element i/os table 10-10. dll library element i/o descriptions library element name mode of operation description trdlla time reference delay dll this mode generates four phases of the clock, 0, 90, 180, 270, along with the control setting used to generate these phases. ciddlla clock injection delay dll (four delay cell mode) this mode removes the clock tree delay, aligning the external feedback clock to the reference clock. it has a single output coming from the fourth delay block. signal i/o description clki i clock input pin from dedicated clock input pin, other i/o or logic block. clkfb i clock feedback input pin from dedicated feedback input pin, internal feedback, other i/o or logic block. this signal is not user selectable. rstn i active low synchronous reset. from dedicated pin or internal node. aluhold i ?1? freezes the alu. for trdlla and ciddlla. uddcntl i active high synchronous enable signal from cib for updating digital control to pic delay. it must be driven high at least two clock cycles. dcntl[8:0] o digital delay control code signals. clkop o the primary clock output for all possible modes. clkos o the secondary clock output with finer phase shift and/or division by 2 or by 4. lock o active high phase lock indicator. lock means the reference and feedback clocks are in phase. note: refer to device data sheet for frequency specifications. trdlla clki rstn aluhold uddcntl clkop clkos lock dcntl ciddlla clki clkfb rstn aluhold clkop clkos lock 10-22 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide dll modes of operation clock injection removal mode (ciddlla) the dll can be used to reduce clock injection delay (ciddlla). clock injection delay is the delay from the input pin of the device to a destination element such as a flip-f lop. the dll will add delay to th e clki input to align clki to clkfb. if the clkfb signal comes from the clock tree (clkop, clkos) then the delay of the dll and the clock tree will be removed from the overall clock path. fi gure 10-20 shows a circuit example and waveform. figure 10-20. clock injection delay removal via dll clock injection removal mode can also provide a dcntl port. in this mode, the delay added to the clki signal is output on the dcntl port so that other input signals can be delayed by the same amount. this is very useful if sev- eral clocks are used in the same circuit to minimize the number of dlls required. when using the dcntl, the dll delay will be limited to the range of the dcntl vector. therefore, ipexpress will re strict the clki rate from 300mhz to 700mhz. time reference delay mode (trdlla: 90-degree phase delay) the time reference delay (trddlla) mode of the dll is used to calculate 90 degrees of delay to be placed on the dcntl vector. this is a useful mode in delaying a cloc k 90 degrees for use in clocking a ddr type interface. figure 10-21 provides a circuit example of this mode. figure 10-21. time reference delay circuit example in this mode, clki accepts a clock input. the dll produc es a dcntl vector that will delay an input signal by 90 degrees of a full period of the clki signal. this dcntl vector can then be connected to a slave delay line (dll- dela) to delay the signal by 90 degrees of the full period of clki. clki clock at clock tree without dll clkop/clkos at clock tree with dll clock injection delay ciddll clki clkfb clkop clock tree delay clk clki data dlldel trdll dcntl d q eclk eclk injection 10-23 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide dll usage in ipexpress ipexpress is used to create and configure a dll. the ipexpress graphical user interface allows users to select parameters for the dll. the result is an hdl model to be used in the simulation and synthesis flow. configuration tab ? usage mode ? select the mode of the dll (time reference de lay [trdlla] or clock injection delay removal [ciddlla]). this selection will enable or disable further options in the gui. ? clki frequency ? the rate of the clki input in mhz. ? clkos divider ? set the divider for the clkos output to be ei ther no divide, divide by 2, or divide by 4. ? clkos phase shift ? set the phase offset of the clkos to th e clkop output. clkop will lead clkos by the amount of phase shift selected. the phase increment is 11.25 degrees. the pull-down list numbers are abbrevi- ated to a decimal point. ? clkfb feedback mode ? sets the feedback mode of the dll to either clkop, clkos or user clock. if clkop/clkos is selected, the clock tree injection delay for the specific output clock will be removed. if user clock is selected, the user will be prov ided with the clkfb port on the dll. ? clkfb frequency ? this is used only with user clock feedback mode. ? provide rstn port ? the rstn port allows the user to reset the dll through a user signal. pll/dll cascading it is possible to connect several arrangements of plls and dlls. there are three possible cascading schemes: ? pll to pll ? pll to dll ? dll to dll it is not possible to connect the dll to a pll. the dll produces abrupt changes on its output clocks when chang- ing delay settings. the pll sees this as radical phase changes that prevent the pll from locking correctly. ipexpress output there are two outputs of ipexpress that are important for use in the design. the first is the 10-24 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-22. clkdiv library symbol table 10-11. clkdivb port definitions table 10-12. clkdivb attribute definition clkdiv declaration in vhdl source code component clkdivb -- synthesis translate_off generic ( gsr : in string); -- synthesis translate_on port ( clki,rst, release:in std_logic; cdiv1, cdiv2, cdiv4, cdiv8:out std_logic); end component; attribute gsr : string; attribute gsr of clkdivinst0 : label is ?disabled?; begin clkdivinst0:clkdivb -- synthesis translate_off generic map( gsr => ?disabled? ); -- synthesis translate_on port map( clki => clkisig, rst => rstsig, release => releasesig, name description clki clock input rst 1 reset input, asynchronously forces all outputs low. release 1 releases outputs synchro nously to input clock. cdiv1 divided by 1 output cdiv2 divided by 2 output cdiv4 divided by 4 output cdiv8 divided by 8 output 1. note: unused rst must be tied to ground. unused release must be tied to v cc . name description value default gsr gsr enable enabled/disabled disabled clkdivb cdiv1 cdiv2 cdiv4 cdiv8 clki rst release 10-25 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide cdiv1 => cdiv1sig, cdiv2 => cdiv2sig, cdiv4 => cdiv4sig, cdiv8 => cdiv8sig ); end clkdiv usage with verilog - example module clkdiv_top(rst,clki,release,cdiv1,cdiv2,cdiv4,cdiv8); input clki,rst,release; output cdiv1,cdiv2,cdiv4,cdiv8; clkdivb clkdibinst0 (.rst(rst),.clki(clki),.release(release), .cdiv1(cdiv1),.cdiv2(cdiv2),.cdiv4(cdiv4),.cdiv8(cdiv8)); defparam clkdibint0.gsr = "disabled"; endmodule clkdiv example circuits the clock divider (clkdiv) can divide a clock by 2 or 4 and drives a primary clock network. the clock dividers are useful for providing the low-speed fpga clocks for i/o shift registers (x2, x4) and ddr (x2, x4) i/o logic interfaces. divide by 8 is provided for slow speed/low power operation. to guarantee a synchronous transfer in the i/o logic, the clkdiv input clock must come from an edge clock and the output drives a primary clock. in this case, they are phase matched. this is especi ally useful for synchronously resetting the i/o logic when mux/demux gearing is used in order to synchronize the entire data bus as shown in figure 10-23. using the low skew characteristics of the edge clock routing, a reset can be provided to all bits of the data bus to synchronize the mux/demux gearing. the second circuit shows that a dll can replace clkdiv for x2 and x4 applications. 10-26 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-23. clkdiv application examples release behavior the port ?release? is used to synchr onize all outputs a fter rst is de-asserted. figure 10-24 illustrates the release behavior. figure 10-24. clkdi v release behavior clkdiv eclk data d q gearing (2x) rst primary clock 8 16 clkop dll clkos clk data d q sclk (system clock) 8 16 gearing (2x) clki rst release cdiv1 cdiv2 cdiv4 cdiv8 de-asserted rst registered clock start counting release synchronizes outputs 10-27 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide dlldel (slave delay line) the slave delay line is designed to generate the desired delay in ddr/spi4 applications. the delay control inputs (dcntl[8:0]) are fed from the general purpose dll outputs. the library element definitions are described in figure 10-25 and table 10-13. figure 10-25. dlldela library symbol table 10-13. dlldela i/o dlldela declaration in vhdl source code component dlldela port ( clki :in std_logic; dcntl0 :in std_logic; dcntl1 :in std_logic; dcntl2 :in std_logic; dcntl3 :in std_logic; dcntl4 :in std_logic; dcntl5 :in std_logic; dcntl6 :in std_logic; dcntl7 :in std_logic; dcntl8 :in std_logic; clko :out std_logic ); end component; begin dlldelainst0: dlldela1 port map ( clki => clkisig, dcntl0 => dcntl0sig, dcntl1 => dcntl1sig, dcntl2 => dcntl2sig, dcntl3 => dcntl3sig, dcntl4 => dcntl4sig, dcntl5 => dcntl5sig, dcntl6 => dcntl6sig, dcntl7 => dcntl7sig, dcntl8 => dcntl8sig, name i/o description clki i clock input dcntl[8:0] i delay control bits clko o clock output dlldela clko clki dcntl0 dcntl1 dcntl2 dcntl3 dcltl4 dcntl5 dcntl6 dcntl7 dcltl8 10-28 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide clko => clkosig ); end dlldela usage with trdlla - verilog - example note: dll0(trdlla) must be generated by ipexpress as a sub-module module ddldel_top (rst,d,clkin,clkin2,clkout,aluhold,uddcntl,q); input rst,d,clkin,clkin2,aluhold,uddcntl; output clkout,q; wire [8:0]dcntl_int; reg qint; dll0 dllinst0 (.clk(clkin2), .aluhold(aluhold), .uddcntl(uddcntl), .clkop(), .clkos(), .dcntl(dcntl_int),.lock()); dlldela delinst0 (.clki(clkin),.dcntl0(dcntl_int[0]),.dcntl1(dcntl_int[1]), .dcntl2(dcntl_int[2]), .dcntl3(dcntl_int[3]), .dcntl4(dcntl_int[4]), .dcntl5(dcntl_int[5]), .dcntl6(dcntl_int[6]), .dcntl7(dcntl_int[7]), .dcntl8(dcntl_int[8]), .clko(clk90)); //synthesis syn_black_box assign clkout = clk90; assign q = qint; always@(posedge clk90 or negedge rst) if (~rst) qint =1'b0; else qint = d; endmodule dlldela application example figure 10-26 shows an example dlldel application. as shown in the timing diagram, dlldel shifts the clock by 90 degrees to center both edges in the middle of data window. 10-29 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-26. spi4.2 and ddr re gisters interface application dqsdll and dqsdel there is another combination of dll and slave delay line, dqsdll and dqsdel, in the latticeecp2/m device family. this pair is similar in design and function to dll and dlldel, but usage is limited to ddr implementation. for additional information, see tn1102, latticeecp2/m sysio usage guide . dcs (dynamic clock select) dcs is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. there are two dcss for each quadrant. the outputs of the dcs then reach primary clock distribution via the feed- lines. figure 10-27 shows the block diagram of the dcs. data + injection delay 90 o shift + injection delay 1.2 ns clk at pin data at pin 1.2 ns fd: fixed delay dd: dynamic delay users can select the delay setting in ipexpress. data clkdiv eclk1 eclk2 dll clkop dlldel dcntl[8:0] clk fd dd data/ clk core logic 840 mbps 420 mhz 840 mbps/ 420 mhz 10-30 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-27. dcs library symbol dcs library element definition table 10-14 defines the i/o ports of the dcs block. there are eight modes available. table 10-15 describes how each mode is configured. table 10-14. dcs i/o definition table 10-15. dcs modes of operations dcs timing diagrams each mode performs its unique operation. clock output timing is determined by input clocks and the edge of the sel signal. figure 10-28 describes the timing of each mode. i/o name description input sel input clock select clk0 clock input 0 clk1 clock input 1 output dcsout clock output attribute name description output value sel = 0 sel = 1 dcs mode rising edge triggered, latched state is high clk0 clk1 pos falling edge triggered, latched state is low clk0 clk1 neg sel is active high, disabled output is low 0 clk1 high_low sel is active high, disabled output is high 1 clk1 high_high sel is active low, disabled output is low clk0 0 low_low sel is active low, disabled output is high clk0 1 low_high buffer for clk0 clk0 clk0 clk0 buffer for clk1 clk1 clk1 clk1 dcs dcsout clk0 sel clk1 10-31 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-28. timing diagrams by dcs mode clk0 clk1 sel dcsout sel falling edge: - wait for clk1 falling edge, latch output & remain low - switch output at clk0 falling edge sel rising edge: - wait for clk0 falling edge, latch output & remain low - switch output at clk1 falling edge dcs mode = neg clk0 clk1 sel dcsout sel falling edge: - wait for clk1 rising edge, latch output & remain high - switch output at clk0 rising edge sel rising edge: - wait for clk0 rising edge, latch output & remain high - switch output at clk1 rising edge dcs mode = pos 10-32 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-28. timing diagrams by dcs mode (cont.) clk1 sel dcsout - switch low @clk1 falling edge. - if sel is low, output stays low at on clk1 rising edge. sel must not change during setup prior to rising clock. dcs mode = high_low clk0 sel dcsout - switch low @clk0 falling edge. - if sel is high, output stays low at on clk0 rising edge. dcs mode = low_low clk1 sel dcsout - switch high @clk1 rising edge. - if sel is low, output stays low high on clk1 falling edge. dcs mode = high_high clk0 sel dcsout - switch high @ clk0 rising edge. - if sel is high, output stays high on clk0 falling edge. dcs mode = low_high 10-33 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide dcs usage with vhdl - example library ecp2m; use ecp2m.components.all; library ieee; use ieee.std_logic_1164.all; entity dcstest is port ( clksel : in std_logic; dcsclk0 : in std_logic; sysclk1 : in std_logic; dcsclk : out std_logic ); end dcstest; architecture dcstest_arch of dcstest is component dcs -- synthesis translate_off generic ( dcsmode : string := "pos" ); -- synthesis translate_on port ( clk0 :in std_logic; clk1 :in std_logic; sel :in std_logic; dcsout :out std_logic ); end component; attribute dcsmode : string; attribute dcsmode of dcsinst0 : label is "pos"; begin dcsinst0: dcs -- synthesis translate_off generic map ( dcsmode => "pos" ) -- synthesis translate_on port map ( sel => clksel, clk0 => dcsclk0, clk1 => sysclk1, dcsout => dcsclk ); end dcstest_arch; 10-34 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide dcs usage with ve rilog - example module dcs(clk0,clk1,sel,dcsout); input clk0, clk1, sel; output dcsout; dcs dcsinst0 (.sel(sel),.clk0(clk0),.clk1(clk1),.dcsout(dcsout)); defparam dcsinst0.dcsmode = "clk0"; endmodule oscillator (oscd) there is a dedicated os cillator in the latticeecp2/m devices whose out put is made available for users. the oscilla- tor frequency is programmable with a range of 2.5 to 130mhz. the ou tput of the oscillator ca n also be routed as an input clock to the clock tree. the oscilla tor frequency output can be further divided by intern al logic (user logic) for lower frequencies, if desired. the osc illator is powered down when not in use. the output of this oscillator is not a precision clock. it is intended for use as an extra clock that does not require accurate clocking. library element name: oscd table 10-16. oscd port definition table 10-17. oscd attribute definition please refer to the latticeecp2/m family data sheet for detailed specifications. osc library symbol (oscd) figure 10-29. ocs symbol i/o name description output osc oscillator clock output user attribute attribute name value (mhz) default value nominal frequency nom_freq 2.5, 4.3, 5.4, 6.9, 8.1, 9.2, 10.0, 13. 0, 15.0, 20.0, 26.0, 30.0, 34.0, 41.0, 45.0, 55.0, 60.0, 130.0 2.5 oscd cfgclk 10-35 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide osc usage with vhdl - example component oscd -- synthesis translate_off generic(nom_freq: string); -- synthesis translate_on port (cfgclk:out std_logic); end component; attribute nom_freq : string; attribute nom_freq of oscins0 : label is ?2.5?; begin oscinst0: oscd -- synthesis translate_off generic map (nom_freq => ?2.5?) -- synthesis translate_on port map ( cfgclk=> osc_int); end osc usage with verilog - example module osc_top(osc_clk); output osc_clk; oscd oscinst0 (.cfgclk(osc_clk)); defparam oscinst0.nom_freq = "2.5"; endmodule 10-36 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide input clock sharing the reference clock from the pads can be shared in latticeecp2/m plls and dlls as shown in figures 10-30 and 10-31. this feature is useful when only one clock source is available for multiple plls/dlls. figure 10-30. input clock sharing (latticeecp2-50 and latticeecp2-70) latticeecp2-70 spll pio gpll pio spll pio spll clki spll clki gpll clki dll clki dll pio spll pio gpll pio spll pio spll clki spll clki gpll clki dll clki dll pio latticeecp2-50 gpll pio spll pio spll clki gpll clki dll clki dll pio gpll pio spll pio spll clki gpll clki dll clki dll pio 10-37 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-31. input clock sharing (latticeecp2m with six splls) setting clock preferences clock preferences allow designers to implement clocks to the desired performance. preferences can be set in the isplever design planner spreadsheet view (or tools > spreadsheet view in diamond) or in preference files. frequently used preferences are descr ibed in appendix c. for additional information see the isplever or dia- mond on-line help system. power supplies each pll has its own power supply. on the latticeecp2-6, latticeecp2-12, and latticeecp2-20 devices the pll power supply has been combined with the package vcc fo r better performance. there will only be vcc pins on these devices. on the larger latticeecp2 and all latticeecp2m devices, the pll power supply has its own power supply pins, vccpll. since vcc and vccpll are normally the same 1.2v, it is recommended that they are driven from the same power supply on the circuit board, thus minimizing leakage. in addition, each of these supplies should be independently isolated from the main 1.2v supply on the board using proper board filtering techniques to minimize the noise coupling between them. the dll is powered from the fpga core power supply. dll pio clki dll clki gpll gpll pio clki spll spll pio dll pio clki dll clki gpll gpll pio clki spll spll pio quadrant tl quadrant tr quadrant bl quadrant br clki spll spll pio clki spll spll pio clki spll spll pio clki spll spll pio 10-38 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com revision history date version change summary february 2006 01.0 initial release. april 2006 01.1 removed unsupported devices, removed dll smi phrases, rephrased dduty support due to software incomplete. september 2006 01.2 added detailed clock network descriptions. added ipexpress gui quick reference table. added latticeecp2m information throughout. osc divider value range updated. january 2007 01.3 updated frequency range. described clkop and clkok synchronous timing relationship with respective reset signals. january 2007 01.4 updated ipexpress main window screen shot. updated latticeecp2/m configuration tab screen shot. updated user parameters in the configuration gui table. june 2007 01.5 corrected reference to exhplld in optional external capacitor sec- tion (changed to ehxplld). updated gsr section of attributes. august 2008 01.6 updated the latticeecp2/ m pll configuration tab screen shot. updated the port names for the latticeecp2/m pll library symbols. added latticeecp2/m pll modules section. corrected the external capacitor section. removed the dll operation mode cimd lla since it is not available on latticeecp2/m. updated power supplies section. march 2009 01.7 updated ?dcs usage with vhdl - example? code. october 2009 01.8 updated input clock shari ng (latticeecp2-50 and latticeecp2-70) fig- ure. february 2010 01.9 reconciled lock description among machxo, latticexp2, latticeecp2/m and latticeecp3. may 2010 02.0 specified dedicated clock pins in the secondary clocks text section. june 2010 02.1 updated for lattice diamond design software support. 10-39 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide appendix a. primary clock sources and distribution figure 10-32. latticeecp2 primary clock sources and distribution figure 10-33. latticeecp2 primary clock muxes primary clocks in center switch box latticeecp2 spll1 : available in latticeecp2-70 spll2 : available in latticeecp2-50 and larger devices general routing quadrant tl general routing quadrant tr 2 3 clk0 clk2 clk4 clk1 clk3 clk5 clk6 clk7 dcs 36:1 36:1 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 dcs clk6 clk7 dcs 36:1 36:1 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 dcs clk5 clk3 clk1 clk4 clk2 clk0 general routing quadrant bl general routing quadrant br 2 3 clk0 clk2 clk4 clk1 clk3 clk5 clk6 clk7 dcs 36:1 36:1 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 dcs clk6 clk7 dcs 36:1 36:1 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 dcs clk5 clk3 clk1 clk4 clk2 clk0 gpll clkop clkos clkok dll clkop clkos clkok spll2* clkop clkos clkok spll1* clkop clkos clkok pclkt7 clkdiv clkdiv1 clkdiv2 clkdiv4 clkdiv8 pclkt6 gpll clkop clkos clkok dll clkop clkos clkok spll2* clkop clkos clkok spll1* clkop clkos clkok pclkt2 clkdiv clkdiv1 clkdiv2 clkdiv4 clkdiv8 pclkt3 pclk t0 pclk t1 pclkt4 pclkt5 clk0 - 5 18 pll outputs* 4 dll outputs 8 clkdiv outputs 4 pclk pins general routing *latticeecp2-50 has twelve pll outputs vcc 36:1 clk6 - 7 15 pll outputs* 3 dll outputs 8 clkdiv outputs 4 pclk pins 2 from general routing *latticeecp2-50 has ten pll outputs 32:1 dcs 10-40 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-34. latticeecp2m primary clock sources and distribution latticeecp2m primary clocks in center switch box general routing quadrant tl general routing quadrant tr 2 3 clk0 clk2 clk4 clk1 clk3 clk5 clk6 clk7 dcs 46:1 46:1 46:1 46:1 46:1 46:1 41:1 41:1 41:1 41:1 dcs clk6 clk7 dcs 46:1 46:1 46:1 46:1 46:1 46:1 41:1 41:1 41:1 41:1 dcs clk5 clk3 clk1 clk4 clk2 clk0 pclkt7 pclkt2 pclk t0 pclk t1 serdes tx_h_clk availability ur: all devices lr: latticeecp2m-50 or larger devices ul/ll: latticeecp2m-70 or larger devices. gpll clkop clkos clkok dll clkop clkos clkok spll2 clkop clkos clkok spll1 clkop clkos clkok clkdiv clkdiv1 clkdiv2 clkdiv4 clkdiv8 pclkt3 serdes_lr* tx_h_clk serdes_ur* tx_h_clk spll3* clkop clkos clkok gpll clkop clkos clkok dll clkop clkos clkok spll2 clkop clkos clkok spll1 clkop clkos clkok clkdiv clkdiv1 clkdiv2 clkdiv4 clkdiv8 pclkt6 serdes_ll* tx_h_clk serdes_ul* tx_h_clk spll3* clkop clkos clkok general routing quadrant bl general routing quadrant br 2 3 clk0 clk2 clk4 clk1 clk3 clk5 clk6 clk7 dcs 46:1 46:1 46:1 46:1 41:1 41:1 41:1 41:1 dcs clk6 clk7 dcs 46:1 46:1 46:1 46:1 46:1 46:1 41:1 41:1 41:1 41:1 dcs clk5 clk3 clk1 clk4 clk2 clk0 pclkt4 pclkt5 46:1 46:1 10-41 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-35. latticeecp2m primary clock muxes 46:1 dcs clk6 - 7 20 pll outputs 3 dll outputs 8 clkdiv outputs 4 pclk pins 2 from general routing 41:1 clk0 - 5 24 pll outputs 4 dll outputs 8 clkdiv outputs 4 pclk pins general routing *latticeecp2m-50 has two serdes tx clk outputs vcc 4 serdes tx clks* 4 serdes tx clks* 10-42 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide appendix b. pll, dll, clkidv an d eclk locations and connectivity figure 10-36 shows the locations, site names, and connectivity of the plls, dlls, clkdivs and eclks figure 10-36. pll, dll, clkidv and eclk locations and connectivity lclkdiv rc l kd iv eclk1 eclk2 eclk1 eclk2 internal node internal node eclk2 eclk1 in terna l n od e in terna l n od e ecl k1 ecl k2 pclkt7 lgpll_in ldll_del internal node internal node internal node internal node clkop clkos lgpll clkop clkos ldll pclkt6 pclkt2 lgpll_in rdll_del internal node internal node internal node internal node clkop clkos rgpll clkop clkos rdll pclkt3 pcl kt4 pcl kt5 pclkt0 pclkt1 10-43 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide appendix c. clock preferences a few key clock preferences are introduced below. refer to the software ?help? file for other preferences and detailed information. asic the following preference command assigns a phase of 90 to the trdlla_clkos: asic "my_dll" type "trdlla" clkos_phase=90; frequency the following physical preference command assigns a frequency of 100 mhz to a net named clk1: frequency net "clk1" 100 mhz; the following preference specifies a hold margin value for each clock domain: frequency net "rx_clka_cmos_c" 100.000 mhz hold_margin 1 ns; maxskew the following command assigns a maximum skew of 5ns to a net named netb: maxskew net "netb" 5 ns; multicycle the following command will rela x the period to 50ns fo r the path starting at compa to compb (net1): multicycle "path1" start comp "compa" end comp "compb" net "net1" 50 ns ; period the following command assigns a clock period of 30ns to the port named clk1: period port "clk1" 30 ns; prohibit this command prohibits the use of a primar y clock to route a clock net named bf_clk: prohibit primary net "bf_clk"; use primary use a primary clock resource to route the specified net. use primary net clk_fast; use primary dcs net "bf_clk"; use primary pure net ?bf_clk? quadrant_tl; use secondary use a secondary clock resource to route the specified net. use secondary net "clk_lessfast" quadrant_tl; use edge use a edge clock resource to route the specified net. use edge net ?clk_fast?; clock_to_out specifies a maximum allowable outp ut delay relative to a clock. 10-44 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide here are two preferences using both the clkport and clknet keywords showing the corresponding scope of trace reporting. the clknet will stop tracing the path before the pll, so you will not get pll comp ensation timing numbers. clock_to_out port "rxaddr_0" 6.000000 ns clknet "pll_rxclk" ; the above preference will yiel d the following clock path: physical path details: clock path pll_inst/pll_utp_0_0 to pfu_33: name fanout delay (ns) site resource route 49 2.892 ulppll.mclk to r3c14.clk0 pll_rxclk -------- 2.892 (0.0% logic, 100.0% route), 0 logic levels. if clkport is used, the trace is complete back to the clock port resource and provides pll compensation timing numbers. clock_to_out port "rxaddr_0" 6.000000 ns clkport "rxclk" ; the above preference will yiel d the following clock path: clock path rxclk to pfu_33: name fanout delay (ns) site resource in_del --- 1.431 d5.pad to d5.inck rxclk route 1 0.843 d5.inck to ulppll.clkin rxclk_c mclk_del --- 3.605 ulppll.clkin to ulppll.mclk pll_inst/pll_utp_0_0 route 49 2.892 ulppll.mclk to r3c14.clk0 pll_rxclk -------- 8.771 (57.4% logic, 42.6% route), 2 logic levels. input_setup specifies an setup time requirement for input ports relative to a clock net. input_setup port "datain" 2.000000 ns hold 1.000000 ns clkport "clk" pll_phase_back ; pll_phase_back this preference is used with input_setup when the user needs a trace calculation based on the previous clock edge. this preference is useful when setting the pll output ph ase adjustment. since there is no negative phase adjust- ment provided, the pll_phase_back preference works as if negative phase ad justment is available. for example: if a phase adjustment of -90 of clkos is desired, the user can set the phase to 270 and set the input_setup preference with pll_phase_back. pll_phase_back usage in pre-map preference editor: the pre-map preference editor can be used to set the pll_phase_back attribute. 1. open the design planner (pre-map). 2. in the design planner control window, select spreadsheet view under view . 3. in the spreadsheet view window, select input_setup/clock_to_out? 4. the input_setup/clock_to_out preference window is shown in figure 10-37. 10-45 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-37. input_setup/clock_to_out prefer ence window (see appendix d figure 10-41 for ? diamond equivalent) 10-46 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide appendix d. lattice diamond usage overview this appendix discusses the use of lattice diamond design software for projects that include the latticeecp2m serdes/pcs module . for general information about the use of lattice diamond, refer to the lattice diamond tutorial. if you have been using isplever software for your fpga design projects, lattice diamond may look like a big change. but if you look closer, you will find many similariti es because lattice diamond is based on the same toolset and work flow as isplever. the changes are intended to provide a simpler, more integrated, and more enhanced user interface. converting an isplever pr oject to lattice diamond design projects created in isplever can easily be imported into la ttice diamond. the pr ocess is automatic except for the isplever process properties, which are similar to the diamond strategy settings, and pcs modules. after importing a project, you need to set up a strategy for it and regenerate any pcs modules. importing an isple ver design project make a backup copy of the isplever project or make a new copy that will become the diamond project. 1. in diamond, choose file > open > import isplever project . 2. in the isplever project dialog box, browse to the project?s .syn file and open it. 3. if desired, change the base file name or location for the diamond project. if you change the location, the new diamond files will go into the ne w location, but the original source files will not move or be copied. the diamond project will refere nce the source files in the original location . the project files are converted to diamond format with the default strategy settings. adjusting pcs modules pcs modules created with ipexpress have an unusual file structure and need additional adjustment when import- ing a project from isplever. there are two ways to do this adjustment. the preferred method is to regenerate the module in diamond. however this may upgrade the module to a more recent version. an upgrade is usually desir- able but if, for some reason, you do not want to upgrade the pcs module, you can manually adjust the module by copying its .txt file into the implementation folder. if you use this method, you must remember to copy the .txt file into any future implementation folders. regenerate pcs modules 1. find the pcs module in the input files folder of file list view. the module may be represented by an .lpc, .v, or .vhd file. 2. if the file list view shows the verilog or vhdl file for the module, and you want to regenerate the module, import the module?s .lpc file: a. in the file list view, right-click the implementation folder ( ) and choose add > existing file . b. browse for the module?s .lpc file, 10-47 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide in file list, the .lpc file is replaced with an .ipx file. the ipexpress manifest (.ipx) file is new with diamond. the .ipx file keeps track of the files needed for complex modules. using ipexpress wi th lattice diamond using ipexpress with lattice diamond is essentially same as with isplever. the configuration gui tabs are all the same except for the generation options tab. figure 10-38 shows the gener- ation options tab window. figure 10-38. generation options tab table 10-18. serdes_pcs gui attr ibutes ? generation options tab gui text description automatic automatically generates the hdl and configuration(.txt) files as needed. some changes do not require regenerating both files. force module and settings generation generates both the hdl and configuration files. force settings generation only generates only the attributes file. you ge t an error message if the hdl file also needs to be generated. force place & route process reset resets the place & route design process, forcing it to be run again with the newly generated pcs module. force place & route trace process reset resets the place & route trace process, fo rcing it to be run again with the newly generated pcs module. note: automatic is set as the default option. if either automatic or forc e settings generation only and no sub-options (process rese t options) are checked and the hdl module is not generated, the reset pointer is set to bitstream generation automatically. after the generation is finished, the reset marks in the process window will be reset accordingly. 10-48 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide creating a new simulation proj ect using simulation wizard this section describes how to use the simulation wizard to create a simulation project (.spf) file so you can import it into a standalone simulator. 1. in project navigator, click tools > simulation wizard . the simulation wizard opens. 2. in the preparing the simulator interface page click next . 3. in the simulator project name page, enter the name of your project in the project name text box and browse to the file path location where you want to put your simulation projec t using the project location text box and browse button. when you designate a project name in this wizard page, a corresponding folder will be created in the file path you choose. click yes in the popup dialog that asks you if you wish to create a new folder. 4. click either the active-hdl ? or modelsim ? simulator check box and click next . 5. in the process stage page choose which type of process stage of simulation project you wish to create valid types are rtl, post-synthesis gate-level, post-map gate-level, and post-route gate-level+timing. only those process stages that are available are activated. note that you can make a new selection for the current strategy if you have more than one defined in your project. the software supports multiple strategies per project implementation which allow you to experiment with alternative optimization options across a common set of source files. since each strategy may have been processed to different stages, this dialog allo ws you to specify which stage you wish to load. 6. in the add source page, select from the source files listed in the source files list box or use the browse button on the right to choose another desired source file. note that if you wish to keep the source files in the local simulation project directory you just created, check the copy source to simulation directory option. 7. click next and a summary page appears and provides information on the project selections including the simulation libraries. by default, the run simulator chec k box is enabled and will launch the simulation tool you chose earlier in the wizard in the simulator project name page. 8. click finish . the simulation wizard project (.spf) file and a simulation script do file are generated after running the wizard. you can import the do file into your current project if de sired. if you are using active -hdl, the wizard will generate an .ado file and if you are using modelsim, it creates and .mdo file. note: pcs configuration file, (.txt) must be added in step 6. 10-49 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-39. diamond spreadsheet view (see figure 10-5 for isplever equivalent) figure 10-40. diamond ipexpr ess main window (see figure 10-14 for isplever equivalent) 10-50 latticeecp2/m sysclock pll/dll lattice semiconductor desi gn and usage guide figure 10-41. diamond input_setup preference window (see figure 10-37 for isplever equivalent) www.latticesemi.com 11-1 tn1104_01.9 march 2009 technical note tn1104 ? 2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction this technical note discusses memory usage for the latticeecp2? and latt iceecp2m? device families. it is intended to be used by design engineers as a guide for integrating the ebr- (embedded block ram) and pfu- based memories in this devi ce family using the isplever ? design tool. the architecture of these devices provides resources for fpga on-chip memory applications. the sysmem? ebr complements the distributed pfu-based memory. single-port ram, dual-port ram, pseudo dual-port ram, fifo and rom memories can be constructed using the ebr. luts and pfu can implement distributed single-port ram, dual-port ram and rom. the capabilities of the ebr ra m and pfu ram are referred to as primitives and are descr ibed later in this docu- ment. designers can utilize the memory primitives in two ways via the ipexpr ess? tool in the isplever software. the ipexpress gui allows users to specify the memory type and size required. ipexpress takes this specification and constructs a netlist to implement the desired memory by using one or more of the memory primitives. the remainder of this document discusses the use of ipexpress, memory modules and memory primitives. memories in latticeecp2/m devices there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom and register functions. the pff block contains building blocks for logic, arithmet ic and rom functions. both pfu and pff blocks are opti- mized for flexibility allowing complex designs to be implem ented quickly and efficiently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. the latticeecp2 family of devices contains up to two rows of sysmem ebr blocks and the latticeecp2m family of devices contains up to seven rows of sysmem ebr bloc ks. sysmem ebrs are large, dedicated 18k fast memory blocks. each sysmem block can be configured in a variety of depths and widths of ram or rom. in addition, latticeecp2/m devices contain up to two rows of sysdsp? blocks. each sysdsp block has multipliers and accu- mulators, which are the building blocks fo r complex signal processing capabilities table 11-1. latticeecp2/m lut and memory densities luts 6k 12k 20k 35k 50k 70k 100k device ecp2-6 ecp2-12 ecp2-20 ecp2m-20 ecp2-35 ecp2m-35 ecp2-50 ecp2m-50 ecp2-70 ecp2m-70 ecp2m-100 luts (k) 6 12 21 19 32 34 48 48 68 67 95 distributed ram (kbits) 12 24 42 41 65 71 96 101 136 145 202 ebr sram blocks 3 12 15 66 18 114 21 225 60 246 288 ebr sram (kbits) 55 221 276 1217 332 2101 387 4147 1106 4534 5308 latticeecp2/m memory usage guide 11-2 lattice semiconductor latticee cp2/m memory usage guide figure 11-1. simplified block diagram, latticeecp2-6 device (top level) utilizing ipexpress designers can utilize ipexpress to easily specify a variet y of memories in their de signs. these modules are con- structed using one or more memory primitives along with general purpose routing and luts, as required. the available primitives are: ? single port ram (ram_dq) ? ebr-based ? dual port ram (ram_dp_true) ? ebr-based ? pseudo dual port ram (ram_dp) ? ebr-based ? read only memory (rom) ? ebr-based ? first in first out memory (dual clock) (fifo_dc) ? ebr-based ? distributed single port ram (distributed_spram) ? pfu-based ? distributed dual port ram (distributed_dpram) ? pfu-based ? distributed rom (distributed_rom) ? pfu/pff-based ? distributed shift register (ram_based_shift_register) - pfu based (see ipexpress help for details) ipexpress flow for generating any of these memories, create (or open) a project for the latticeecp2/m devices. from the project navigator, select tools > ipexpress or click on the button in the toolbar when latticeecp2/m devices are targeted in the project. this opens the ipexpress main window as shown in figure 11-2. programmable function units (pfus) flexible sysio buffers: lvcmos, hstl, sstl, lvds, and other standards sysdsp blocks multiply and accumulate support sysmem block ram 18kbit dual port sysclock pl ls and dlls frequency synthesis and clock alignment flexible routing optimized for speed, cost and routability configuration logic, including dual boot and encryption. on-chip oscillator and soft-error detection. configuration port pre-engineered source synchronous support ? ddr1/2 ? spi4.2 ? adc/dac devices 11-3 lattice semiconductor latticee cp2/m memory usage guide figure 11-2. ipexpress - main window the left pane of this window includes the module tree. the ebr-based memory modules are under the ebr_components and the pfu-based distributed memory modules are under storage_components , as shown in figure 11-2. as an example, let us consider generating an ebr-based pseudo dual port ram of size 512x16. select ram_dp under ebr_components . the right pane changes as shown in figure 11-3. 11-4 lattice semiconductor latticee cp2/m memory usage guide figure 11-3. example generating pseudo dual port ram (ram_dp) using ipexpress in the right pane, options like the device family , macro type , category , and module_name are device and selected module dependent. these cannot be changed in ipexpress. users can change the directory wh ere the generated module files will be placed by clicking the browse button in the project path . the module name text box allows users to specify an entity name for the module they are about to generate. users must provide this entity name. design entry , verilog or vhdl, by default, is the same as the project type. if the project is a vhdl project, the selected design entry option will be ?sch ematic/ vhdl?, and ?schematic/ verilog- hdl? if the project type is verilog- hdl. the device pull-down menu allows users to select different de vices within the same family, latticeecp2/m in this example. by clicking the customize button, another window opens where users can customize the ram (figure 11-4). 11-5 lattice semiconductor latticee cp2/m memory usage guide figure 11-4. example generating pseudo dual port ram (ram_dp) module customization the left side of this window shows the block diagram of the module. the right side includes the configuration tab where users can choose options to customize the ram_dp (e.g. specify the address port sizes and data widths). users can specify the address depth and data width for the read port and the write port in the text boxes pro- vided. in this example, we are generating a pseudo dual port ram of size 512 x 16. users can also create rams of different port widths for pseudo dual port and true dual port rams. the input data and the address control are always registered, as the hardware only supports the clocked write operation for the ebr based rams. the check box enable output registers inserts the output registers in the read data port. output registers are optional for ebr-based rams. users have the option to set the reset mode as asynchronous reset or synchronous reset. enable gsr can be checked to enable the global set reset. if an ebr is pre-loaded during configuration, the gsr input must be dis- abled or the release of the gsr during device wake up must occur before the release of the device i/os becomes active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restric- tions if the ebr synchronous reset is used and the ebr gsr input is disabled. users can also pre-initialize their memo ry with the contents specified in the memory file . it is optional to provide this file in the ram; however for rom, the memory file is required. these files can be of binary, hex or addresses hex format. the details of these formats are discussed in the initialization file section of this document. at this point, users can click the generate button to generate the module they have customized. a vhdl or verilog netlist is then generated and placed in the specified location. users can incorporate this netlist in their designs. another important button is the load parameters button. ipexpress stores the parameters specified in a 11-6 lattice semiconductor latticee cp2/m memory usage guide once the module is generated, users can either instantiate the *.lpc or the verilog-hdl/ vhdl file in top-level mod- ule of their design. the various memory modules, both ebr and distributed, are discussed in detail in this document. memory modules ecc is supported in most memories. if you choos e to use ecc, you will have a 2-bit error signal. ? when error[1:0]=00, there is no error. ? when error[0]=1, it indicates that there was a 1 bit error which was fixed. ? when error[1]=1, it indicates that there was a 2-bit error which cannot be corrected. single port ram (r am_dq) ? ebr based the ebr blocks in latticeecp2/m devices can be configur ed as single port ram or ram_dq. ipexpress allows users to generate the verilog-hdl or vhdl along edif netlist for the memory size as per design requirements. ipexpress generates the memory module as shown in figure 11-5. figure 11-5. single port memory module generated by ipexpress since the device has a number of ebr blocks, the generated module makes use of these ebr blocks, or primi- tives, and cascades them to create the memory sizes specified by the user in the ipexpress gui. for memory sizes smaller than an ebr block, the module will be created in one ebr block. for memory sizes larger than one ebr block, multiple ebr blocks can be cascaded in depth or width (as required to create these sizes). in single port ram mode, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. the various ports and their definitions for the single port memory are listed in table 11-2. the table lists the corre- sponding ports for the module generated by ipexpress and for the ebr ram_dq primitive. ram_dq ebr-based single port memory clock clocken reset we address data q 11-7 lattice semiconductor latticee cp2/m memory usage guide table 11-2. ebr-based single port memory port definitions reset (or rst) resets only the input and output registers of the ram. it does not reset the contents of the memory. chip select (cs) is a useful port in the ebr primitiv e when multiple cascaded ebr blocks are required by the memory. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can cascade eight memories easily. if the memory si ze specified by the user requires more than eight ebr blocks, the isplever software automatically generates the additional address decoding logic, which is imple- mented in the pfu (external to the ebr blocks). each ebr block consists of 18,432 bits of ram. the values for x (address) and y (data) for each ebr block for the devices are listed in table 11-3. table 11-3. single port memory sizes for 16k memories for latticeecp2/m table 11-4 shows the various attributes available for the single port memory (ram_dq). some of these attributes are user-selectable through the ipexpress gui. for detailed attribute definitions, refer to appendix a. port name in generated module port name in the ebr block primitive des cription active state clock clk clock rising clock edge clocken ce clock enable active high address ad[x:0] address bus ? data di[y:0] data in ? q do[y:0] data out ? we we write enable active high reset rst reset active high ? cs[2:0] chip select ? single port memory size input data outp ut data address [msb:lsb] 16k x 1 di do ad[13:0] 8k x 2 di[1:0] do[1:0] ad[12:0] 4k x 4 di[3:0] do[3:0] ad[11:0] 2k x 9 di[8:0] do[8:0] ad[10:0] 1k x 18 di[17:0] do[17:0] ad[9:0] 512 x 36 di[35:0] do[35:0] ad[8:0] 11-8 lattice semiconductor latticee cp2/m memory usage guide table 11-4. single port ram attributes for latticeecp2/m the single port ram (ram_dq) can be configured as normal or write through modes. each of these modes affects the data coming out of port q of the memory during the write operation followed by the read opera- tion at the same memory location. additionally, users can select to enable the output registers for ram_dq. figures 11-6-11-9 show the internal tim- ing waveforms for the single port ram (ram_dq) with these options. attribute description values default value user selectable through ipexpress address depth address depth read port 16k, 8k, 4k, 2k, 1k, 512 yes data width data word width read port 1, 2, 4, 9, 18, 36 1 yes enable output registers register mode (pipelining) for write port noreg, outreg noreg yes enable gsr enables global set reset enable, disable enable yes reset mode selects the reset type async, sync async yes memory file format binary, hex, addressed hex yes write mode read / write mode for write port normal, write- through normal yes chip select decode chip select decode for read port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no init value initialization value 0x000000000000000000000 00000000000000000000000 00000000000000000000000 0000000000000......0xffff fffffffffffffffffffff fffffffffffffffffffff fffffffffffffffffffff fffffffffffff 0x000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000 no 11-9 lattice semiconductor latticee cp2/m memory usage guide figure 11-6. single port ram timing waveform - normal mode, without output registers figure 11-7. single port ram timing waveform - normal mode, with output registers add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_1 data_2 add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 data_1 clock reset wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr 11-10 lattice semiconductor latticee cp2/m memory usage guide figure 11-8. single port ram timing waveform - write through mode, without output registers figure 11-9. single port ram timing waveform - write through mode, with output registers add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_2 data_0 data_3 data_4 add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clock wren address data q clocken t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 reset 11-11 lattice semiconductor latticee cp2/m memory usage guide true dual port ram (r am_dp_true) ? ebr based the ebr blocks in the latticeecp2/m devices can be c onfigured as true-dual port ram or ram_dp_true. ipexpress allows users to generate th e verilog-hdl, vhdl or edif netlists for the memory size as per design requirements. ipexpress generates the memory module as shown in figure 11-10. figure 11-10. true dual port memory module generated by ipexpress the generated module makes use of these ebr blocks or primitives. for memory sizes smaller than an ebr block, the module will be created in one ebr bl ock. when the specified memory is la rger than one ebr block, multiple ebr blocks can be cascaded in depth or width (as required to create these sizes). in true dual port ram mode, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. the various ports and their definitions for single port memory are listed in table 11-5. the table lists the corre- sponding ports for the module generated by ipexpress and for the ebr ram_dp_true primitive. table 11-5. ebr-based true dual port memory port definitions reset (or rst) resets only the input and output registers of the ram. it does not reset the contents of the memory. chip select (cs) is a useful port in the ebr primitiv e when multiple cascaded ebr blocks are required by the memory. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. since cs is a 3- bit bus, it can cascade eight memories easily. however, if the memory size specified by the user requires more than eight ebr blocks, the isplever software automatically generates t he additional addre ss decoding logic, which is implemented in the pfu external to the ebr blocks. port name in generated module port name in the ebr block primitive description active state clocka, clockb clka, clkb clock for porta and portb rising clock edge clockena, clockenb cea, ceb clock enables for port clka and clkb active high addressa, addressb ada[18:19-x1], adb[18:19-x2] address bus port a and port b ? dataa, datab dia[y1:0], dib[y2:0 ] input data port a and port b ? qa, qb doa[y1:0], dob[y2:0] output data port a and port b ? wra, wrb wea, web write enable port a and port b active high reseta, resetb rsta, rstb reset for porta and portb active high ? csa[2:0], csb[2:0] chip selects for each port ? ram_dp_true ebr-based true dual port memory clocka clockena reseta wra addressa dataina qa clockb clockenb resetb wrb addressb datainb qb 11-12 lattice semiconductor latticee cp2/m memory usage guide each ebr block consists of 18,432 bits of ram. the values for x?s (for address) and y?s (data) for each ebr block for the devices are listed in table 11-6. table 11-6. true dual port memory sizes for 16k memory for latticeecp2/m table 11-7 shows the various attributes available for the single port memory (ram_dq). some of these attributes are user-selectable through the ipexpress gui. for detailed attribute definitions, refer to the appendix a. table 11-7. true dual port ram attributes for latticeecp2/m dual port memory size input data port a input data port b output data port a output data port b address port a [msb:lsb] address port b [msb:lsb] 16k x 1 dia dib doa dob ada[13:0] adb[13:0] 8k x 2 dia[1:0] dib[1:0] doa[1:0 ] dob[1:0] ada[12:0] adb[12:0] 4k x 4 dia[3:0] dib[3:0] doa[3:0 ] dob[3:0] ada[11:0] adb[11:0] 2k x 9 dia[8:0] dib[8:0] doa[8:0 ] dob[8:0] ada[10:0] adb[10:0] 1k x 18 dia[17:0] dib[17:0] doa[ 17:0] dob[17:0] ada[9:0] adb[9:0] attribute description values default value user selectable through ipexpress port a address depth address depth port a 16k, 8k, 4k, 2k, 1k yes port a data width data word width port a 1, 2, 4, 9, 18 1 yes port b address depth address depth port b 16k, 8k, 4k, 2k, 1k yes port b data width data word width port b 1, 2, 4, 9, 18 1 yes port a enable output registers register mode (pipelining) for port a noreg, outreg noreg yes port b enable output registers register mode (pipelining) for port b noreg, outreg noreg yes enable gsr enables global set reset enable, disable enable yes reset mode selects the reset type async, sync async yes memory file format binary, hex, addressed hex yes port a write mode read / write mode for port a normal, write- through normal yes port b write mode read / write mode for port b normal, write- through normal yes chip select decode for port a chip select decode for port a 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no chip select decode for port b chip select decode for port b 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no init value initialization value 0x00000000000000000000 0000000000000000000000 0000000000000000000000 0000000000000000......0xf ffffffffffffffffffff ffffffffffffffffffff ffffffffffffffffffff fffffffffffffffffff 0x000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000 no 11-13 lattice semiconductor latticee cp2/m memory usage guide the true dual port ram (ram_dp_true) can be configured as normal or write through modes. each of these modes affects what data comes out of the port q of the memory during the write operation followed by the read operation at the same memory location. the detailed discussions of the write modes and the constraints of the true dual port can be found in appendix a. additionally, users can select to enable the output registers for ram_dp_true. figures 11-11 through 11-14 show the internal timing waveforms for the true dual port ram (ram_dp_true) with these options. figure 11-11. true dual port ram timing waveform - normal mode, without output registers add_a0 add_a1 add_a0 add_a1 add_a2 data_a0 data_a1 invalid data data_a0 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_a1 data_a2 add_b0 add_b1 add_b0 add_b1 add_b2 data_b0 data_b1 invalid data data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_b1 data_b2 11-14 lattice semiconductor latticee cp2/m memory usage guide figure 11-12. true dual port ram timing waveform - normal mode with output registers add_a0 add_a1 add_a0 add_a1 add_a2 data_a0 data_a1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr add_b0 add_b1 add_b0 add_b1 add_b2 data_b0 data_b1 invalid data data_b0 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_b1 invalid data data_a0 t coo_ebr data_a1 reset 11-15 lattice semiconductor latticee cp2/m memory usage guide figure 11-13. true dual port ram timing wavefo rm - write through mode, without output registers add_a0 add_a1 add_a0 data_a0 data_a1 data_a2 data_a3 data_a4 invalid data data_a1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_a2 data_a0 data_a3 data_a4 add_b0 add_b1 add_b0 data_b0 data_b1 data_b2 data_b3 data_b4 invalid data data_b1 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_b2 data_b0 data_b3 data_b4 11-16 lattice semiconductor latticee cp2/m memory usage guide figure 11-14. true dual port ram timing wavefo rm - write through mode, with output registers add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clocka wrena addressa dataa qa clockena t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 add_0 add_1 add_0 data_0 data_1 data_2 data_3 data_4 invalid data data_1 clockb wrenb addressb datab qb clockenb t suwren_ebr t hwren_ebr t suaddr_ebr t haddr_ebr t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr data_2 data_0 data_3 reset 11-17 lattice semiconductor latticee cp2/m memory usage guide pseudo dual port ram (ram_dp) ? ebr based the ebr blocks in latticeecp2/m devices can be configured as pseudo-dual port ram or ram_dp. ipexpress allows users to generate the verilog-hdl or vhdl along with edif netlists for the memory size as per design requirements. ipexpress generates the memory module as shown in figure 11-15. figure 11-15. pseudo dual port memory module generated by ipexpress the generated module makes use of these ebr blocks or primitives. for memory sizes smaller than an ebr block, the module will be created in one ebr bloc k. if the specified memory is larger than one ebr block, multiple ebr blocks can be cascaded in depth or width (as required to create these sizes). in pseudo dual port ram mode, the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. the various ports and their definitions for the single port memory are listed in table 11-8. the table lists the corre- sponding ports for the module generated by ipexpress and for the ebr ram_dp primitive. table 11-8. ebr-based pseudo-dual port memory port definitions reset (rst) resets only the input and output registers of the ram. it does not reset the contents of the memory. chip select (cs) is a useful port when multiple cascaded ebr blocks are required by the memory. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. since cs is a 3-bit bus, it can cascade eight memories easily. however, if the memory size specifie d by the user requires more than eight ebr blocks, the isplever software automatically generates the additional address decoding logic, which is implemented in the pfu external to the ebr blocks. port name in generated module port name in the ebr block primitive des cription active state rdaddress adr[x1:0] read address ? wraddress adw[x2:0] write address ? rdclock clkr read clock rising clock edge wrclock clkw write clock rising clock edge rdclocken cer read clock enable active high wrclocken cew write clock enable active high q do[y1:0] read data ? data di[y2:0] write data ? we we write enable active high reset rst reset active high ? cs[2:0] chip select ? ram_dp ebr based pseudo dual port memory wrclock wrclocken reset we wraddress data rdclock rdclocken rdaddress q 11-18 lattice semiconductor latticee cp2/m memory usage guide each ebr block consists of 18,432 bits of ram. the values for x?s (for address) and y?s (data) for each ebr block for the devices are as in table 11-9. table 11-9. pseudo-dual port memory sizes for 16k memory for latticeecp2/m table 11-10 shows the various attributes available for the pseudo-dual port memory (ram_dp). some of these attributes are user-selectable through the ipexpress gui. for detailed attribute definitions, refer to appendix a. table 11-10. pseudo-dual port ram attributes for latticeecp2/m pseudo-dual port memory size input data port a input data port b output data port a output data port b read address port a [msb:lsb] write address port b [msb:lsb] 16k x 1 dia dib doa dob rad[13:0] wad[13:0] 8k x 2 dia[1:0] dib[1:0] doa[1:0 ] dob[1:0] rad[12:0] wad[12:0] 4k x 4 dia[3:0] dib[3:0] doa[3:0 ] dob[3:0] rad[11:0] wad[11:0] 2k x 9 dia[8:0] dib[8:0] doa[8:0 ] dob[8:0] rad[10:0] wad[10:0] 1k x 18 dia[17:0] dib[17:0] doa[ 17:0] dob[17:0] ra d[9:0] wad[9:0] 512 x 36 dia[35:0] dib[35:0] doa[35 :0] dob[35:0] ra d[8:0] wad[8:0] attribute description values default value user selectable through ipexpress read port address depth address depth read port 16k, 8k, 4k, 2k, 1k, 512 yes read port data width data word width read port 1, 2, 4, 9, 18, 36 1 yes write port address depth address depth write port 16k, 8k, 4k, 2k, 1k yes write port data width data word width write port 1, 2, 4, 9, 18, 36 1 yes write port enable out- put registers register mode (pipelining) for write port noreg, outreg noreg yes enable gsr enables global set reset enable, disable enable yes reset mode selects the reset type async, sync async yes memory file format binary, hex, addressed hex yes read port write mode read / write mode for read port normal normal yes write port write mode read / write mode for write port normal normal yes chip select decode for read port chip select decode for read port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no chip select decode for write port chip select decode for write port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no init value initialization value 0x0000000000000000000000000 000000000000000000000000000 000000000000000000000000000 0......0xfffffffffffffffffff ffffffffffffffffffffffff ffffffffffffffffffffffff fffffffffffff 0x000000000000 00000000000000 00000000000000 00000000000000 00000000000000 000000000000 no 11-19 lattice semiconductor latticee cp2/m memory usage guide users have the option to enable the output registers for pseudo-dual port ram (ram_dp). figures 11-16 and 11- 17 show the internal timing waveforms for pseudo-dual port ram (ram_dp) with these options. figure 11-16. pseudo dual port ram ti ming diagram - withou t output registers data_0 data_1 data_2 invalid data data_0 wrclock data q wrclocken t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t co_ebr data_1 dat a_2 add_0 add_1 add_2 rdaddress t suaddr_ebr t haddr_ebr rdclock rdclocken t suce_ebr t hce_ebr add_0 add_1 add_2 wraddress t suaddr_ebr t haddr_ebr 11-20 lattice semiconductor latticee cp2/m memory usage guide figure 11-17. pseudo dual port ram ti ming diagram - with output registers read only memory (rom) - ebr based the ebr blocks in the latticeecp2/m devices can be config ured as read only memory or rom. ipexpress allows users to generate the verilog-hdl or vhdl and the edif netlist for the memory size, as per design requirements. users are required to provide the rom memory content in the form of an initialization file. ipexpress generates the memory module as shown in figure 11-18. figure 11-18. read-only memory module generated by ipexpress the generated module makes use of these ebr blocks or primitives. for memory sizes smaller than an ebr block, the module will be created in one ebr bloc k. if the specified memory is larger than one ebr block, multiple ebr blocks can be cascaded, in depth or width (as required to create these sizes). in rom mode, the address for the port is registered at the input of the memory array. the output data of the mem- ory is optionally registered at the output. data_0 data_1 data_2 invalid data data_0 wrclock data q wrclocken t sudata_ebr t hdata_ebr t suce_ebr t hce_ebr t coo_ebr dat a_1 add_0 add_1 add_2 rdaddress t suaddr_ebr t haddr_ebr rdclock rdclocken t suce_ebr t hce_ebr add_0 add_1 add_2 wraddress t suaddr_ebr t haddr_ebr rom ebr based read only memory outclock outclocken reset address q 11-21 lattice semiconductor latticee cp2/m memory usage guide the various ports and their definitions for the rom are listed in table 11-11. the table lists the corresponding ports for the module generated by ipexpress and for the rom primitive. table 11-11. ebr-based rom port definitions reset (rst) resets only the input and output registers of the ram. it does not reset the contents of the memory. chip select (cs) is a useful port when multiple cascaded ebr blocks are required by the memory. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. since cs is a 3-bit bus, it can cascade eight memories easily. however, if the memory size specifie d by the user requires more than eight ebr blocks, the isplever software automatically generates the additional address decoding logic, which is implemented in the pfu external to the ebr blocks. while generating the rom using ipexpress, the user must pr ovide the initialization file to pre-initialize the contents of the rom. these files are the *.mem files and they can be of binary, hex or the addressed hex formats. the ini- tialization files are discussed in detail in the initializing memory sect ion of this document. users have the option of enabling the output registers for read only memory (rom). figures 11-19 and 11-20 show the internal timing waveforms for the read only memory (rom) with these options. each ebr block consists of 18,432 bits of ram. the values for x?s (for address) and y?s (data) for each ebr block for the devices are as per table 11-12. table 11-12. rom memory sizes for 16k memory for latticeecp2/m table 11-13 shows the various attributes available for the read only memory (rom). some of these attributes are user-selectable through the ipexpress gui. for detailed attribute definitions, refer to appendix a. port name in generated module port name in the ebr block primitive description active state address ad[x:0] read address ? outclock clk clock rising clock edge outclocken ce clock enable active high reset rst reset active high ? cs[2:0] chip select ? rom output data address port [msb:lsb] 16k x 1 doa wad[13:0] 8k x 2 doa[1:0] wad[12:0] 4k x 4 doa[3:0] wad[11:0] 2k x 9 doa[8:0] wad[10:0] 1k x 18 doa[17:0] wad[9:0] 512 x 36 doa[35:0] wad[8:0] 11-22 lattice semiconductor latticee cp2/m memory usage guide table 11-13. rom attributes for latticeecp2/m figure 11-19. rom timing waveform - without output registers figure 11-20. rom timing waveform - with output registers attribute description values default value user selectable through ipexpress address depth address depth read port 16k, 8k, 4k, 2k, 1k, 512 yes data width data word width read port 1, 2, 4, 9, 18, 36 1 yes enable output registers register mode (pi pelining) for write port noreg, outreg noreg yes enable gsr enables global se t reset enable, disable enable yes reset mode selects the re set type async, sync async yes memory file format binary, hex, addressed hex yes chip select decode chip select decode for read port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 no add_0 add_1 add_2 add_3 add_4 invalid data data_0 outclock address q outclocken t suaddr_ebr t haddr_ebr t suce_ebr t hce_ebr t co_ebr data_1 data_2 data_3 data_4 add_0 add_1 add_2 add_3 add_4 invalid data data_0 outclock address q outclocken t suaddr_ebr t haddr_ebr t suce_ebr t hce_ebr t coo_ebr data_1 data_2 data_3 11-23 lattice semiconductor latticee cp2/m memory usage guide first in first out (fifo, fifo_dc) ? ebr based the hardware has embedded block ram (ebr) which can be configured in single port (ram_dq), pseudo-dual port (ram_dp) and true dual port (ram_dp_true) rams. the fifos in these devices can be built using these rams. the ipexpress point tool in the isplever design software allows users to build a fifo and fifo_dc around pseudo dual port ram (or dp_ram). each of these fifos can be configured with (pipelined) and without (non-pipelined) output registers. in the pipe- lined mode users have an extra option to enable the outp ut registers by the rden si gnal. we will discuss the oper- ation in the following sections. let us take a look at the operation of these fifos. first in first out (fifo) memory the fifo, or the single clock fifo, is an emulated fifo. the address logic and the flag logic is implemented in the fpga fabric around the ram. the ports available on the fifo are: ? reset ?clock ?wren ?rden ?data ?q ? full flag ? almost full flag ? empty flag ? almost empty flag let us first discuss the non-pipelined or the fifo without output registers. figure 11-21 shows the operation of the fifo when it is empty and the data starts to get written into it. 11-24 lattice semiconductor latticee cp2/m memory usage guide figure 11-21. fifo without output re gisters, start of data write cycle the wren signal must be high to start writing into the fifo. the empty and almost empty flags are high to begin and full and almost full are low. when the first data is written into the fifo, the empty flag de-asserts (or goes low), as the fifo is no longer empty. in this figure we assume that the almost empty setting flag setting is 3 (address location 3). so the almost empty flag gets de-asserted when the third address location is filled. now let us assume that we cont inue to write into the fifo to fill it. when the fifo is f illed, the almost full and full flags are asserted. figure 11-22 shows the behavior of these flags. in this figure we assume that fifo depth is 'n'. figure 11-22. fifo without output registers, end of data write cycle in this case, the almost full flag is in the 2 location before the fifo is filled. the almost full flag is asserted when the n-2 location is written, and the full flag is a sserted when the last word is written into the fifo. data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid q q data_n-2 data_n-1 data_n data_x clock reset wren rden data empty almost empty full almost full invalid q q data_x 11-25 lattice semiconductor latticee cp2/m memory usage guide data_x data inputs do not get written as the fifo is full (the full flag is high). now let us look at the waveforms when the contents of the fifo are read out. figure 11-23 shows the start of the read cycle. rden goes high and the data read starts. the full and almost full flags are de-asserted, as shown. figure 11-23. fifo without output registers, start of data read cycle similarly, as the data is read out and fifo is emptied, the almost empty and empty flags are asserted. figure 11-24. fifo without output registers, end of data read cycle figures 11-21 to 11-24 show the behavior of non-pipelined fifo or fifo without output registers. when we pipe- line the registers, the output data is delayed by one clock cycle. there is also the extra option for output registers to be enabled by the rden signal. data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid data q data_n-3 data_n-2 data_n-1 data_n clock reset wren rden data empty almost empty full almost full invalid data q data_n-4 11-26 lattice semiconductor latticee cp2/m memory usage guide figures 11-25 to 11-28 show the similar waveforms for the fifo with output register and with output register enable with rden. it should be noted that flags are asserted and de-asserted with similar timing to the fifo without output registers. however, it is only the data out 'q' that is delayed by one clock cycle. figure 11-25. fifo with output registers, start of data write cycle figure 11-26. fifo with output registers, end of data write cycle data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full invalid q q data_n-2 data_n-1 data_n data_x clock reset wren rden data empty almost empty full almost full invalid q q data_x 11-27 lattice semiconductor latticee cp2/m memory usage guide figure 11-27. fifo with output registers, start of data read cycle figure 11-28. fifo with output registers, end of data read cycle and finally, if you select the option enab le output register with rden, it still delays the data out by one clock cycle (as compared to the non-pipelined fifo). the rden should also be high during that clock cycle, otherwise the data takes an extra clock cycle when the rden goes true. data_1 invalid data data_2 data_3 data_4 clock reset wren rden data empty almost empty full almost full invalid data q data_n-4 data_n-3 data_n-2 data_n-1 data_n clock reset wren rden data empty almost empty full almost full invalid data q data_n-5 11-28 lattice semiconductor latticee cp2/m memory usage guide figure 11-29. fifo with output registers and rden on output registers dual clock first in first out (fifo_dc) memory: the fifo_dc or the dual clock fifo is also an emulated fifo. again, the address logic and the flag logic is imple- mented in the fpga fabric around the ram. the ports available on the fifo_dc are: ? reset ? rpreset ? wrclock ?rdclock ?wren ?rden ?data ?q ? full flag ? almost full flag ? empty flag ? almost empty flag fifo_dc flags the fifo_dc, as an emulated fifo, required the flags to be implemented in the fpga logic around the block ram. because of the two clocks, the flags were required to change clock domains from read clock to write clock and vice versa. this adds latency to the flags either dur ing assertion or de-assertion. the latency can be avoided only in one of the cases (either assertion or de-assertion) or distributed among these cases. in the current emulated fifo_dc, there is no latency during assertion of these flags which we feel is more impor- tant. thus, when these flags are required to go true, there is no latency. however, due to the design of the flag logic running on two clock domains, there is latency during the de-assertion. data_1 invalid data data_2 data_3 data_4 data_5 clock reset wren rden data empty almost empty full almost full q data_1 invalid data data_2 11-29 lattice semiconductor latticee cp2/m memory usage guide let us assume that we start to write into the fifo _dc to fill it. the write operatio n is controlled by wrclock and wren, however it takes extra rdclock cycles for de-assertion of the empty and almost empty flags. on the other hand, de-assertion of full and almost full result in the reading out of the data from the fifo_dc. it takes extra wrclock cycles, after reading this data, for the flags to come out. with this in mind, let us look at the fifo_dc without output registers waveforms. figure 11-30 shows the operation of the fifo_dc when it is empty and the data starts to be written into it. figure 11-30. fifo_dc without output registers, start of data write cycle the wren signal must be high to start writing into the fifo_dc. the empty and almost empty flags are high to begin and full and almost full are low. when the first data is written into the fifo_dc, the empty flag de-asserts (or goes low), as the fifo_dc is no lon- ger empty. in this figure we assume that the almost empty setting flag setting is 3 (address location 3). so the almost empty flag is de-asserted when the third address location is filled. now let us assume that we continue to write into the fifo_dc to fill it. when the fifo_dc is fille d, the almost full and full flags are asserted. figure 11-31 shows the behavior of these flags. in this figure the fifo_dc depth is 'n'. data_1 invalid data data_2 data_3 data_4 data_5 wrclock reset wren rden data empty almost empty full almost full invalid q q rdclock rpreset 11-30 lattice semiconductor latticee cp2/m memory usage guide figure 11-31. fifo_dc without output registers, end of data write cycle in this case, the almost full flag is in the 2 location be fore the fifo_dc is filled. th e almost full flag is asserted when the n-2 location is written, and the full flag is asserted when the last word is written into the fifo_dc. data_x data inputs do not get written as the fifo_dc is full (the full flag is high). note that the assertion of these flags is immediate and there is no latency when they go true. now let us look at the waveforms when the contents of the fifo_dc are read out. figure 11-32 shows the start of the read cycle. rden goes high and the data read starts. the full and almost full flags are de-asserted, as shown. in this case, note that the de-assertion is delayed by two clock cycles. wrclock reset empty almost empty full almost full invalid q q rdclock rpreset data_n-2 data_n-1 data_n data_x data_x wren rden data 11-31 lattice semiconductor latticee cp2/m memory usage guide figure 11-32. fifo_dc without output registers, start of data read cycle similarly, as the data is read out, and fifo_dc is emptied, the almost empty and empty flags are asserted. figure 11-33. fifo_dc without output registers, end of data read cycle wrclock reset empty almost empty full almost full invalid data q rdclock rpreset data_1 data_2 invalid q wren rden data data_3 data_6 data_5 data_4 wrclock reset empty almost empty full almost full invalid data q rdclock rpreset wren rden data data_n-2 data_n-1 data_n data_n data_n-3 11-32 lattice semiconductor latticee cp2/m memory usage guide figure 11-33 show the behavior of non-pipelined fifo_dc or fifo_dc without output registers. when we pipeline the registers, the output data is delayed by one clock cycle. there is an extra option for the output registers to be enabled by the rden signal. figures 11-34 to 11-37 show the similar waveforms for the fifo_dc with output register and without output regis- ter enable with rden. note that flags are asserted and de-asserted with similar timing to the fifo_dc without out- put registers. however, it is only the data out 'q' that is delayed by one clock cycle. figure 11-34. fifo_dc with output registers, start of data write cycle data_1 invalid data data_2 data_3 data_4 data_5 wrclock reset wren rden data empty almost empty full almost full invalid q q rdclock rpreset 11-33 lattice semiconductor latticee cp2/m memory usage guide figure 11-35. fifo_dc with output registers, end of data write cycle figure 11-36. fifo_dc with output registers, start of data read cycle wrclock reset empty almost empty full almost full invalid q q rdclock rpreset data_n-2 data_n-1 data_n invalid data invalid data wren rden data wrclock reset empty almost empty full almost full invalid data q rdclock rpreset data_1 invalid q wren rden data data_2 data_5 data_4 data_3 11-34 lattice semiconductor latticee cp2/m memory usage guide figure 11-37. fifo_dc with output registers, end of data read cycle and finally, if you select the option to en able the output register with rden, it still delays the data out by one clock cycle (as compared to the non -pipelined fifo_dc). the rd en should also be high during that clock cycle, other- wise the data takes an extra clock cycle when the rden is goes true. figure 11-38. fifo_dc with output registers and rden on output registers wrclock reset empty almost empty full almost full invalid data q rdclock rpreset wren rden data data_n-3 data_n-2 data_1 data_n data_n-4 wrclock reset empty almost empty full almost full invalid data q rdclock rpreset invalid q wren rden data data_3 data_2 data_1 11-35 lattice semiconductor latticee cp2/m memory usage guide distributed single port ram (d istributed_spram ) ? pfu based pfu-based distributed single port ram is created using the 4-input lut (look-up table) available in the pfu. these luts can be cascaded to create larger distributed memory sizes. figure 11-39 shows the distributed single port ram module as generated by ipexpress. figure 11-39. distributed single port ram module generated by ipexpress the generated module makes use 4-input lut available in the pfu. additional logic like clock, reset is generated by utilizing the resources available in the pfu. ports such as read clock (rdclock) and read clock enable (rdclocken), are not available in the hardware prim- itive. these are generated by ipexpress when the user wants the to enable the output registers in their ipexpress configuration. the various ports and their definitions for the memory ar e as per table 11-14. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. table 11-14. pfu-based distributed single port ram port definitions ports such as clock enable (clocken) are not available in the hardware primitive. these are generated by ipex- press when the user wishes to enable the output registers in the ipexpress configuration. users have the option of enabling the output registers for distributed single port ram (distributed_spram). fig- ures 11-40 and 11-41 show the internal timing waveforms for the distributed single port ram (distributed_spram) with these options. port name in generated module port name in the pfu primitive description active state clock ck clock rising clock edge clocken ? clock enable active high reset ? reset active high we wre write enable active high address ad[3:0] address ? data di[1:0] data in ? q do[1:0] data out ? pfu based distributed single port memory clock clocken reset we address q data 11-36 lattice semiconductor latticee cp2/m memory usage guide figure 11-40. pfu based distri buted single port ram timing waveform - without output registers figure 11-41. pfu based distri buted single port ram timing waveform - with output registers distributed dual port ram (distributed_dpram) ? pfu based pfu-based distributed dual port ram is also created using the 4-input lut (look-up table) available in the pfu. these luts can be cascaded to create a larger distributed memory sizes. add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 clock we address data q clocken hwren_pfu suaddr_pfu haddr_pfu sudata_pfu hdata_pfu coram_pfu data_1 t t t t t t t suwren_pfu data_2 add_0 add_1 add_0 add_1 add_2 data_0 data_1 invalid data data_0 clock we t t t t t t address data q clocken hwren_pfu suaddr_pfu haddr_pfu sudata_pfu hdata_pfu co suwren_pfu reset data_1 data_2 11-37 lattice semiconductor latticee cp2/m memory usage guide figure 11-42. distributed dual port ram module generated by ipexpress the generated module makes use of the 4-input lut available in the pfu. additional logic like clock and reset is generated by utilizing the res ources available in the pfu. ports such as read clock (rdclock) and read clock enable (rdclocken), are not available in the hardware prim- itive. these are generated by ipexpress when the user wants the to enable the output registers in the ipexpress configuration. the various ports and their definitions for memory are as per table 11-15. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. table 11-15. pfu-based distributed dual-port ram port definitions ports such as read clock (rdclock) and read clock enab le (rdclocken) are not ava ilable in the hardware primi- tive. these are generated by ipexpress when the user wants to enable the output registers in the ipexpress config- uration. users have the option of enabling the output registers for distributed dual port ram (distributed_dpram). fig- ures 11-43 and 11-44 show the internal timing waveforms for the distributed dual port ram (distributed_dpram) with these options. port name in generated module port name in the ebr block primitive description active state wraddress wad[3:0] write address ? rdaddress rad[3:0] read address ? rdclock ? read clock rising clock edge rdclocken ? read clock enable active high wrclock wck write clock rising clock edge wrclocken ? write clock enable active high we wre write enable active high data di[1:0] data input ? q rdo[1:0] data out ? pfu based distributed dual port memory wraddress rdaddress rdclock rdclocken reset q we wrclock wrclocken data 11-38 lattice semiconductor latticee cp2/m memory usage guide figure 11-43. pfu based distributed dual port ram timing waveform - without output registers data_0 data_1 data_2 invalid data wrclock data q wrclocken sudata_ebr hdata_ebr coram_pfu suce_ebr hce_ebr rdaddress add_0 add_1 add_2 wraddress suaddr_ebr haddr_ebr we add_0 add_1 add_2 data_0 t t t t t t t data_1 data_2 11-39 lattice semiconductor latticee cp2/m memory usage guide figure 11-44. pfu based distributed dual port ram timing waveform - with output registers distributed rom (distr ibuted_rom) ? pfu based pfu-based distributed rom is also created using the 4-input lut (look-up table) available in the pfu. these luts can be cascaded to create larger distributed memory sizes. figure 11-45 shows the distributed rom module as generated by ipexpress. figure 11-45. distributed rom generated by ipexpress the generated module makes use of the 4-input lut available in the pfu. additional logic like clock and reset is generated by utilizing the res ources available in the pfu. data_0 data_1 invalid data data_0 wrclock data q wrclocken t t t t t t t t t t t sudata_pfu hdata_pfu suwren_pfu hwren_pfu coram_pfu data_1 add_0 add_1 rdaddress rdclock rdclocken suce_pfu hce_pfu add_0 add_1 wraddress suaddr_pfu haddr_pfu reset we suwren_pfu hwren_pfu pfu-based distributed rom address outclock outclocken reset q 11-40 lattice semiconductor latticee cp2/m memory usage guide ports such as out clock (outclock) and out clock enable (outclocken) are not available in the hardware primi- tive. these are generated by ipexpress when the user wants to enable the output registers in the ipexpress config- uration. the various ports and their definitions for memory are as per table 11-16. the table lists the corresponding ports for the module generated by ipexpress and for the primitive. table 11-16. pfu-based distributed rom port definitions users have the option to enable the output registers for distributed rom (distributed_rom). figures 11-46 and 11-47 show the internal timing waveforms for the distributed rom with these options. figure 11-46. pfu based rom timing waveform ? without output registers figure 11-47. pfu based rom timing waveform ? with output registers port name in generated module port name in the pfu block primitive description active state address ad[3:0] address ? outclock ? out clock rising clock edge outclocken ? out clock enable active high reset ? reset active high q do data out ? add_0 tt t add_1 add_2 invalid data data_0 address q suaddr_pfu haddr_pfu coram_pfu data_1 data_2 add_0 tt t add_1 add_2 invalid data data_0 outclock address q outclocken suaddr_pfu haddr_pfu data_1 reset coram_pfu 11-41 lattice semiconductor latticee cp2/m memory usage guide initializing memory in the ebr based rom or ram memory modes and the pfu based rom memory mode, it is possible to specify the power-on state of each bit in the memory array. each bit in the memory array can have one of two values: 0 or 1. initialization file format the initialization file is an ascii file, which users can cr eate or edit using any ascii editor. ipexpress supports three types of memory file formats: ? binary file ? hex file ? addressed hex the file name for the memory initialization file is *.me m ( 11-42 lattice semiconductor latticee cp2/m memory usage guide hex file the hex file is essentially a text file of hex characters arranged in a similar row-column arrangement. the number of rows in the file is same as the number of address locations, with each row indicating the content of the memory location. memory size 8x16 a001 0b03 1004 ce06 0007 040a 0017 02a4 addressed hex addressed hex consists of lines of address and data. each line starts with an address, followed by a colon, and any number of data. the format of memfile is address: data data data data ... where address and data are hexa- decimal numbers. -a0 : 03 f3 3e 4f -b2 : 3b 9f the first line puts 03 at address a0, f3 at address a1, 3e at address a2,and 4f at address a3. the second line puts 3b at address b2 and 9f at address b3. there is no limitation on the values of address and data . the value range is automatically checked based on the values of addr_width and data_width. if there is an error in an address or data value, an error message is printed. users need not specify data at all address locations. if data is not specified at certain address, the data at that loca- tion is initialized to 0. ipexpress makes memory initialization possible both through the synthesis and simulation flows. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com 11-43 lattice semiconductor latticee cp2/m memory usage guide revision history date version change summary february 2006 01.0 initial release. april 2006 01.1 updated the initializing memory section september 2006 01.2 added latticeecp2m device information. added dual port memory access notes. april 2007 01.3 updated utilizing ipexpress section. february 2008 01.4 updated pseudo-dual port ram attributes for latticeecp2/m table. march 2008 01.5 updated fifo_dc without output re gisters (non-pipelined) figure. june 2008 01.6 updated first in first out (fifo, fifo_dc) ? ebr based section. removed read-before-write sysmem ebr mode. august 2008 01.7 corrected addressa, addressb information in ebr-based true dual port memory port definitions table. september 2008 01.8 updated ipexpress flow text section. march 2009 01.9 updated memory modules text section. 11-44 lattice semiconductor latticee cp2/m memory usage guide appendix a. attribute definitions data_width data width is associated with the ra m and fifo elements. the data_width attribute will define the number of bits in each word. it takes the values as defined in the ram size tables in each memory module. regmode regmode or the register mode attribute is used to enable pipelining in the memory. this attribute is associated with the ram and fifo elements. the regmode attribute takes the noreg or outreg mode parameter that disables and enables the output pipeline registers. resetmode the resetmode attribute allows users to select the mode of re set in the memory. this attribute is associated with the block ram elements. resetmode takes two parameters: sync and async. sync means that the memory reset is synchronized with th e clock. async means that the memory reset is asynch ronous to clock. csdecode csdecode or the chip select decode attributes are asso ciated to block ram elements. cs, or chip select, is the port available in the ebr primitive that is useful when memory requires multiple ebr blocks cascaded. the cs signal forms the msb for the address when multiple ebr blocks are cascaded. cs is a 3-bit bus, so it can cascade eight memories easily. csdecode takes the following parameters: ?000?, ?001?, ?010?, ?011?, ?100?, ?101?, ?110?, and ?111?. csdecode values determine the decoding val ue of cs[2:0]. csdecode_w is chip select decode for write and csdecode_r is chip select decode for read for pseudo dual port ram. csdecode_a and csdecode_b are used for true dual port ram elements and refer to the a and b ports. writemode the writemode attribute is associated with the block ram elements. it takes the normal and write- through mode parameters. in normal mode, the output data does not change or get updated, during the write operation. this mode is sup- ported for all data widths. in writethrough mode, the output data is updated with the input data during the write cycle. this mode is sup- ported for all data widths. writemode_a and writemode_b are used for dual port ram elements and refer to the a and b ports in case of a true dual port ram. for all modes (of the true dual port module), simultaneous read access from one port and write access from the other port to the same memory address is not recommended. the read data may be unknown in this situation. also, simultaneous write access to the same address fr om both ports is not recommended. (when this occurs, the data stored in the address becomes undetermined when one port tries to write a ?h? and the other tries to write a ?l?). it is recommended that the designer implements control logi c to identify this situatio n if it occurs and either: 1. implement status signals to flag the read data as possibly invalid, or 2. implement control logic to prevent the simultaneous access from both ports. gsr gsr or the global set/ reset attribute is used to enable or disable the global set/reset for ram element. www.latticesemi.com 12-1 tn1105_01.8 june 2010 technical note tn1105 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction latticeecp2? and latticeecp2m? devices support double data rate (ddr) and single data rate (sdr) inter- faces using the logic built into the programmable i/o (pio). sdr applications capture data on one edge of a clock while the ddr interfaces captur e data on both the rising and falling edges of the clock, thus doubling performance. the latticeecp2/m i/os also have dedicated circuitry to support ddr and ddr2 sdram memory interfaces. this technical note details the use of latticeecp2/m devices to implement both a high-speed generic ddr interface and ddr and ddr2 memory interfaces. ddr and ddr2 sdram interfaces overview a ddr sdram interface will transfer data at both the rising and falling edges of the clock. the ddr2 is the second generation of the ddr srdram memory. the ddr and ddr2 sdram interfaces rely on the use of a data strobe signal, called dqs, for high-speed opera- tion. the ddr sdram interface uses a single-ended dqs strobe signal, whereas the ddr2 interface uses a dif- ferential dqs strobe. figures 12-1 and 12-2 show typical ddr and ddr2 sdram interface signals. sdram interfaces are typically impl emented with eight dq data bits per dqs. an x16 inte rface will use two dqs signals and each dqs is associated with eight dq bits. both the dq and dqs are bi-directional ports used to both read and write to the memory. when reading data from the external memory device, data coming into the device is edge-aligned with respect to the dqs signal. this dqs strobe signal needs to be phase-shifted 90 degrees before fpga logic can sample the read data. when writing to a ddr/ ddr2 sdram, the memory controller (fpga) must shift the dqs by 90 degrees to center-align with the data signals (dq). a clock si gnal is also provided to the memory. this clock is pro- vided as a differential clock (clkp and clkn) to minimize duty cycle variations. the memory also uses these clock signals to generate the dqs signal during a read via a dll inside the memory. figures 12-3 and 12-4 show dq and dqs timing relationships for read and write cycles. for other detailed timing requirements, please refer to the ddr sdram jedec specification (jesd79c). during read, the dqs signal is low for some duration after it comes out of tristate. th is state is called preamble. the state when the dqs is low before it goes into tristate is the postamble state. this is the state after the last valid data transition. ddr sdram also requires a data mask (dm) signal to mask data bits during write cycles. note that the ratio of dqs to data bits is independen t of the overall width of the memory. an 8-bit interface will have one strobe signal. ddr sdram interfaces use the sstl25 class i/ii i/o standards whereas the ddr2 sdram interface uses the sstl18 class i/ii i/o standards. the ddr2 sdram interface also supports differential dqs (dqs and dqs#). latticeecp2/m high-speed i/o interface 12-2 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-1. typical ddr sdram interface figure 12-2. typical ddr2 sdram interface the following two figures show the dq and dqs relationship for memory read and write interfaces. figure 12-3. dq-dqs during read ddr memory fpga (ddr memory controller) 8 dq<7:0> dm dq<7:0> dqs address control command clk/clkn address control command clkp/clkn x address control command dq<7:0> dqs clk/clkn y z dqs dm dm fpga (ddr memory controller) ddr memory 8 dq<7:0> dm dq<7:0> dqs, dqs# address control command clk/clkn address control command clkp/clkn x address control command dq<7:0> dqs, dqs# clk/clkn y z dqs, dqs# dm dm dqs (at pin) preamble postamble dqs pin to reg and 90 degree phase shift dq (at pin) dqs (at reg) dq (at reg) 12-3 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-4. dq-dqs during write implementing ddr memory interfaces with latticeecp2/m devices as described in the ddrsdram overview section, the ddr sdram interfaces rely primarily on the use of a data strobe signal called dqs for high-speed operation. when reading data from the external memory device, data coming into the latticeecp2/m device is edge-aligned with respect to the dqs signal. therefore, the latticeecp2/m device needs to shift the dqs (a 90-degree phase shift) before using it to sample the read data. when writing to a ddr sdram, the memory controller from the latticeecp2/m device must generate a dqs sig- nal that is center-aligned with the dq, the data signals. this is accomplished by ensuring the dqs strobe is 90 degrees ahead relative to dq data. latticeecp2/m devices have dedicated dqs support circuitry for generating the appropriate phase shifting for dqs. the dqs phase shift circuit uses a frequency refere nce dll to generate delay control signals associated with each of the dedicated dqs pins and is designed to compensate for process, voltage and temperature (pvt) variations. the frequency reference is provided through one of the global clock pins. the dedicated ddr support circuit is al so designed to provide comfortable and consistent marg ins for data sam- pling window. this section describes how to implement the read and write sectio ns of a ddr memory interface. it also provides details of the dq and dqs grouping rules associated with the latticeecp2/m devices. dqs grouping each dqs group generally consists of at least 10 i/os (one dqs, eight dq and one dm) to implement a complete 8-bit ddr memory interface. la tticeecp2/m devices support dqs signals on the bottom, left and right sides of the device. each dqs signal on the bottom half of the device will span across 18 i/os and on the left and ri ght sides of the device will span across 16 i/os. any 10 of these i/os spanned by the dqs can be us ed to implement an 8-bit ddr memory interface. figure 12-5. dq-dqs grouping dqs (at pin) dq (at pin) dqs pad n* i/o pads (ninth i/o pad) dq or dm dq or dm *n=18 on bottom banks and n=16 on the left and right side banks. 12-4 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-5 shows a typical dq-dqs group for a latticeecp2 /m device. the ninth i/o of this group of 16 i/os (on the left and right side banks) and 18 i/os (on the bottom bank) is the dedicated dqs pin. all eight pads before of the dqs and 7 (on the left and right side) and 9 (on the bottom bank) pads after the dqs are covered by this dqs bus span. the user can assign any eight of these i/o pads to be dq data pins. therefore, to implement a 32-bit wide memory interface you would need to use four such dq-dqs groups. when not interfacing with the memory, the dedicated dqs pin can be used as a general purpose i/o. each of the dedicated dqs pins is internally connected to the dqs phase shift circuitry. the pinout information contained in the latticeecp2/m family data sheet shows pin locations for the dqs pads. table 12-1 shows an extract from the data sheet. in this case, the dqs is marked as ldqs8 (l = left side, 8 = associated pfu row/column). since dqs is always the fifth true pad in the dq-dqs gr oup, counting from low to high pf u row/column number, ldqs6 will cover pl2a to pl11b. following this convention, there are eight pads before and seven pads after dqs for dq available following counter-clockwise for the left and bottom sides of the device and following clockwise for the top and right sides of the device. the user can assign any eight of these pads to be dq data signals. table 12-1. ecp2-50 672 fpbga pinout from latticeecp2/m family data sheet ball number ball function ba nk dual function differential d2 pl2a 7 vref2_7 t* d1 pl2b 7 vref1_7 c* gnd gndio 7 f6 pl5a 7 t f5 pl5b 7 c vccio vccio 7 e4 pl6a 7 t* e3 pl6b 7 c* vcc vcc 7 e2 pl7a 7 t e1 pl7b 7 c gnd gndio 7 gnd gnd 7 h6 pl8a 7 ldqs8 t* h5 pl8b 7 c* f2 pl9a 7 t vccio vccio 7 f1 pl9b 7 c h8 pl10a 7 t* j9 pl10b 7 c* g4 pl11a 7 t gnd gndio 7 g3 pl11b 7 c h7 pl12a 7 t* vccaux vccaux 7 12-5 latticeecp2/m lattice semiconductor hi gh-speed i/o interface ddr software primitives this section describes the software primitives that ca n be used to implement ddr in terfaces. these primitives include: ? dqsdll ? the dqs delay calibration dll ? dqsbufc ? the dqs delay function and the clock polarity selection logic ? iddrmx1a ? the ddr input and dqs to system clock transfer registers with half clock cycle transfer ? iddrmfx1a ? the ddr input and dqs to system clock transfer registers with full clock cycle transfer ? oddrmxa ? the ddr output registers hdl usage examples for each of these primitives are listed in appendices a and b. dqsdll the dqsdll generates a 90-degree phase shift required for the dqs signal. this primitive implements the on- chip dqsdll. only one dqsdll should be instantiated for all the ddr implementations on one half of the device. the clock input to this dll should be at the same freq uency as the ddr interface. the dll generates the delay based on this clock frequency and the update control input to this block. the dll updates the dynamic delay con- trol to the dqs delay block when this update control ( uddcntl) input is asserted. fi gure 12-6 shows the primitive symbol. the active low signal on uddcntl updates the dqs phase alignment and should be initiated at the beginning of read cycles. figure 12-6. dqsdll symbol table 12-2 provides a description of the ports. table 12-2. dqsdll ports dqsdll update control: the dqs delay can be updated for pvt variation using the uddcntl input. the dqsdel is updated when the when the uddcntl is held low. the dqsdel can be updated when variations are expected. dqsdel can be updated anytime, except when the memory controller is receiving data from the memory. dqsdll configuration: by default, this dll will generate a 90-degre e phase shift for the dqs strobe based on the frequency of the input reference clock to the dll. the user can control the sensitivity to jitter by using the lock_sensitivity attribute. this configuration bit can be programmed to be either ?high? or ?low?. the dll lock detect circuit has two modes of operation controlled by the lock_sensitivity bit, which selects more or less sensitivity to jitter. if this dll is operated at or above 150 mhz, it is recommended that the lock_sensitivity bit be programmed ?high? (more sensitive). when running at or below 100 mhz, it is recom- port name i/o description clk i system clk should be at the frequency of the ddr interface from the fpga core. rst i resets the dqsdll uddcntl i provides update signal to the d ll that will update the dynamic delay. lock o indicates when the dll is in phase. dqsdel o the digital delay generated by the dll, should be connected to the dqsbuf primitive. clk rst uddcntl lock dqsdel dqsdll 12-6 latticeecp2/m lattice semiconductor hi gh-speed i/o interface mended that the bit be programmed ?low? (more tolerant). for 133 mhz, the lock_sensitivity bit can go either way. dqsbufc this primitive implements the dqs dela y and the dqs transition detector logic. figure 12-7 shows the primitive symbol. figure 12-7. dqsbufc symbol the dqsbufc is composed of the dqs delay, the dqs transition detect and the dqsxfer block as shown in figure 12-8. this block inputs the dqs and delays it by 90 degrees. it also generates the ddr clock polarity and the dqsxfer signal. the preamble detect (prmbdet) signal is generated from the dqsi input using a voltage divider circuit. figure 12-8. dqsbufc function dqsi dqso dqsbufc clk read ddrclkpol dqsc prmbdet dqsdel xclk dqsxfer datavalid dqs delay dqs transition detect prmbdet dqsi dqso + - + - vref- dv* *dv ~ 170mv for ddr1 (sstl25 signaling) *dv ~ 120mv for ddr2 (sstl18 signaling) read fpga clk dqsdel vref ddrclkpol dqsc prmbdet dqsxfer xclk dqsxfer data valid module datavalid 12-7 latticeecp2/m lattice semiconductor hi gh-speed i/o interface dqs delay block: the dqs delay block receives the digital control delay line (dqsdel) coming from one of the two dqsdll blocks. these control signals are used to delay the dqsi by 90 degrees. dqso is the delayed dqs and is connected to the clock input of the first set of ddr registers. dqs transition detect: the dqs transition detect block generates the ddr clock polarity signal based on the phase of the fpga clock at the first dqs transition. the ddr read control signal and fpga clk inputs to this coming and should be coming from the fpga core. dqsxfer: this block generates the 90-degree phase shifted clock to for the ddr wr ite interface. t he input to this block is the xclk. the user can choose to connect th is either to the edge clock or the fpga clocks. the dqsxfer is routed using the dqsxfer tree to all the i/os spanned by that dqs. data valid module: the data valid module generates a datavalid signal. this signal indicates to the fpga that valid data is transmitted out of the input ddr registers to the fpga core. table 12-3 provides a description of the i/o ports associated with the dqsbufc primitive. table 12-3. dqsbufc ports read pulse generation the read signal to the dqsbufc block is internally gene rated in the fpga core. the read signal goes high when the read command to control the ddr-sdram is in itially asserted. this precedes the dqs preamble by one cycle, yet may overlap the trailing bits of a prior r ead cycle. the dqs detect circuitry of the latticeecp2/m device requires the falling edge of the read signal to be placed withi n the preamble stage. the preamble state of the dqs can be detected using the cas latency and the round trip delay for the signals between the fpga and the memory device. note that the internal fpga core generates the read pulse. the rise of the read pulse should coincide with the initial read command of the read burst and need to go low before the preamble goes high. figure 12-9 shows a read pulse timing example with respect to the prmbdet signal. port name i/o description dqsi i dqs strobe signal from memory clk i system clk read i read generated from the fpga core dqsdel i dqs delay from the dqsdll primitive xclk i edge clock or system clk dqso o delayed dqs strobe signal, to the input capture register block dqsc o dqs strobe signal before delay, going to the fpga core logic ddrclkpol o ddr clock polarity signal prmbdet o preamble detect signal, going to the fpga core logic dqsxfer o 90 degree shifted clock going to the output ddr register block datavalid o signal indicating transmission of valid data to the fpga core 12-8 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-9. read pulse generation iddrmx1a this primitive will implement the input register block in memory mode. the ddr registers are designed to use edge clock routing on the i/o side and the primary clock on the fpga side. the eclk input is used to connect to the dqs strobe coming from the dqs delay block (dqsbufc primitive). the sclk input is connected to the system (fpga) clock. ddrclkpol is an input fr om the dqs clock polarity tree. this signal is generated by the dqs transition detect circuit in the hardwa re. the ddrclkpol signal is used to choose the polarity of the sclk to the synchronization registers. figure 12-10. iddrmx1a symbol table 12-4 provides a description of all i/o ports associated with the iddrmx1a primitive. read dqs prmbdet first dqs transition preamble prior read cycle postamble postamble ok read fail read fail vth read ok iddrmx1a eclk rst qa qb d sclk ce ddrclkpol 12-9 latticeecp2/m lattice semiconductor hi gh-speed i/o interface table 12-4. iddrmx1a ports figure 12-11 shows the input register block configured in the iddrmx1a mode. figure 12-11. input register block in iddrmx1a mode figure 12-12 shows the iddrmx1a timing waveform. port name i/o definition d i ddr data eclk i the phase shifted dqs should be connected to this input rst i reset sclk i system clk ce i clock enable ddrclkpol i ddr clock polarity signal qa o data at positive edge of the clk qb o data at the negative edge of the clk note: the ddrclkpol input to iddrmx1a should be connected to the ddrclkpol output of dqsbufc. data iddrmx1a qb qa ddr registers synchronization registers b c e d a eclk sclk ddrclkpol 12-10 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-12. iddrmx1a waveform iddrmfx1a with the iddrmx1a, the data can enter the fpga at either the positive or negative edge of the sclk depending on the state of the ddrclkpol signal. the iddrmfx1a modul e includes an additional clock transfer stage that ensures that the data is transferred at a known edge of the system clock. figure 12-13. iddrmfx1a symbol table 12-5 provides a description of all i/o ports associated with the iddrmfx1a primitive. dqs at i/o ddr data at i/o eclk( dqs shifted 90 deg) p0 n0 p1 n1 n2 p2 p3 n3 p4 p0 n0 p1 n1 p2 n2 p3 n3 p4 n0 n1 n2 n3 p0 p1 p2 p3 xx xx ddr data at iddrmx1a a b qa p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 xx n4 n4 c p0 p1 p2 p3 xx qa sclk sclk case 1: ddrclkpol = 0 case 2: ddrclkpol = 1 qb n0 n1 n2 n3 xx n0 n1 n2 n3 xx qb iddrmfx1a eclk rst qa qb d clk1 ce ddrclkpol clk2 12-11 latticeecp2/m lattice semiconductor hi gh-speed i/o interface table 12-5. iddrmfx1a ports figure 12-14 shows the latticeecp2 input register bl ock configured to function in the iddrxmfx1a mode. the ddr registers are designed to use edge clock routing on the i/o side and the primary clock on the fpga side. the eclk input is used to connect to the dqs strobe coming from the dqs delay block (dqsbufc primitive). the clk1 and clk2 inputs should be connected to the slow system (fpga) clock. ddrclkpol is an input from the dqs clock polarity tree. this signal is generated by the dqs transition detect circuit in the hardware. the addi- tional clock transfer registers are shared with the output register block. figure 12-14. input register block in iddrmfx1a mode figure 12-15 shows the iddrmfx1a timing waveform. port name i/o description d i ddr data eclk i the phase shifted dqs should be connected to this input rst i reset clk1 i slow fpga clk clk2 i slow fpga clk ce i clock enable ddrclkpol i ddr clock polarity signal qa o data at the positive edge of the clk qb o data at the negative edge of the clk note: the ddrclkpol input to iddrmfx1a should be connected to the ddrclkpol output of dqsbufc. data iddrmfx1a qb qa ddr registers synchronization registers clock transfer registers b c e d h i a eclk clk2 clk1 ddrclkpol 12-12 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-15. iddrmfx1a waveform oddrmxa the oddrmxa primitive implements the out put register for both th e write and the tristate functions. this primitive is used to output ddr data and the dqs strobe to the memory. all the ddr output tristate functions are also imple- mented using this primitive. figure 12-16 shows the oddrmxa primitive symbol and its i/o ports. figure 12-16. oddrmxa symbol table 12-6 provides a description of all i/o ports associated with the oddrmxa primitive. dqs at i/o ddr data at i/o eclk( dqs shifted 90 deg) p0 n0 p1 n1 n2 p2 p3 n3 p4 p0 n0 p1 n1 p2 n2 p3 n3 p4 n0 n1 n2 n3 p0/n0 p1/n1 p2/n2 p3/n3 xx xx ddr data at iddrmfx1a a b d/e p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 xx n4 n4 c clk2 p0 p1 p2 p3 xx n0 n1 n2 n3 xx qa qb p0/n0 p1/n1 p2/n2 p3/n3 xx d/e clk1 clk1 case 1: ddrclkpol = 0 case 2: ddrclkpol = 1 oddrmxa clk da db q rst dqsxfer 12-13 latticeecp2/m lattice semiconductor hi gh-speed i/o interface table 12-6. oddrmxa ports figure 12-17 shows the latticeecp2 output register block configured in the oddrxma mode. figure 12-17. output register block in oddrxma mode figure 12-18 shows the oddrmxa timing waveform. port name i/o description clk i system clk or eclk da i data at the negative edge of the clock db i data at the positive edge of the clock rst i reset dqsxfer i 90-degree phase shifted cloc k coming from the dqsbufc block q i ddr data to the memory notes: 1. rst should be held low during ddr write operation. 2. ddr output and tristate registers do not have ce suppor t. rst is available for the tristate ddrx mode (while read- ing). the lsr will default to set when used in the tristate mode. 3. when asserting reset during ddr writes, it is important to keep in mind that this only resets the flip-flops and not the latches. q da db oddrxma eclk a0 b0 c0 dqsxfer 12-14 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-18. oddrmxa waveform note that the dqsxfer is inverted inside the oddrxma. this will ca use the data coming out of the oddrxma to be -90 in phase with the output of the oddrxc module. memory read implementation latticeecp2/m devices contain a variety of features to simplify implementation of the read portion of a ddr inter- face: ? dll compensated dqs delay elements ? ddr input registers ? automatic dqs to system clock domain transfer circuitry ? data valid module dll compensated dqs delay elements the dqs from the memory is connected to the dqs delay element. the dqs delay block receives a 6-bit delay control from the on-chip dqsdll. this 6-bit delay is mode led as a single bit in the software. the latticeecp2/m devices support two dqsdll, one on the left and one on the right side of the device. the dqsdel generated by the dqsdll on the left side is routed to all the dqs blocks on the left and bottom half of the device. the delay gen- erated by the dqsdll on the right side is distributed to all the dqs delay blocks on the right side and the other bottom half of the device. there are no dqs pins on the to p banks of the device. these digital delay control signals are used to delay the dqs from the memory by 90 degrees. the dqs received from the memory is delayed in each of the dqs delay blocks and this delay dqs is used to clock the first set stage ddr input registers. dqs transition detect or automatic clock polarity select in a typical ddr memory interface design, the phase relation between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. prior to the read operation in ddr memories, dqs is in tristate (pulled by termination). co ming out of tristate, the ddr memory de vice drives dqs low in the preamble state. the dqs transition detect block detects the first dqs rising edge after a preamble transition and generates a signal indicating the required polarity for the fpga system clock (ddrclkpol). this signal is used to control the polarity of the clock to the synchronizing registers. eclk reg a0 reg b0 p0 p1 p2 p3 p4 latch c0 p0 p1 p2 p3 p4 n0 n1 n2 n3 xx n4 n0 n1 n2 n3 xx n4 .. .. n0 n1 n2 q n3 xx xx xx da db p0 n0 p1 n1 p2 n2 p3 xx n3 p4 dqsxfer 12-15 latticeecp2/m lattice semiconductor hi gh-speed i/o interface data valid module the data valid module generates a datavalid signal. this signal indicates to the fpga that valid data is transmit- ted out the input ddr registers to the fpga core. ddr i/o register implementation the first set of ddr registers is used to de-mux the ddr data at the positive and negative edge of the phase shifted dqs signal. the register that captures the positive-edge data is followed by a negative-edge triggered reg- ister. this register transfers the positive edge data from the first register to the negative edge of dqs so that both the positive and negative portions of the data are now aligned to the negative edge of dqs. the second stage of registers is clocked by the fpga clock, the polarity of this clock is selected by the ddr clock polarity signal generated by the dqs transition detect block. the i/o logic registers can be implemented in two modes: ? half clock transfer mode ? full clock transfer mode in half clock transfer mode the data is transferred to the fpga core after the second stage of the register. in full clock transfer mode, an additional stage of i/o registers clocked by the fpga clock is used to transfer the data to the fpga core. the latticeecp2/m family data sheet explains each of these circuit elements in more detail. memory read implement ation in software three primitives in the isplever ? design tools represent the capability of these three elements. the dqsdll rep- resents the dll used for calibration. the iddrmx1a/iddrmfx1a primitive represents the ddr input registers and clock domain transfer registers with or without full clock transfer. finally, the dqsbufc represents the dqs delay block, the clock polarity control logic and the data valid module. figures 12-19 and 12-20 show the read interface block generated using the ipex press? tool in the isplever software. figure 12-19. software primitive implementation for memory read (half clock transfer) ddrclkpol dqs lock dqsdll dqsi clk read dqsdel dq dqso sclk eclk ddrclkpol d rst ce qa qb rst uddcntl dqsdel datain_p datain_n dqsc prmbdet lock dqsbufc iddrmx1a dqsc prmbdet xclk dqsxfer datavalid dqsxfer datavalid reset clk uddcntl read ce xclk 12-16 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-20. software primitive implementation for memory read (full clock transfer) read timing waveforms figures 12-21 and 12-22 show read data transfer for half and full clock cycle data transfer based on the results of the dqs transition detector logic. this circuitry decides whether or not to invert the phase of fpga system clk to the synchronization registers based on the relative phases of prmbdet and clk. ? case 1: if the fpga clock is low on the first prmbdet tran sition, then ddrclkpol is low and no inversion is required. ? case 2: if the fpga clock is high on the first prmbdet, then ddrclkpol is high and the fpga clock (clk) needs to be inverted before it is used for synchronization. figure 12-21 illustrate s the ddr data timing using half clock transfer mode at different stages of the iddrmx1a registers. the first stage of the register captures data on the positive edge as shown by signal a and the negative edge as shown by signal b. data stream a goes through an additional half clock cycle transfer shown by signal c. phase-aligned data streams b and c are presented to the next stage registers clocked by the fpga clock. figure 12-22 illustrates the ddr data ti ming using full clock transfer mode at different stages of iddrmfx1a regis- ters. in addition to the first two register stages in the half clock mode, the full clock transfer mode has an additional stage register clocked by the fpga clock. in this case, d and e are the data streams after the second register stage presented to the final stage of registers clocked by the fpga clock. ddrclkpol dqs lock dqsdll dqsi clk read dqsdel dq dqso clk2 eclk ddrclkpol d rst ce qa qb rst uddcntl dqsdel datain_p datain_n dqsc prmbdet lock dqsbufc iddrmfx1a dqsc prmbdet xclk dqsxfer datavalid dqsxfer datavalid clk1 reset clk uddcntl read ce xclk 12-17 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-21. read data transfer when using iddrmx1a notes: 1. ddr memory sends dq aligned to dqs strobe. 2. the dqs strobe is delayed by 90 deg rees using the dedicated dqs logic. 3. dq is now center al igned to dqs strobe. 4. prmbdet is the preamble detect signal generated using the dqsb ufb primitive. this is used to generate the ddrclkpol signal. 5. the first set of i/o registers, a and b, c apture data on the positive and negative edges of dqs. 6. i/o register c transfers data so that both data are now aligned to negative edge of dqs. 7. ddclkpol signal generated will determine if the fpga clk going into the synchronization registers need to be inverted. the dd rclk- pol=0 when the fpga clk is low at the first rising edge of prmbde t. the clock to the synchronization registers is not inverted. the ddrclkpol=1 when the fpga clk is high at the first rising edge of prmbdet. in this case the clock to the synchronization regist er is inverted. 8. the i/o synchronization registers capture data on either the rising or falling edge of the fpga clock. 9. the datavalid signal goes high when valid data enters the fpga core. once data valid is asserted, it stays high until the nex t read pulse. ddrclkpol= 0 dqs at pin dq at pin dqs at iol fpga clk prmbdet clk to sync io registers a b c p0 n0 n1 p1 p0 n0 p1 n1 p0 p1 n0 n1 p0 p1 p0 n0 qa qb dq at iol fpga clk ddrclkpol=1 p0 n0 clk to sync io registers qa qb datavalid 12-18 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-22. read data tr ansfer when using iddrmfx1a p0 n0 n1 p1 p0 n0 p1 n1 p0 p0 n0 n1 p1 p0 p2 n0 n1 n2 p1 p0 n0 n1 p1 p0 p2 n0 n1 n2 n0 n1 n2 p1 p0 p2 p1 p0 p2 p2 n2 p2 n2 p2 n2 dqs at pin dq at pin prmbdet dqs at iol dq at iol a b c d e qa qb fpga clock (case 2) ddrclkpol = 1 clk to sync i/o registers d e qa qb datavalid notes: 1. ddr memory sends dq aligned to dqs strobe. 2. the dqs strobe is delayed by 90 degress, using the dedicated dqs logic. 3. dq is now center-aligned to the dqs strobe. 4. prmbdet is the preamble detect signal generated usin the dqsbufb primitive. this is used to generate the ddrclkpol signal. 5. the first set of i/o registers, a and b, capture data on the positive and negative edges of dqs. 6. i/o register c transfers data such that both data are aligned to the negative edge of dqs. 7. the ddclkpol signal generated will determine whether the fpga clock going into the synchronization registers needs to be inverted. the ddrclkpol = 0 when the fpga clock is low at the first rising edge of prmbdet. so, the clock to the synchronization registers is not inverted. the ddrclkpol = 1 when the fpga clock is high at the first rising edge of prmbdet. in this case, the clock to the synchronization register is inverted. 8. registers d and e capture data at the fpga clock. 9. the data again registers at the fpga clock to ensure a full clock cycle transfer. 10. the datavalid signal goes high when valid data enters the fpga core. once datavalid is asserted, it stays high until the next read pulse. fpga clock (case 1) ddrclkpol = 0 clk to sync i/o registers 12-19 latticeecp2/m lattice semiconductor hi gh-speed i/o interface data read critical path when using iddrxm1a, the data in the second stage ddr registers can be regi stered either on the positive edge or on the falling edge of the fpga cloc k depending on the ddrclkpol signal. in order to ensure that the data transferred to the fpga core registers is aligned to the rising edge of the system clock, this path should be con- strained with a half clock transfer. this half clock transfer can be forced in the software by assigning a multi-cycle constraint (multi-cycle of 0.5 x) on all the data paths to first pfu regist er. when using iddrxmfx1a, there is an additional stage of registers inside the i/o block that transfers data to the positive edge of the fpga clock. hence no constraint is required for this case. dqs postamble at the end of a read cycle, the ddr sdram device executes the read cycle postamble and then immediately tristates both the dq and dqs output drivers. since neither the memory controller (fpga) nor the ddr sdram device are driving dq or dqs at that time, these signals float to a level determined by the off-chip termination resistors. while these signals are floating, noise on the dqs strobe may be interpreted as a valid strobe signal by the fpga input buffer. this can cause the last read data captured in the iol input ddr registers to be overwrit- ten before the data has been transferred to the free running resynchronization registers inside the fpga. figure 12-23. postamble effect on read latticeecp2/m devices have extra dedicated logic in the in the dqs delay block that prevents this postamble prob- lem. the dqs postamble logic is automatically implemented when the user instantiates the dqs delay logic (dqsbufc software primitive) in the design. memory write implementation to implement the write portion of a d dr memory interface, two streams of si ngle data rate data must be multi- plexed together with data transitioning on both edges of the clock. in addition, during a write cycle, dqs must arrive at the memory pins center-aligned with the data, dq. along with the dqs strobe and data this portion of the inter- face must also provide the clkp, clkn address/command and data mask (dm) signals to the memory. it is the responsibility of the fpga ou tput control to edge-alig n the ddr output signals (addr,cmd, dqs, but not dq, dm) to the rising edge of the outgoing differential clock (clkp/clkn). challenges encountered by the during memory write: 1. dqs needs to be center-aligned with the outgoing ddr data, dq. p0 p1 n0 p0 dq at iol dqs at pin dq at pin dqs at iol p0 n0 n1 p1 n1 p0 n0 n1 p1 p1 clk at synce reg datain_p datain_n a b c p0 n0 12-20 latticeecp2/m lattice semiconductor hi gh-speed i/o interface 2. differential clk signals (clkp and clkn) need to be generated. 3. the controller must meet the ddr interface specification for t dss and t dsh parameters, defined as dqs falling to clkp rising setup and hold times. 4. the ddr output data must be muxed from two sdr streams into a single outgoing ddr data stream. all ddr output signals (?addr, cmd?, dq s, dq, dm) are initially aligned to the rising edge of the fpga clock inside the fpga core. the relative phase of the signals may be adjusted in the iol logic before departing the fpga. these adjustments are shown in figure 12-24. latticeecp2/m devices contain ddr output and tri-state registers along with the dqsxfer signal generated by the dqsbufc that allows easy implem entation of the write portion of t he ddr memory interfaces. the ddr out- put registers can be accessed in the design tools via the o ddrmxa and the oddrxc primitives. the dqs signal and the ddr cl ock outputs are generated us ing the oddrxc primitive. as shown in the figure, the clkp and dqs signals are generated so that they are 180 degrees in phase with the clock. this is done by con- necting ?1? to the da input and ?0? to the db inputs of the oddrxc primitive. refe r to the ddr generic software primitive section of this document to see the oddrxc timing waveforms. the ddr clock output is then fed into a sstl differential output buffer to generate clkp and clkn differential clocks. generating the clkn in this manner prevents any skew between the two signals. when interfacing to ddr1, sdram memory clkp should be connected to the sstl25d i/o standard. when interfacing to ddr2 memory, it should be connected to the sstl18d i/o standard. the dqsxfer output from the dqsbufc block is the 90-degree phase shifted clock. this 90-degree phase shifted clock is used as an input to the oddrmxa block. the oddrmxa is used to generate the dq and dm data outputs going to the memory. in the oddrmxa module, the data is first registered using the eclk or fpga clock input and then shifted out using the dqsxfer signal. to ensure that the data going to the memory is center- aligned to the dqs, the dqsxfer is in verted inside the oddrxma primitive. this will generate data that is cen- ter-aligned to the dqs. refer to the software primitives section of this document for the oddrxma timing wave- forms. the ddr interface specification for t dss and t dsh parameters defined as dqs fa lling to clkp rising setup and hold times must be met. this is accomplished by ensuring that the clkp and dqs signals are identical in phase. the tristate control for the dqs and dq outputs can also be implemented using the oddrxc primitive. figure 12-24 shows the ddr write impl ementation using the ddr primitives. 12-21 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-24. software implementation for memory write clk q q q q q q ?1? ?0? ?1? ?0? dqstri_p clkp (clk+180) oddrxc oddrxc oddrxc oddrmxa oddrmxa oddrmxa dqsxfer (clk+90) eclk / fpga clock dqs (clk+180) dq (clk+270) dm (clk+270) clkn (clk) dqstri_n datatri_p datatri_n dataout_p dataout_n dmout_p dmout_n da db rst clk da db rst clk da db rst clk da db rst dqsxfer clk da db rst dqsxfer clk da db rst dqsxfer 12-22 latticeecp2/m lattice semiconductor hi gh-speed i/o interface write timing waveforms figure 12-25 shows the ddr write side data transfer timing for the dq data pad and the dqs strobe pad. when writing to the ddr memory device, the dm (data mask) and the addr/ cmd (address and command) signals are also sent to the memory device along with the data and strobe signals. figure 12-25. ddr write da ta transfer for dq data design rules/guidelines listed below are some rules and guidelines to keep in mind when implementing ddr memory interfaces in the latticeecp2/m devices. ? the latticeecp2/m devices have dedicated dq-dqs banks. please refer to the logical signal connections of the groups in the latticeecp2/m family data sheet before locking these pins. ? there are two dqsdll on the device, one for the left half and one for the right half of the device. therefore, only one dqsdll primitive should be instantiated for each half of the device. since there is only one dqsdll on each half of the device, all the ddr memory interfaces on that half of the device should run at the same fre- quency. each of the dqsdll will generate 90-degree digital delay bits for all the dqs delay blocks on that half of the device based on the reference clock input to the dll. ? when implementing a ddr sdram interface, all interfac e signals should be connec ted to the sstl25 i/o stan- dard. in the case of the ddr2 sdram interface, the interface signal should be connected to sstl18 i/o stan- dard. ? for ddr2, the differential dqs signals need to be connected to sstl18 the dif ferential i/o standard. ? when implementing the ddr interface, the vref1 of the bank is used to provide the reference voltage for the interface pins. generic high speed ddr implementation in addition to the ddr memory interface, the i/o logic ddr registers can be used to implement high speed ddr interfaces. the input ddr registers can operate in full clock transfer and half clock transfer modes. the ddr input and output register also su pport x1 and x2 gearing rati os. a gearing capability is prov ided to mux/demux the i/o data rate (eclk) to the fpga clock rate (sclk). for ddr interfaces, this ratio is slightly different than the sdr ratio. a basic 2x ddr element provides four fpga side bits for two i/o side bits at half the clock rate on the fpga side. p0 n0 p1 n1 p2 n2 p3 xx n3 p4 eclk p0 p1 p2 p3 p4 n0 n1 n2 n3 n4 .. .. da db dqs clkp clkn dqsxfer dq .. 12-23 latticeecp2/m lattice semiconductor hi gh-speed i/o interface the data going to the ddr registers can be optionally delayed before going to the ddr register block. generic ddr software primitives the ipexpress tool in the isplever so ftware can be used to generate the ddr modules. the various ddr modes described below can be configured in the ipexpress tool. the various modes are implemented using the following software primitives. ? iddrxc ? ddr generic input ? iddrfxa ? ddr generic input with full clock transfer (x1 gearbox) ? iddrx2b ? ddr generic input with 2x gearing ratio. ddrx2 inputs a double data rate signal as four data streams. two stages of ddr registers are used to conv ert serial ddr data at in put pad into four sdr data streams entering fpga core logic. ? oddrxc ? ddr generic output ? oddrx2b ? ddr generic output with 2x gearing ratio. the ddrx2 inputs four separate data streams and out- puts a single data stream to the i/o buffer. ? delayb ? the ddr input can be optionally delayed before it is input to the ddr registers. the user can choose to implement a fixed delay value or use a dynamic delay. iddrxc this primitive inputs ddr data at both edges of the clk and generates two streams of data. the clk to this mod- ule can be connected to either the edge clock or the primary fpga clock. figure 12-26 shows the primit ive symbol for iddrxc mode. figure 12-26. iddrxc symbol table 12-7 lists the port names and descriptions for the iddrxc primitive. table 12-7. iddrxc port names figure 12-27 shows the latticeecp2 input register block configured in the iddrxfc mode. port name i/o definition d i ddr data clk i this clock can be connected to the eclk or the fpga clock ce i clock enable signal rst i reset to the ddr register qa o data at the positive edge of the clock qb o data at the negative edge of the clock d clk ce rst qb qa iddrxc 12-24 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-27. input register block configured as iddrxc figure 12-28 shows the timing waveform when using the iddrxc module. figure 12-28. iddrxc waveform iddrfxa this primitive inputs ddr data at both edges of clock clk1 and generates two streams of data aligned to clock clk2. clk1 can be connected either to the edge clock or the internal fpga clock. if the edge clock input is used for clk1 then clk2 should be generated from the same clock going to clk1. data iddrxc fpga clock edge clock qb qa ddr registers synchronization registers b c e d a clk clk at i/o ddr data at i/o clk at iddrxc p0 n0 p1 n1 n2 p2 p3 n3 p4 p0 n0 p1 n1 p2 n2 p3 n3 p4 n0 n1 n2 n3 p0 p1 p2 p3 xx xx ddr data at iddrxc a b qa p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 xx n4 n4 c n0 n1 n2 n3 xx qb 12-25 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-29 shows the primit ive symbol for the iddrfxa mode. figure 12-29. iddrfxa symbol table 12-8 lists the port names and descriptions for the iddrfxa primitive. table 12-8. iddrfxa port names figure 12-31 shows the latticeecp2 input register block configured in the iddrxfxa mode. clk1 used to regis- ter the ddr registers and the first set of synchronization r egisters. clk2 is used by the third stage of registers and should be clocked by the fpga clock. these clock transfer registers are shared with the output register block. figure 12-30. input register block configured as iddrfxa port name i/o description d i ddr data clk1 i this clock can be connected to the eclk or the fpga clock clk2 i this clock should be connected to the fpga clock ce i clock enable signal rst i reset to the ddr register qa o data at the positive edge of the clock qb o data at the negative edge of the clock d clk1 clk2 ce rst qb qa iddrfxa data iddrfxa fpga clock edge clock qb qa ddr registers synchronization registers clock transfer registers b c e d h i a clk1 clk2 12-26 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-31 shows the timing waveform when using the iddrfxa module. figure 12-31. iddrfxa waveform clk at i/o ddr data at i/o clk1 (shifted 90 deg) p0 n0 p1 n1 n2 p2 p3 n3 p4 p0 n0 p1 n1 p2 n2 p3 n3 p4 n0 n1 n2 n3 p0/n0 p1/n1 p2/n2 p3/n3 xx xx ddr data at iddrfxa a b d/e p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 xx n4 n4 c clk2 p0 p1 p2 p3 xx n0 n1 n2 n3 xx qa qb 12-27 latticeecp2/m lattice semiconductor hi gh-speed i/o interface iddrx2b this module is used when a gearing function is required. this primitive inputs the ddr data at both edges of the edge clock and generates four streams of data aligned to sclk. sclk is always half the frequency of eclk. it is recommended that the clkdiv module or pll be used to generate the sclk from the eclk. figure 12-32 shows the primitiv e symbol for the iddrx2b mode. figure 12-32. iddrx2b symbol table 12-9 lists the port names and descriptions for the iddrx2b primitive. table 12-9. iddrx2b port names figure 12-33 shows the latticeecp2 input register block c onfigured in the iddrx2b mode. the ddr registers and the first set of synchronization registers are clocked by the eclk input. the sclk is used to clock the third stage of register. this primitive will out put four streams of data. the 2x geari ng function is implemented by using the synchronization registers of the complementary pio. the clock transfer registers are shared with the output register block. port name i/o description d i ddr data eclk i this clock can be connected to the fast edge clock sclk i this clock should be connected to the fpga clock ce i clock enable signal rst i reset to the ddr register qa0, qa1 o data at the positive edge of the clock qb0, qb1 o data at the neg ative edge of the clock d eclk sclk ce rst qa0 qa1 qb0 qb1 iddrx2b 12-28 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-33. input register block configured as iddrx2b figure 12-34 shows the timing waveform using the iddrx2b module. data iddrx2b sclk eclk true pio in lvds sysi/o pair comp pio in lvds sysi/o pair qb1 qa1 qb0 qa0 ddr registers synchronization registers clock transfer registers synchronization registers clock transfer registers b c e d g f h i a j k 12-29 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-34. iddrx2b waveform oddrxc this is the ddr output module. this primitive will input two data streams and mux them together to generate a sin- gle stream of data going to the sysio? buffer. the clk to this module can be connected to the edge clock or to the fpga clock. this primitive is also used for when ddr function is required for the tristate signal. figure 12-35 shows the primitive symbol for the oddrxc mode. figure 12-35. oddrxc symbol table 12-10 lists the port names and descriptions for the oddrxc primitive. clk at i/o ddr data at i/o eclk (shifted 90 deg) p0 n0 p1 n1 n2 p2 p3 n3 p4 p0 n0 p1 n1 p2 n2 p3 n3 p4 n0 n1 n2 n3 p0/n0 p1/n1 p2/n2 p3/n3 p0/n0 p1/n1 p2/n2 n1 p1 n0 p0 n3 p3 n2 p2 xx xx xx xx xx xx ddr data at iddrx2b a b d/e f/g xx p0 p1 p2 p3 p4 p0 p1 p2 p3 p4 xx n4 n4 c sclk qb1 qa1 qb0 qa0 clk da db rst q oddrxc 12-30 latticeecp2/m lattice semiconductor hi gh-speed i/o interface table 12-10. oddrxc port names figure 12-36 shows the output register block of the latticeecp2 device configured in oddrxc mode. figure 12-36. output re gister block in oddrc mode figure 12-37 shows the timing wave form when using the oddrxc module. figure 12-37. oddrxc waveform oddrx2b this ddr output module can be used when a gearbox function is required. this primitive inputs four data streams and muxes them together to generate a single stream of data going to the sysio buffer. port name i/o definition da i data at the negative edge of the clock db i data at the positive edge of the clock clk i this clock can be connected to the edge clock or to the fpga clock rst i reset signal q o ddr data output q da db oddrxc eclk a0 b0 c0 eclk reg a0 reg b0 p0 p1 p2 p3 p4 latch c0 p0 p1 p2 p3 p4 n0 n1 n2 n3 xx n4 n0 n1 n2 n3 xx n4 .. .. n0 n1 n2 q n3 xx xx xx da db p0 n0 p1 n1 p2 n2 p3 xx n3 p4 12-31 latticeecp2/m lattice semiconductor hi gh-speed i/o interface ddr registers of the complementary pio are used in this mode. the complementary pio register can no longer be used to perform the ddr function. there are two clocks going to this primitive. the eclk is connected to the faster edge clock and the sclk is connected to the slower fpga clock. the ddr data output of this primitive is aligned to the faster edge clock. figure 12-38 shows the primitive symbol for the oddrx2b mode. figure 12-38. oddrx2b symbol table 12-11 lists the port names and descriptions for the oddrx2b primitive. table 12-11. oddrx2b port names figure 12-39 shows the latticeecp2 output register block in the oddrx2b mode. port name i/o description da0, db0 i data at the negative edge of the clock da1, db1 i data at the positive edge of the clock eclk i this clock should be connected to the faster edge clock sclk i this clock should be connected to the slower fpga clock rst i reset signal q o ddr data output eclk sclk da0 da1 db0 db1 rst q oddrx2b 12-32 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-39. output register block configured in oddrx2b mode figure 12-40 shows the timing wave form when using the oddrxc module. q db0 db1 true pio in lvds sysi/o pair comp pio in lvds sysi/o pair da0 da1 oddrx2b sclk eclk a0 b0 c0 a1 b1 c1 d0 e0 f0 12-33 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-40. oddrx2b waveform delayb data going to the ddr registers can be optionally delayed using the delay block. the delay block receives 4-bit delay control. the 4-bit delay can be set using fixed multiplier values or it can be controlled by the user. the delayb block is available for us e with the input ddr registers. the delayb block can be configured when generating the ddr input modules in the ipexpress tool of the soft- ware. the delay can be adjusted in 35ps steps. users can choose from three types of delay values: 1. dynamic ? the delay value is controlled by the user logic using the del[3:0] input of the delayb block. sclk reg a0 reg b0 d1 d5 d9 d13 d17 latch c0 d1 d5 d9 d13 d17 d3 d7 d11 d15 xx d19 d3 d7 d11 d15 xx d19 .. .. d3 d7 d11 a ( mux0) d15 xx xx xx db0 db1 sclk reg a1 reg b1 d0 d4 d8 d12 d16 latch c1 d0 d4 d8 d12 d16 d2 d6 d10 d14 xx d18 d2 d6 d10 d14 xx d18 .. .. d2 d6 d10 b ( mux1) d14 d0 d2 d4 d6 d8 d10 d12 d14 xx xx xx xx da0 da1 d16 d1 d3 d5 d7 d9 d11 d13 xx d15 d17 d1 d3 d5 d7 d9 d11 d13 xx d15 d17 copy of a ( mux0) d0 d2 d4 d6 d8 d10 d12 d14 xx d1 d3 d5 d7 d9 d11 d13 xx d15 d1 d3 d5 d7 d9 d11 d13 d15 q d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 xx xx latch f0 reg e0 reg d0 eclk 12-34 latticeecp2/m lattice semiconductor hi gh-speed i/o interface 2. fixed ? when choosing the fixed value, the user will also need to choose from one of the 16 multiplier val- ues. this will tie the inputs del[3:0] of the delayb bl ock to a fixed value dependi ng on the multiplier value chosen. 3. fixed_xgmii ? the del [3:0] will be configured with t he delay value required when implementing a xgmii interface. figure 12-41 shows the primitive symbol for the delayb mode. figure 12-41. delayb symbol table 12-12 lists the port names and descriptions for the delayb primitive. table 12-12. delayb port names design rules/guidelines listed below are some rules and guidelines for implem enting generic ddr interfaces in latticeecp2/m devices. ? when implementing a 2x gearing mode, the complement pio registers are used. this complementary pio regis- ter can no longer be used and should not be connected. ? ddr registers are available on the left, right and bottom sides of the device. the top side does not support ddr registers. ddr usage in isplever ipexpress this section describes how ipexpress in isplever is used to generate the ddr modules. if you are using lattice diamond? design software, refer to appendix a to see how ddr modules are generated in diamond. ipexpress can be used to configure an d generate the ddr memory interface and generic ddr mo dule. the tool will gener- ate an hdl module that will contain the ddr primitiv es. this module can be using in the top level design. figure 12-42 shows the main window of ipexpress. the ddr_generic and ddr_mem options under architech- ture->io are used to configure the ddr modules. port name i/o definition a i ddr input from the sysio buffer del (0:3) i delay inputs z o delay ddr data a del(0:3) z delayb 12-35 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-42. ipexpress main window ddr generic figure 12-43 shows the main window w hen ddr_generic is selected. the only entry required in th is window is the module name. other entries are set to the project settings. the user may change these entries if desired. after entering the module name, click on customize to open the configuration tab window as shown in figure 12-44. figure 12-43. ipexpress main window for ddr_generic 12-36 latticeecp2/m lattice semiconductor hi gh-speed i/o interface configuration tab the configuration tab lists all user-accessible attribut es with default values set. upon completion, click generate to generate source and constraint files. the user may choose to use the .lpc file to load parameters. figure 12-44. configuration tab for ddr_generic the user can change the mode parameter to choose either input, output, bidirection or tristate ddr module. the other configuration parameters will change according to the mode selected. th e delay parameter is only available for input and bidirectional modes. sim ilarly the multiplier for fixed delay pa rameter is only available when the delay parameter is configured to fixed. table 12-13. user parameters in the ipexpress gui ddr_mem figure 12-45 shows the main window w hen ddr_mem is selected. similar to the ddr_generic, the only entry required here is the module name. other entries are set to the project settings. the user may change these entries user parameters description values/range default mode mode selection for the ddr block. input, output, bidirectional, tristate input data width width of the data bus. 1-64 8 gearing ratio gearing ratio selection. 1x, 2x 1 1x delay input delay configuration. dynamic, fixed, fixed xgmii dynamic multiplier for fixed delay fixed delay setting. available only when delay is configured as fixed. 0-15 0 use single clk for 1x allows the selection of a single clock for the gear- ing logic. on/off off 1. only 1x available when mode is bidirection or tristate. 12-37 latticeecp2/m lattice semiconductor hi gh-speed i/o interface if desired. after entering the module name, click on customize to open the configuration tab window as shown in figure 12-46. figure 12-45. ipexpress main window for ddr_mem configuration tab the configuration tab lists all user-accessible attribut es with default values set. upon completion, click generate to generate source and constraint files. the user may choose to use the .lpc file to load parameters. 12-38 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-46. configuration tab for ddr_mem the user can change the mode parameter to choose either the ddr or ddr2 interface. the other configuration parameters will change according to the mode selected. the number of dqs pa rameter determines the number of ddr interfaces. the software will assume there are eight data bits for every dqs. the user can also choose the frequency of operation an d the ddr dll will be configured to this frequency. the user has an option to enable the clock enable and tristate enables for the ddr registers. it is recommend that the lock/jitter be enabled if the ddr interface is running at 150mhz or higher. the parameters available depend on the mode selected. tables 12-14 and 12-15 describe all user parameters in the ipexpress gui and their usage for modes ddr and ddr2. table 12-14. user parameters in the ipexpress gui when in ddr mode user parameters description values/range default i/o buffer configuration i/o standard used for the interface. this will also depend on the mode selected. sstl25_i, sstl25_ii sstl25_i data width width of the data bus 8-64 8 number of dqs number of dqs will determine the number of dqs groups 1, 2, 4, 8 1 frequency of dqs ddr interface frequency. this is also input to the ddr dll. the values will depend on the mode selected. 100mhz, 133mhz, 166mhz, 200mhz 200mhz lock/jitter sensitivity dll sensit ivity to jitter high, low high lsr for ddr input register lsr control reset, set reset create clock enable for ddr input register create clock enable inputs to the block on/off off tri-state enable for ddr output registers creates tri-state contro l for the ddr data output registers. on/off on ddr tristate enable for the dqs output creates tristate control for dqs output on/off on 12-39 latticeecp2/m lattice semiconductor hi gh-speed i/o interface table 12-15. user parameters in the ipexpress gui when in ddr2 mode fcram (?fast cycle random access memory?) interface fcram is a ddr-type dram, which performs data output at both the rising and falling edges of the clock. fcram devices operate at a core voltage of 2.5v with sstl class ii i/o. it has enhanced both the core and peripheral logic of the sdram. in fcram the address and command signals are synchronized with the clock input, and the data pins are synchronized with the dqs signal. data output takes place at both the rising and falling edges of the dqs. dqs is in phase with the clock i nput of the device. the ddr sdram and ddr fcram controller will have differ- ent pinouts. latticeecp2/m devices can implement the fcram interface using dedicated dqs logic, input ddr registers and output ddr registers, as described in the implementing memory interfaces section of this document. generation of address and control signals for fcram are different than in ddr sdram devices. please refer to the fcram data sheets to see detailed specifications. toshiba, inc. and fujitsu, inc. offer fcram devices in 256mb densities. they are available in x8 or x16 configurations. board design guidelines the most common challenge associated with implementing ddr memory interfaces is the board design and lay- out. it is required that users strictly follow the guidelines recommended by memory device vendors. some of the common recommendations include matching trace lengths of interface signals to avoid skew, proper dq-dqs signal grouping, proper termination of the sstl2 or sstl18 i/o standard, proper vref and vtt gener- ation decoupling and proper pcb routing. the following documents include board layout guidelines: ? www.idt.com , idt, pcb design for double data rate memory ? www.motorola.com , an2582, hardware and layout design considerations for ddr interfaces references ? www.jedec.org , jedec standard 79, do uble data rate (ddr) sdram specification ? www.micron.com , ddr sdram data sheets user parameters description values/range default i/o buffer configuration i/o standard used for the interface. this will also depend on the mode selected. sstl18_i, sstl18_ii sstl18_i data width width of the data bus 8-64 8 number of dqs number of dqs will determine the number of dqs groups 1, 2, 4, 8 1 frequency of dqs ddr interface frequency. this is also input to the ddr dll. the values will depend on the mode selected. 166mhz, 200mhz, 266mhz 200mhz lock/jitter sensitivity dll sensit ivity to jitter high, low high lsr for ddr input register lsr control reset, set reset create clock enable for ddr input register create clock enable inputs to the block on/off off tri-state enable for ddr output registers creates tri-state contro l for the ddr data output registers. on/off on ddr tristate enable for the dqs output creates tristate control for dqs output on/off on dqs buffer configuration for ddr2 dqs buffer can be configured as differential on/off off 12-40 latticeecp2/m lattice semiconductor hi gh-speed i/o interface ? www.infinion.com , ddr sdram data sheets ? www.samsung.com , ddr sdram data sheets ? www.toshiba.com , ddr fcram data sheet ? www.fujitsu.com , ddr fcram data sheet ? rd1019, qdr memory controller reference design ?eb23, latticeecp2 advanced evaluation board user?s guide ?ipug35, ddr1 & ddr2 sdram controller (pipelined versions) user?s guide technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com revision history date version change summary february 2006 01.0 original version. september 2006 01.1 some figures updated. added information on delayb block. september 2006 01.2 updated for latticeecp2m. added ?ddr generic usage in ipexpress? section. february 2007 01.3 updated ddr and ddr2 sdram interfaces overview section. june 2007 01.4 updated the port names on the input ddr block diagrams. updated text in the dqs transi tion detect under memory read implementation section. updated the dqsdel from 6-bit bus to single bit in figures 12-19 and 12-20. updated text in the dll compensat ed dqs delay elements section under memory read implementation. october 2007 01.5 updated ddrx2b waveform diagram. june 2009 01.6 updated dqsdll update control text section. january 2010 01.7 updated read data transfer when using iddrmfx1a figure. updated data read critical path text section. june 2010 01.8 added appendix a. 12-41 latticeecp2/m lattice semiconductor hi gh-speed i/o interface appendix a. ddr generation usin g ipexpress with lattice diamond the ipexpress tool in the lattice diamond design software can be used to configure and generate the ddr mem- ory interface and generic ddr module. ipexpress will gene rate an hdl module that will contain the ddr primi- tives. this module can be us ing in the top level design. figure 12-47 shows the main window of ipexpress. the ddr_generic and ddr_mem options under architech- ture > io are used to conf igure the ddr modules. figure 12-47. ipexpress main window ddr generic figure 12-48 shows the main window w hen ddr_generic is selected. the only entry required in th is window is the module name. other entries are set to the project settings. the user may change these entries if desired. after entering the module name, click on customize to open the configuration tab window as shown in figure 12-49. figure 12-48. ipexpress main window for ddr_generic 12-42 latticeecp2/m lattice semiconductor hi gh-speed i/o interface configuration tab the configuration tab lists all user-accessible attribut es with default values set. upon completion, click generate to generate source and constraint files. the user may choose to use the .lpc file to load parameters. figure 12-49. configuration tab for ddr_generic the user can change the mode parameter to choose either the input, output, bi-directional or tristate ddr mod- ules. the other configuration parameters will change according to the mode selected. the de lay parameter is only available for input and bi-directional modes. similarly, the multiplier for fixed delay parameter is only available when the delay parameter is configured as fixed. table 12-16. user parameters in the ipexpress gui ddr_mem figure 12-50 shows the main window when ddr_mem is selected. similar to ddr _generic, the only entry required here is the module name. other entries are set to the project settings. the user may change these entries if desired. after entering the module name, click on customize to open the configuration tab window as shown in figure 12-51. user parameters description values/range default mode mode selection for the ddr block. input, output, bidirectional, tristate input data width width of the data bus. 1-64 8 gearing ratio gearing ratio selection. 1x, 2x 1 1x delay input delay configuration. dynamic, fixed, fixed xgmii dynamic multiplier for fixed delay fixed delay setting. available only when delay is configured as fixed. 0-15 0 use single clk for 1x allows the selection of a single clock for the gear- ing logic. on/off off 1. only 1x available when mode is bi-directional or tristate. 12-43 latticeecp2/m lattice semiconductor hi gh-speed i/o interface figure 12-50. ipexpress main window for ddr_mem configuration tab the configuration tab lists all user-accessible attribut es with default values set. upon completion, click generate to generate source and constraint files. the user may choose to use the .lpc file to load parameters. figure 12-51. configuration tab for ddr_mem the user can change the mode parameter to choose either the ddr or ddr2 interface. the other configuration parameters will change according to th e mode selected. the number of dqs parameters determ ines the number 12-44 latticeecp2/m lattice semiconductor hi gh-speed i/o interface of ddr interfaces. the software will assume there are eight data bits for every dqs. the user can also choose the frequency of operation an d the ddr dll will be configured to this frequency. the user has the option to enable the clock enable and tristate enables for th e ddr registers. it is recommend that the lock/jitter be enabled if the ddr interface is running at 150 mhz or higher. the parameters available depend on the mode selected. tables 12-17 and 12-18 describe all user parameters in the ipexpress gui and their usage for modes ddr and ddr2. table 12-17. user parameters in the ipexpress gui when in ddr mode table 12-18. user parameters in the ipexpress gui when in ddr2 mode user parameters description values/range default i/o buffer configuration i/o standard used for the interface. this will also depend on the mode selected. sstl25_i, sstl25_ii sstl25_i data width width of the data bus 8-64 8 number of dqs number of dqs will determine the number of dqs groups 1, 2, 4, 8 1 frequency of dqs ddr interface frequency. this is also input to the ddr dll. the values will depend on the mode selected. 100mhz, 133mhz, 166mhz, 200mhz 200mhz lock/jitter sensitivity dll sensit ivity to jitter high, low high lsr for ddr input register lsr control reset, set reset create clock enable for ddr input register create clock enable inputs to the block on/off off tri-state enable for ddr output registers creates tri-state contro l for the ddr data output registers. on/off on ddr tristate enable for the dqs output creates tristate control for dqs output on/off on user parameters description values/range default i/o buffer configuration i/o standard used for the interface. this will also depend on the mode selected. sstl18_i, sstl18_ii sstl18_i data width width of the data bus 8-64 8 number of dqs number of dqs will determine the number of dqs groups 1, 2, 4, 8 1 frequency of dqs ddr interface frequency. this is also input to the ddr dll. the values will depend on the mode selected. 166mhz, 200mhz, 266mhz 200mhz lock/jitter sensitivity dll sensit ivity to jitter high, low high lsr for ddr input register lsr control reset, set reset create clock enable for ddr input register create clock enable inputs to the block on/off off tri-state enable for ddr output registers creates tri-state contro l for the ddr data output registers. on/off on ddr tristate enable for the dqs output creates tristate control for dqs output on/off on dqs buffer configuration for ddr2 dqs buffer can be configured as differential on/off off www.latticesemi.com 13-1 tn1106_01.4 november 2009 technical note tn1106 ? 2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction power considerations in fpga design are critical for determining the maximum system power requirements and sequencing requirements of the fpga on the board. this technical note provides users with detailed power consid- erations such as sequencing. also included are instruct ions for calculating power consumption in latticeecp2? and latticeecp2m? devices using the power ca lculator available in the lattice isplever ? design tool. general guidelines for reducing power consumption are also discussed. power supply sequencing power-up sequencing there are three main power supplies that are required to power-up the latticeecp2/m device for proper operation: v cc , v ccaux and v ccio8 . bank 8, or v ccio8 , powers the sysconfig? port and configuration circuitry and is therefore required during power-up. the nominal voltages for these power supplies are 1.2v for v cc , 3.3v for v ccaux and 1.2v to 3.3v for v ccio8 . the nominal trip points for these power supplies are 0.6v to 0.8 v for v cc and v ccio8 , and 2.2v to 2.5v for v ccaux . for power supply sequencing, refer to the recommended operation conditions section of the latticeecp2/m family data sheet . each power supply must follow a monotonically clean ramp between the trip points and the minimum required sup- ply voltage. note that for slow ramps (w hen the power-up ramp rate is 10s or 10 0s milliseconds) it is critical that the ramp is clean and monotonic. the device may go in and out of the power-up reset if the ramp is unclean and non- monotonic, especially around the trip point. this also applies when powering down the device. a clean, monotonic ramp will ensure that the device will power up and power down properly. after initialization is complete, if any v cc , v ccaux or v ccio8 drops below its power-down trip point, the device will reset. any v ccio[7:0] can be removed without resetting the de vice after initialization is complete. refer to the latticeecp2/m family data sheet and tn1108, latticeecp2/m sysconfig usage guide , for config- uration timing and power-up information. power-down sequencing during power-down, power should be removed from one of the supplies? v cc , v ccaux or v ccio8 first to ensure that no high currents are seen on the input pins as the other v ccio supplies are removed. this only applies when input signals are still being driven, such as in hot-socketing applications. for non-hot-socketing applications, the input signals are likely to be powered from the same supply as v ccio . therefore, they will usually be less than or equal to v ccio during power down. power sequencing recommendations latticeecp2/m devices do not have a power-up sequence requirement. the supplies can be brought up in any sequence. in order to minimize the transients and hot socketing cu rrents during power up, lattice recommends that the v cc be brought up before v ccaux or v ccio8 . additionally, v cc should reach its minimum voltage value before v ccaux and v ccio8 reach their minimum values. when removing the supplies, v ccaux or v ccio8 must be removed before v cc is turned off. note that this this sequence is not a requirement for latticeecp2/m devices. power estimation and management for latticeecp2/m devices 13-2 power estimation and management lattice semiconductor for latticeecp2/m devices for latticeecp2ms power-up sequencing, refer to the recommended operation conditions section of the latticeecp2/m family data sheet . power calculator hardware assumptions the power calculator reports the power dissipation in terms of: 1. dc portion of the power consumption 2. ac portion of the power consumption total power dissipation is the sum of the static (dc) and dynamic (ac) powe r dissipations of a device. while dc power depends upon voltage, temperature and process variation, ac power is a strong function of the frequency and the activity of the resources and a weak function of voltage, temperature and process. static power or dc power dc power can be further subdivided into the power consumption of the used and unused resources. another important term is quiescent power, the dc power for a blank (be or bulk erase) device. in the bulk erase mode, none of the resources are used, so it is the total dc power of an unused device. the ac portion of the power consumption, associated with used resources, is the dynamic part of the power con- sumption. ac power dissipation is directly proportional to the frequency and activity at which the resource is run- ning and the number of resource units used. junction temperature for a fixed temperature, voltage and device package combination, quiescent power is fixed. ambient temperature that affects the junction temperature is a factor that contributes to the final power consump- tion. power calculator models this ambient-to-junction temper ature dependency. when a user provides an ambient tem- perature, it is rolled into an algorithm which calculates the junction temperature and quiescent power through an iterative process. typical and worst case process power/i cc another factor that affects the dc power is process variati on. this variation is turn causes variation in quiescent power. power calculator takes these factors into account and allows users to specify either a typical process or a worst case process. ? a typical process selection under device variation allows users to calculate the power dissipation of a design using a typical process device. ? the worst case selection under the same option provides the maximum power dissipation for the device and package combination. this informatio n is particularly useful for fpga power budgeting for the entire system. dynamic power budgets and maximum operating temperature when designing a system, designers must make sure a de vice operates at specified temperatures within the sys- tem environment. this is particularly important to consid er before a system is designed. with power calculator, users can predict device thermodyna mics and estimate the dynamic power budget. t he ability to estimate a device?s operating temperature prior to board design also allows the designer to better plan for power budgeting and airflow. although total power, ambient temperature, thermal resistance and airflow all contribute to device thermodynamics, the junction temperature (as specified in the device data sheet) is the key to device operation. the allowed junction temperature range is 0c to 85c for commercial devices and -40c to 100c for industrial devices. any time the junction temperature of the die falls out of these ranges, the performance and reliability of the device?s operation 13-3 power estimation and management lattice semiconductor for latticeecp2/m devices must be evaluated. the reliability limit of junction temperature, on t he other hand, for this ge neration of device tech- nology is 125c. let us consider an example for how to determine and use the power calculator for thermal analysis. once the user has imported or provided a ll the required information in the power ca lculator, the software will provide the power estimation and predict the junction temperature (t j ). any time this junction temperature is outside the limits spec- ified in the device data sheet, the viab ility of operating the device at this j unction temperature must be re-evaluated. a commercial device is likely to show speed degradation with a junction temperature above 85c and an industrial device at a junction temperature will degrade above 100c. it is required th at the die temperat ure be kept below these limits to achieve the guaranteed speed operation. operating a device at a higher temperature also means a higher sicc. the difference between the sicc and the total icc (both static icc and dynamic icc) at a given temperature provides the dynamic budget available. if the device runs at a dynamic icc higher than this budget, the total icc is also higher. this causes the die temperature to rise above the specified operating conditions. there are a number of ways to handle this situation. some of these are discussed in the power management sec- tion of this document. the four factors listed earlier in this section, namely power, ambient temperature, thermal resistance and airflow, can also be varied and controlled to reduce the junction temperature of the device. power calculator is a powerful tool to help system designe rs properly budget the fpga power that in turn helps improve the overall system reliability. power calculator power calculator is a powerful tool that allows users to estimate power consumption at two different levels: 1. estimate of the utilized resources before completing place and route 2. post place and route design at a coarse level of estimation, the user provides estimate s of device usage in the power calculator wizard and the tool provides a rough estimate of the power consumption. for a more accurate approach, a designer can import actu al device utilization by importing the post place and route netlist (ncd) file. power calculation equations the following are the power equations used in the power calculator: total dc power (resource) = total dc power of used portion + total dc power of unused portion = [dc leakage per resource when used * nresource] + [dc leakage per resource when unused * (n total resource - n resource )] where: n total resource is the total number of resources in a device. n resource is the number of resources used in the design. the total dc power consumption for all the resources as per the design data is the sum of the quiescent power and the individual dc power of the resources in the power calculator. total dc power (i ccaux ) = k resource * 525 a + typical standby i ccaux 13-4 power estimation and management lattice semiconductor for latticeecp2/m devices where: k resource is the number of reference input i/o such as hstl/sstl. for lvds kre- source is number of inputs divided by two. i ccaux is a dc current that does not change with i/o toggle rate or temperature. typical standby i ccaux is found in the data sheet. the ac power, on the other hand, is governed by the following equation: total ac power (resource) = k resource * f max * af resource * n resource where: n resource is the number of resources used in the design. k resource is the power constant for the resource in mw/mhz. f max is the max. frequency at which the resource is running. frequency is measured in mhz. af resource is the activity factor for the resource group.the activity factor is a percentage of the switching frequency. for example, the power consumption of the lut is calculated as per the following equation, total ac power (lut) = k lut * f max * af lut * n lut where: n lut is the number of luts used in the design. k lut is the power constant for the lut blocks in mw/mhz. f max is the max. frequency of the lut clock measured in mhz. af lut is the activity factor for the lut. the activity factor is a percentage of the switching frequency. another example is the power consumption of the ebr block, which is calculated as follows: total ac power (ebr) = k ebr * f max * af ebr * n ebr where: nebr is the number of ebr blocks used in the design. kebr is the power constant for the ebr blocks in mw/mhz. fmax is the max. frequency of the ebr clock measured in mhz. afebr is the activity factor for the read and write ports of the ebr. the activity factor is a percent- age of the switching frequency. also note that the lut can be configured in logic, ripple or distributed ram modes. each of these modes has a different power constant/power coefficient. however, the equations stay the same. the ac power of some of the dedicated blocks can be calculated using the following equation: total ac power (dedicated resource) = k resource * f max * n resource where: n resource is the number of resources used in the design. k resource is the power constant for the resource in mw/mhz. f max is the max. frequency at which the resource is running measured in mhz. 13-5 power estimation and management lattice semiconductor for latticeecp2/m devices activity factor calculation the activity factor % (or af%) is defined as the percentage of frequency (or time) that a signal is active or toggling the output. most resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running. users must provide this value as a percentage under the af% column in the power cal- culator tool. another term for i/os is the i/o toggle rate. the af% is applicable to the pfu, routing, and memory read write ports, etc. the activity of i/os is determined by the signals provided by the user (in the case of inputs) or as an out- put of the design (in the case of outputs). the rates at which i/os toggle define their activity. the i/o toggle rate or the i/o toggle frequency is a better measure of their activity. the toggle rate (or tr) in mhz of the output is defined in the following equation: toggle rate (mhz) = 1/2 * f max * af% users are required to provide the tr (mhz) value for the i/o instead of providing the frequency and af% for other resources. af can be calculated for each routing resource, output or pfu. however, this involves long calculations. the gen- eral recommendation for a design occupying roughly 30% to 70% of the device is an af% between 15% and 25%. this is an average value. the accurate value of an af depends upon clock frequency, stimulus to the design and the final output. ambient and junction temperatures and airflow a common method of characterizing a packaged device?s thermal performance is with thermal resistance, ? . in a semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a given reference for each watt of power (heat) dissipated at the die surface. its units are c/w. the most common examples are ? ja , thermal resistance junction-to-ambient (in c/w) and ? jc , thermal resis- tance junction-to-case (also in c/w). another factor is ? jb , thermal resistance junction-to-board (in c/w). knowing the reference (i.e. ambient, case or board) temperature, the power and the relevant ? value, the junction temperature can be calculated as follows. t j = t a + ? ja * p (1) t j = t c + ? jc * p (2) t j = t b + ? jb * p (3) where t j , t a , t c and t b are the junction, ambient, case (or package) and board temperatures (in c) respec- tively. p is the total power dissipation of the device. ? ja is commonly used with natural and forced convection air-cooled systems. ? jc is useful when the package has a high conductivity case mounted directly to a pcb or heat sink. ? jb applies when the board temperature adjacent to the package is known. power calculator utilizes the ambient te mperature (c) to calculate the junc tion temperature ( c) based on the ? ja for the targeted device, per equation 1 above. users can al so provide the airflow values (in lfm) to get a more accurate value of the junction temperature. managing power consumption one of the most critical factors in design today is reducing the system power consumption. low power consump- tion is especially important for hand-held devices and ot her modern electronic products. there are several design techniques that can significantly reduce overall system power consumption. these include: 13-6 power estimation and management lattice semiconductor for latticeecp2/m devices 1. reducing the operating voltage. 2. operating within the specified package temperature limitations. 3. using optimum clock frequency to reduce power consum ption, as the dynamic power is directly propor- tional to the frequency of operation. designers must determine if a portion of their design can be clocked at a lower rate, which will reduce power. 4. reducing the span of the design across the device . a more closely placed design utilizes fewer routing resources for less power consumption. 5. reducing the voltage swing of the i/os where possible. 6. using optimum encoding where possible. for example, a 16-bit binary counter has, on average, only 12% activity factor and a 7-bit binary counter has an average of 28% activity factor. on the other hand, a 7-bit linear feedback shift register can toggle as much as 50% activity factor, which causes higher power consumption. a gray code counter, where only one bit changes at ea ch clock edge, will use the least amount of power, as the activity factor is less than 10%. 7. minimizing the operating temperature, by the following methods: a. use packages that can better dissipate heat. for example, packages with lower thermal impedance. b. place heat sinks and thermal planes around the device on the pcb. c. better airflow techniques using mechanical airflow guides and fans (both system fans and device- mounted fans). power calculator assumptions the following are the assumptions made by the power calculator: 1. the power calculator tool uses equations with constants based on a room temperature of 25c. 2. the user can define the ambient temperature (t a ) for device junction temperature (t j ) calculation based on the power estimation. t j is calculated from the user-entered t a and the power calculation of typical room temperature. 3. i/o power consumption is based on an output loading of 5pf. users have the ability to ch ange this capaci- tive loading. 4. users can estimate power dissipation and current for each type of power supplies that are v cc , v ccio , v ccj , and v ccaux . for v ccaux, only static i ccaux values are provided in the power calculator. additional v ccaux contributions due to differential output buffers, differential input buffers and reference input buffers must be added per pair for differential buffers or per pin for reference input buffers according to the user's design. see the equation given in this technical note for total dc power (i ccaux ). 5. the nominal v cc is used by default to calculate the power consumption. a lower or higher v cc can be cho- sen from a list of available values. 6. users can enter an airflow in linear feet per minute (lfm) along with a heat sink option to calculate the junction temperature. 7. the default value of the i/o types for the latticeecp2/m devices is lvcmos12, 6ma. 8. the activity factor is defined as the toggle rate of the registered output. for example, assuming that the input of a flip-flop is changing at every clock cycle, 100% af of a flip-flop running at 100mhz is 50mhz. 13-7 power estimation and management lattice semiconductor for latticeecp2/m devices technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com revision history date version change summary february 2006 01.0 initial release. september 2006 01.1 updated for latticeecp2/m. added discussion on dynamic power budgets and junction tempera- ture. november 2006 01.2 added calculation of i ccaux in power calculation equations section. january 2007 01.3 updated power supply sequencing section. november 2009 01.4 updated power-up sequencing text section. updated power sequencing recommendations text section. www.latticesemi.com 14-1 tn1107_01.3 june 2010 technical note tn1107 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction this technical note discusses how to access the features of the latticeecp2? and latticeecp2m? sysdsp? (digital signal processing) block described in the latticeecp2/m family data sheet . designs targeting the sys- dsp block can offer significant improvement over traditio nal lut-based implementations. table 14-1 provides an example of the performance and area benefits of this approach: table 14-1. sysdsp block vs. lut-based multipliers sysdsp block hardware the latticeecp2/m sysdsp blocks are located in rows throughout device. below is a block diagram of one of the sysdsp blocks: figure 14-1. latticeecp2/m sysdsp block multiplier width register pipelining latticeecp2-50-7 uses one sysdsp block latticeecp2-50-7 uses luts f max (mhz) 1 luts f max (mhz) 1 luts 9x9 input, multiplier, output 404 0 124 192 18x18 input, multiplier, output 420 0 95 698 36x36 input, multiplier, output 371 0 61 2732 1. these timing numbers were generated using the isplever ? design tool. exact performance ma y vary with design and tool version. outa0(18) outb0(18) outa1(18) outb1(18) outa2(18) outb2(18) outa3(18) outb3(18) summation (38) (two 20 bits in 9x9 mode) 36x36 (mult36) accumulator (52) 1 output registers intermediate pipeline registers adder, subtractor and accumulator functions one of these one of these 36x36, 18x18 and 9x9 multiplier functions output registers to sri of right-side sysdsp block (if it exists) and/or general logic* input registers from sro of left-side sysdsp block (or tied to zero if none) accumulator (52) 3 add/sub (36) (9x9 2x18) 1 pr0 (36) in reg a0 in reg a1 in reg b1 in reg a2 in reg a3 in reg b0 in reg b2 in reg b3 9x9 9x9 36 9x9 9x9 9x9 9x9 9x9 9x9 pr1 (36) pr2 (36) pr3 (36) mult18-0 mult18-1 mult18-2 mult18-3 add/sub (36) (9x9 2x18) 3 *can only be routed to general logic routing when configured with less than three mult18x18. 36 note: each sysdsp block spans nine columns of pfus. latticeecp2/m sysdsp usage guide 14-2 latticeecp2/m lattice semiconductor sysdsp usage guide the sysdsp block can be configured as: ? one 36x36 multiplier ? basic multiplier, no add/sub/accum/sum blocks ? four 18x18 multipliers ? two add/sub/accum blocks ? one summation block for adding four multipliers ? eight 9x9 multipliers ? four add/sub blocks ? two summation blocks note that a sysdsp block can only be configured in one mode at a time. sysdsp block software overview the sysdsp block of the latticeecp2/m device can be targeted in a number of ways. ? the ipexpress? tool in the isplever or lattice diamond? design softwar e allows the rapid creation of mod- ules implementing sysdsp elements. these modules ca n then be used in hdl designs as appropriate. ? the coding of certain functions into a design?s hdl and allowing the synthesis tools to inference the use of a sysdsp block. ? the implementation of designs in the mathworks ? simulink ? tool using a lattice block set. the isplever sys- dsp design tools will then convert t hese blocks into hdl as appropriate. ? instantiation of sysdsp primitives directly in the source code targeting sysdsp bl ock using ipexpress ipexpress allows you to graphically specify sysdsp elements . once the element is specif ied, a hdl file is gener- ated, which can be instantiated in a design. ipexpress allows users to configure all ports and set all available parameters. the following modules target the sysdsp block in ipexpress: ? mult (multiplier) ? mac (multiplier accumulate) ? multaddsub (multiplier add/subtract) ? multaddsubsum (multiply add/subtract and sum) note: see appendix b for information about targeting a sysdsp block using lattice diamond design software and ipexpress. mult module the mult module configures elements to be packed into the sysdsp primitiv es. the basic mode screen illustrated in figure 14-2 consists of an optional one clock, one clock enable and one reset tied to all registers. multiple sys- dsp blocks can be spanned to accommodate large multiplic ations. additional luts may be required if multiple sysdsp blocks are needed. select area/speed to determine the lut implementation. the input data format can be selected as parallel, shift or dynamic. the shift format can only be enabled if inputs are less than 18 bits. the shift format enables a sample/shift register, which is usef ul in applications such as the fir filter. the advanced mode screen, illustrated in fi gure 14-3, allows finer control over the re gister. in the advanced mode, users can control each register with independent clocks, clock enables and resets. mult inputs can be from 2 to 72 bits. 14-3 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-2. mult mode basic set-up figure 14-3. mult mode advanced set-up 14-4 latticeecp2/m lattice semiconductor sysdsp usage guide mac module the mac module configures multiply accumulate elements to be packed into the primitive mult18x18macb. the basic mode, shown in figure 14-4, consists of an optional one clock, one clock enable and one reset tied to all reg- isters. because of the accumulator, th e output register is automatically enabled. multiple sysdsp blocks can be spanned to accommodate large multiplications. the accumulator of the sysdsp block is 52 bits deep and addi- tional luts can be used if a larger accumulation is requ ired. if sysdsp blocks are spanned, additional lut logic may be required. select area/speed to determine the lut implementation. the input data format can be selected as parallel, shift or dynamic. the shift format can only be enabled if inputs are less than 18 bits. the shift format enables a sample/shift register. the accumsload loads the accumulator with the value from the ld port. this is required to initialize and load the first value of the accumulation. the advanced mode, shown in figure 14-5, allows finer control over the registers. in the advanced mode, users can control each register with independent clocks, clock enables and resets. mac inputs can be from 2 to 72 bits. figure 14-4. mac mode basic set-up 14-5 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-5. mac mode advanced set-up multaddsub module the multaddsub gui configures multiplier addition/subtr action elements to be packed into the primitives mult18x18addsubb or mult9x9addsubb. the basic mode, shown in figure 14-6, consists of an optional one clock, one clock enable and one reset tied to all registers. multiple sysdsp blocks can be spanned to accom- modate large multiplications. if sysdsp blocks are spanned, additional lut logic may be required. select area/speed to determine the lut implementation. the input data format can be selected as parallel, shift or dynamic. the shift format can only be enabled if inputs are less than 18 bits. the shift format enables a sam- ple/shift register, which is useful in applications such as the fir filter. the advanced mode, shown in figure 14-7, provides finer control over the registers. in the advanced mode, users can control each register with independent clocks, clock enables and resets. multaddsub inputs can be from 2 to 72 bits. 14-6 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-6. multaddsub mode basic set-up figure 14-7. multaddsub mode advanced set-up 14-7 latticeecp2/m lattice semiconductor sysdsp usage guide multaddsubsum module the multaddsubsum gui configures multiplier addition/subtraction addition elements to be packed into the primitives mult18x18addsubsumb or mult9x9addsubsumb. the basic mode, shown in figure 14-8, con- sists of an optional one clock, one clock enable and one reset tied to all registers. multiple sysdsp blocks can be spanned to accommodate large multiplications. if sysdsp blocks are spanned, additional lut logic may be required. select area/speed to determine the lut implementation. the input data format can be selected as par- allel, shift or dynamic. the shift format is can only be enabled if inputs are less than 18 bits. the shift format enables a sample/shift register, which is useful in applicat ions such as the fir filter. the advanced mode, shown in figure 14-9, provides finer control over the registers. in the advanced mode, users can control each register with independent clocks, clock enables and resets. multaddsubsum inputs can be from 2 to 72 bits. figure 14-8. multaddsubsum mode basic set-up 14-8 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-9. multaddsubsum mode advanced figure 14-10. multaddsubsum mode advanced 14-9 latticeecp2/m lattice semiconductor sysdsp usage guide targeting the sysdsp block by inference the inferencing flow enables the design tools to infer sysdsp blocks from a hdl design. it is important to note that when using the inferencing flow, unle ss the code style matches the sysdsp block, results will not be optimal. con- sider the following verilog and vhdl examples: // this verilog example will be mapped into single mult18x18macb with the output register enabled module mult_acc (dataout, dataax, dataay, clk); output [16:0] dataout; input [7:0] dataax, dataay; input clk; reg [16:0] dataout; wire [15:0] multa = dataax * dataay; // 9x9 multiplier wire [16:0] adder_out; assign adder_out = multa + dataout; // accumulator always @(posedge clk) begin dataout <= adder_out; // output register of the accumulator end endmodule -- this vhdl example will be mapped into single mult18x18macb with all the registers enabled library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mac is port (clk, reset : in std_logic; dataax, dataay : in std_logic_vector(8 downto 0); dataout : out std_logic_vector(17 downto 0)); end; architecture arch of mac is signal dataax_reg, dataay_reg : std_logic_vector(8 downto 0); signal multout, multout_reg : std_logic_vector(17 downto 0); signal addout : std_logic_vector(17 downto 0); signal dataout_reg : std_logic_vector(17 downto 0); begin dataout <= dataout_reg; process (clk, reset) begin if (reset = ?1?) then dataax_reg <= (others => ?0?); dataay_reg <= (others => ?0?); elsif (clk?event and clk=?1?) then dataax_reg <= dataax; dataay_reg <= dataay; end if; end process; multout <= dataax_reg * dataay_reg; process (clk, reset) begin if (reset = ?1?) then multout_reg <= (others => ?0?); elsif (clk?event and clk=?1?) then multout_reg <= multout; end if; 14-10 latticeecp2/m lattice semiconductor sysdsp usage guide end process; addout <= multout_reg + dataout_reg; process (clk, reset) begin if (reset = ?1?) then dataout_reg <= (others => ?0?); elsif (clk?event and clk=?1?) then dataout_reg <= addout; end if; end process; end arch; the above rtl will infer the following block diagram: figure 14-11. mult18x18macb block diagram this block diagram can be mapped directly into the sysdsp primitives. note that if a test point were added between the multiplier and the accumulator, or two output registers, etc. the code could not be mapped into a mult18x18macb of a sysdsp block. theref ore, options that could be included in a design are input registers, pipeline registers, etc. multiplier accumulator 14-11 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-12. mac18x18macb packed into a sysdsp block sysdsp blocks in the report file to check the configuration of the sysdsp blocks in your design you can look at the map and place & route (par) report files. the map report file shows the mapped sysdsp components/primitives in your design. the place & route (par) report file shows the number of components in each sysdsp block. the report files that follow show how the inferred mac was used. map report file . mult18x18macb addout_17_0: multiplier operation unsigned operation registers clk ce rst -------------------------------------------- input pipeline operation registers clk ce rst -------------------------------------------- input pipeline overflow1 accum1[51:0] overflow3 accum3[51:0] mui18a0[17:0] mui18b0[17:0] mui18a3[8:0] mui18b3[8:0] sroa[17:0]* srob[17:0]* clk[3:0]** ce[3:0]* rst[3:0]* notes: *these signals are optional. **at least one clock is required. sria[17:0]* srib[17:0]* 18x18 - 0 18x18 - 2 pipe 1 pipe 0 pipe 2 18x18 - 1 18x18 - 3 unused pipe 3 out reg 3 out reg 2 out reg 1 out reg 0 52-bit accum 3 52-bit accum 1 accumsload[3,1]* addnsub[3,1]* sourceb[3,1]* sourcea[3,1]* signeda[3,1]* signedb[3,1]* +/- +/- in reg a 2 in reg b 2 in reg a 3 in reg b 3 in reg a 0 in reg b 0 in reg a1 in reg b1 sload data1[15:0]* mui18a2[17:0] mui18b2[17:0] sload data3[15:0]* mui18a1[17:0] mui18b1[17:0] 14-12 latticeecp2/m lattice semiconductor sysdsp usage guide addsub operation add operation registers clk ce rst -------------------------------------------- input pipeline data input registers clk ce rst --------------------------------------------- a clk0 ce0 rst0 b clk0 ce0 rst0 pipeline registers clk ce rst -------------------------------------------- pipe clk0 ce0 rst0 output register clk ce rst -------------------------------------------- output clk0 ce0 rst0 other gsr enabled number of mapped dsp components: -------------------------------- mult36x36b 0 mult18x18b 0 mult18x18macb 1 mult18x18addsubb 0 mult18x18addsubsumb 0 mult9x9b 0 mult9x9addsubb 0 mult9x9addsubsumb 0 -------------------------------- place & route (par) report file dsp utilization summary: dsp block #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 # of mult36x36b # of mult18x18b # of mult18x18macb 1 # of mult18x18addsubb # of mult18x18addsubsumb # of mult9x9b # of mult9x9addsubb # of mult9x9addsubsumb dsp block 1 component_type instance_name dsp block 2 component_type instance_name dsp block 3 component_type instance_name dsp block 4 component_type instance_name dsp block 5 component_type instance_name dsp block 6 component_type instance_name dsp block 7 component_type instance_name dsp block 8 component_type instance_name dsp block 9 component_type instance_name r45c81 mult18x18macb addout_17_0 dsp block 10 component_type instance_name dsp block 11 component_type instance_name dsp block 12 component_type instance_name dsp block 13 component_type instance_name dsp block 14 component_type instance_name dsp block 15 component_type instance_name dsp block 16 component_type instance_name dsp block 17 component_type instance_name dsp block 18 component_type instance_name 14-13 latticeecp2/m lattice semiconductor sysdsp usage guide targeting the sysdsp block using simulink simulink overview simulink is a graphical add-on (similar to schematic entry) for matlab ? , which is produced by the mathworks. for more information, refer to the simulink web page at www.mathworks.com/products/simulink/ . why is simulink used? ? it allows users to create algorithms using floating point numbers. ? it helps users convert floating point algorithms into fixed point algorithms. how does simulink fit into the normal isplever or diamond design/process flow? ? once you have converted have your algorithm working in fixed point. you can use the lattice ispdsp block to create hdl files, which can be in stantiated in your hdl design. what does lattice provide? ? lattice provides a library of blocks for the simulink to ol, which include multipliers, adders, registers, and other standard building blocks. besides the basic building blocks there are a couple unique lattice blocks: gateways in and out everything between gateways in and out represents the hdl code. everything before a gateway in is the stim- ulus your test bench. everything after the gateway out are the si gnals you will be monitoring in the test bench. below is an example. the box on the left contains gateway in blocks and the three boxes on the right contain gateway out blocks in figure 14-13. generate the generate block is used to convert fixed point simulink design into hdl files which can be instantiated in a hdl design. the generate block is identified by the lattice logo and can be seen in figure 14-13. 14-14 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-13. simulink design targeting the sysdsp block by instantiating primitives the sysdsp block can be targeted by instantiating the sysdsp block primitives into the design. the advantage of instantiating primitives is that it provides access to all ports and sets all available parameters. the disadvantage of this flow is that all this customizat ion requires extra coding by the user. appendix a details the syntax for the sys- dsp block primitives. sysdsp block control signal and data signal descriptions rst asynchronous reset of selected registers ce clock enable 1 = enabled, 0 = disabled signeda dynamic signal: 0 = unsigned, 1 = signed signedb dynamic signal: 0 = unsigned, 1 = signed accumsload dynamic signal: 0 = accumulate, 1 = load addnsub dynamic signal: 0 = subtract, 1 = add sourcea dynamic signal: 0 = par allel input, 1 = shift input sourceb dynamic signal: 0 = par allel input, 1 = shift input 14-15 latticeecp2/m lattice semiconductor sysdsp usage guide technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com revision history date version change summary february 2006 01.0 initial release. september 2006 01.1 updated table 1 with new software numbers. updated figure 1 summation size from 37 to 38 november 2008 01.2 updated sysdsp block control signal and data signal descriptions. june 2010 01.3 updated for lattice diamond design software support. 14-16 latticeecp2/m lattice semiconductor sysdsp usage guide appendix a. dsp block primitives mult18x18b input a17,a16,a15,a14,a13,a12,a11,a10,a9,a8,a7,a6,a5,a4,a3,a2,a1,a0; input b17,b16,b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0; input signeda, signedb, sourcea, sourceb; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria17,sria16,sria15,sria14,sria13,sria12,sria11,sria10,sria9; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib17,srib16,srib15,srib14,srib13,srib12,srib11,srib10,srib9; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa17,sroa16,sroa15,sroa14,sroa13,sroa12,sroa11,sroa10,sroa9; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob17,srob16,srob15,srob14,srob13,srob12,srob11,srob10,srob9; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output p35,p34,p33,p32,p31,p30,p29,p28,p27,p26,p25,p24,p23,p22,p21,p20,p19,p18; output p17,p16,p15,p14,p13,p12,p11,p10,p9,p8,p7,p6,p5,p4,p3,p2,p1,p0; parameter reg_inputa_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb_ce = = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult18x18addsubb input a017,a016,a015,a014,a013,a012,a011,a010,a09; input a08,a07,a06,a05,a04,a03,a02,a01,a00; input a117,a116,a115,a114,a113,a112,a111,a110,a19; input a18,a17,a16,a15,a14,a13,a12,a11,a10; input b017,b016,b015,b014,b013,b012,b011,b010,b09; input b08,b07,b06,b05,b04,b03,b02,b01,b00; input b117,b116,b115,b114,b113,b112,b111,b110,b19; input b18,b17,b16,b15,b14,b13,b12,b11,b10; input signeda, signedb, sourcea0, sourcea1, sourceb0, sourceb1, addnsub; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria17,sria16,sria15,sria14,sria13,sria12,sria11,sria10,sria9; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib17,srib16,srib15,srib14,srib13,srib12,srib11,srib10,srib9; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa17,sroa16,sroa15,sroa14,sroa13,sroa12,sroa11,sroa10,sroa9; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob17,srob16,srob15,srob14,srob13,srob12,srob11,srob10,srob9; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output sum36,sum35,sum34,sum33,sum32,sum31,sum30,sum29,sum28,sum27,sum26,sum25,sum24,sum23,sum22,sum21,su m20,sum19,sum18,sum17,sum16,sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum4,sum3 ,sum2,sum1,sum0; 14-17 latticeecp2/m lattice semiconductor sysdsp usage guide parameter reg_inputa0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult18x18addsubsumb input a017,a016,a015,a014,a013,a012,a011,a010,a09; input a08,a07,a06,a05,a04,a03,a02,a01,a00; input a117,a116,a115,a114,a113,a112,a111,a110,a19; input a18,a17,a16,a15,a14,a13,a12,a11,a10; input a217,a216,a215,a214,a213,a212,a211,a210,a29; input a28,a27,a26,a25,a24,a23,a22,a21,a20; input a317,a316,a315,a314,a313,a312,a311,a310,a39; input a38,a37,a36,a35,a34,a33,a32,a31,a30; input b017,b016,b015,b014,b013,b012,b011,b010,b09; input b08,b07,b06,b05,b04,b03,b02,b01,b00; input b117,b116,b115,b114,b113,b112,b111,b110,b19; input b18,b17,b16,b15,b14,b13,b12,b11,b10; input b217,b216,b215,b214,b213,b212,b211,b210,b29; input b28,b27,b26,b25,b24,b23,b22,b21,b20; input b317,b316,b315,b314,b313,b312,b311,b310,b39; input b38,b37,b36,b35,b34,b33,b32,b31,b30; input signeda, signedb,addnsub1,addnsub3; input sourcea0, sourcea1, sourcea2, sourcea3; input sourceb0, sourceb1, sourceb2, sourceb3; 14-18 latticeecp2/m lattice semiconductor sysdsp usage guide input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria17,sria16,sria15,sria14,sria13,sria12,sria11,sria10,sria9; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib17,srib16,srib15,srib14,srib13,srib12,srib11,srib10,srib9; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa17,sroa16,sroa15,sroa14,sroa13,sroa12,sroa11,sroa10,sroa9; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob17,srob16,srob15,srob14,srob13,srob12,srob11,srob10,srob9; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output sum37,sum36,sum35,sum34,sum33,sum32,sum31,sum30,sum29,sum28,sum27,sum26,sum25,sum24,sum23,sum22,su m21,sum20,sum19,sum18,sum17,sum16,sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum 4,sum3,sum2,sum1,sum0; parameter reg_inputa0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; 14-19 latticeecp2/m lattice semiconductor sysdsp usage guide parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub1_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub1_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub1_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub1_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub1_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub1_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub3_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub3_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub3_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub3_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub3_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub3_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult18x18macb input a17,a16,a15,a14,a13,a12,a11,a10,a9; input a8,a7,a6,a5,a4,a3,a2,a1,a0; input b17,b16,b15,b14,b13,b12,b11,b10,b9; input b8,b7,b6,b5,b4,b3,b2,b1,b0; input addnsub, signeda, signedb,accumsload; input sourcea, sourceb; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input ld51, ld50, ld49, ld48, ld47, ld46, ld45, ld44, ld43, ld42, ld41, ld40 input ld39, ld38, ld37, ld36, ld35, ld34, ld33, ld32, ld31, ld30 input ld29, ld28, ld27, ld26, ld25, ld24, ld23, ld22, ld21, ld20 input ld19, ld18, ld17, ld16, ld15, ld14, ld13, ld12, ld11, ld10 input ld9, ld8, ld7, ld6, ld5, ld4, ld3, ld2, ld1, ld0; input sria17,sria16,sria15,sria14,sria13,sria12,sria11,sria10,sria9; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib17,srib16,srib15,srib14,srib13,srib12,srib11,srib10,srib9; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa17,sroa16,sroa15,sroa14,sroa13,sroa12,sroa11,sroa10,sroa9; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob17,srob16,srob15,srob14,srob13,srob12,srob11,srob10,srob9; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output accum51,accum50,accum49,accum48,accum47,accum46,accum45,accum44,accum43,accum42,accum41,accum40,ac cum39,accum38,accum37,accum36,accum35,accum34,accum33,accum32,accum31,accum30,accum29,accum28,accu m27,accum26,accum25,accum24,accum23,accum22,accum21,accum20,accum19,accum18,accum17,accum16,accum1 5,accum14,accum13,accum12,accum11,accum10,accum9,accum8,accum7,accum6,accum5,accum4,accum3,accum2, accum1,accum0,overflow; parameter reg_inputa_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; 14-20 latticeecp2/m lattice semiconductor sysdsp usage guide parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_accumsload_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_accumsload_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_accumsload_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_accumsload_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_accumsload_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_accumsload_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult36x36b input a35,a34,a33,a32,a31,a30,a29,a28,a27,a26,a25,a24,a23,a22,a21,a20,a19,a18; input a17,a16,a15,a14,a13,a12,a11,a10,a9,a8,a7,a6,a5,a4,a3,a2,a1,a0; input b35,b34,b33,b32,b31,b30,b29,b28,b27,b26,b25,b24,b23,b22,b21,b20,b19,b18; input b17,b16,b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0; input signeda, signedb; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; output p71,p70,p69,p68,p67,p66,p65,p64,p63,p62,p61,p60,p59,p58,p57,p56,p55,p54; output p53,p52,p51,p50,p49,p48,p47,p46,p45,p44,p43,p42,p41,p40,p39,p38,p37,p36; output p35,p34,p33,p32,p31,p30,p29,p28,p27,p26,p25,p24,p23,p22,p21,p20,p19,p18; output p17,p16,p15,p14,p13,p12,p11,p10,p9,p8,p7,p6,p5,p4,p3,p2,p1,p0; parameter reg_inputa_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; 14-21 latticeecp2/m lattice semiconductor sysdsp usage guide mult9x9b input a8,a7,a6,a5,a4,a3,a2,a1,a0; input b8,b7,b6,b5,b4,b3,b2,b1,b0; input signeda, signedb, sourcea, sourceb; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output p17,p16,p15,p14,p13,p12,p11,p10,p9,p8,p7,p6,p5,p4,p3,p2,p1,p0; parameter reg_inputa_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult9x9addsubb input a08,a07,a06,a05,a04,a03,a02,a01,a00; input a18,a17,a16,a15,a14,a13,a12,a11,a10; input b08,b07,b06,b05,b04,b03,b02,b01,b00; input b18,b17,b16,b15,b14,b13,b12,b11,b10; input signeda, signedb,addnsub; input sourcea0, sourcea1, sourceb0, sourceb1; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output sum18,sum17,sum16,sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum4,sum3,sum2,sum1 ,sum0; parameter reg_inputa0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline0_rst = ? rst0, rst1, rst2, rst3 ?; 14-22 latticeecp2/m lattice semiconductor sysdsp usage guide parameter reg_pipeline1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; mult9x9addsubsumb input a08,a07,a06,a05,a04,a03,a02,a01,a00; input a18,a17,a16,a15,a14,a13,a12,a11,a10; input a28,a27,a26,a25,a24,a23,a22,a21,a20; input a38,a37,a36,a35,a34,a33,a32,a31,a30; input b08,b07,b06,b05,b04,b03,b02,b01,b00; input b18,b17,b16,b15,b14,b13,b12,b11,b10; input b28,b27,b26,b25,b24,b23,b22,b21,b20; input b38,b37,b36,b35,b34,b33,b32,b31,b30; input signeda, signedb,addnsub1,addnsub3; input sourcea0, sourcea1, sourcea2, sourcea3; input sourceb0, sourceb1, sourceb2, sourceb3; input ce0,ce1,ce2,ce3,clk0,clk1,clk2,clk3,rst0,rst1,rst2,rst3; input sria8,sria7,sria6,sria5,sria4,sria3,sria2,sria1,sria0; input srib8,srib7,srib6,srib5,srib4,srib3,srib2,srib1,srib0; output sroa8,sroa7,sroa6,sroa5,sroa4,sroa3,sroa2,sroa1,sroa0; output srob8,srob7,srob6,srob5,srob4,srob3,srob2,srob1,srob0; output sum19,sum18,sum17,sum16,sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum4,sum3,sum 2,sum1,sum0; parameter reg_inputa0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputa3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputa3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputa3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb0_rst = ? rst0, rst1, rst2, rst3 ?; 14-23 latticeecp2/m lattice semiconductor sysdsp usage guide parameter reg_inputb1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_inputb3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_inputb3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_inputb3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline2_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline2_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline2_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_pipeline3_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_pipeline3_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_pipeline3_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_output_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_output_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_output_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signeda_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signeda_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signeda_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_signedb_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_signedb_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_signedb_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub1_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub1_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub1_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub1_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub1_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub1_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub3_0_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub3_0_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub3_0_rst = ? rst0, rst1, rst2, rst3 ?; parameter reg_addnsub3_1_clk = ? none, clk0, clk1, clk2, clk3 ?; parameter reg_addnsub3_1_ce = ? ce0, ce1, ce2, ce3 ?; parameter reg_addnsub3_1_rst = ? rst0, rst1, rst2, rst3 ?; parameter gsr = ? enabled, disabled ?; 14-24 latticeecp2/m lattice semiconductor sysdsp usage guide appendix b. using ip express for diamond invoking ipexpress for diamond there are several ways ipexpress can be invoked. to invoke ipexpress from the start menu, select: start > programs > lattice diamond 1.0 > accessories > ipexpress to invoke ipexpress from within diamond, a project must be opened, then invoke the ipexpress icon or select: tools > ipexpress the ipexpress interface appears as shown in figure 14-14. figure 14-14. ipexpress interface scroll to the modules and left-click on the module you wish to use. enter the information into the ipexpress inter- face as shown in the example figure 14-15. 14-25 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-15. creating the module instance select customize . an example of a mult module dialog window appears as shown in figure 14-16. select help for information about the fields in this window. 14-26 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-16. mult mode basic set-up when you are finished selecting your options, select generate . a log window will appear similar to what is shown in figure 14-17. 14-27 latticeecp2/m lattice semiconductor sysdsp usage guide figure 14-17. ip generation log window www.latticesemi.com 15-1 tn1108_02.2 june 2010 technical note tn1108 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction the configuration memory in the latticeecp2? and latticeecp2m? fpgas is built using volatile sram; there- fore, an external non-volatile configuration memory is required to maintain the configuration data when the power is removed. this non-volatile memory supplies the configuration data to the latticeecp2/m when it powers-up, or any other time the device needs to be updated. to support multiple configuration options the latticeecp2 /m supports the lattice sysconfig? interface, as well as the dedicated ispjtag? port. the available configuration options, or ports, are listed in table 15-1. table 15-1. supported configuration ports this technical note covers all of the configuration options available for latticeecp2/m. general configuration flow the latticeecp2/m will enter configuratio n mode when one of thr ee things happens, power is applied to the chip, the programn pin is driven low, or when a jtag refresh instruction is issued. upon entering configuration mode the initn pin and the done pin are driven low to indicate that the device is initializing, i.e. getting ready to receive configuration data. once the latticeecp2/m has finished initializing, the initn pin will be driven high. the low to high transition of the initn pin causes the cfg pins to be sa mpled, telling the la tticeecp2/m which port it is going to configure from. the latticeecp2/m then begins reading data from the selected port and starts looking for the preamble, bdb3 (hex). all data after the preamble is valid configuration data. when the latticeecp2/m has finished reading all of the configuration data, assuming there have been no errors, the done pin goes high and the lattic eecp2/m enters user mode, in other words the device begins to function according to the user?s design. note that the latticeecp2/m may also be programmed via jtag. when programming via jtag, the initn and done signals have no meanin g, because jtag, per the ieee standard, takes comp lete control of t he chip and it?s i/os. the lattice ecp2/m devices are also available in an "s" version which supports the use of an encrypted bitstream configuration file. these versions have the same configuration options as the standard versions, except where noted in this document. when using these devices, the user should refer to the latticeecp2/m family data sheet and tn1109, latticeecp2/m configuration encryption usage guide , in addition to this document, to understand the configuration requirements. the following sections define each configuration pin, each configuration mode, and all of the configuration options for the latticeecp2/m. interface port sysconfig spi spim slave serial slave parallel ispjtag jtag (ieee 1149.1 and ieee 1532 compliant) latticeecp2/m sysconfig usage guide 15-2 lattice semiconductor latticeecp 2/m sysconfig usage guide configuration pins the latticeecp2/m supports two types of configuration pi ns, dedicated and dual-purpose. the dedicated pins are used exclusively for configuration; the dual-purpose pins , when not being used for configuration, are available as extra i/o pins. if a dual-purpose pin is to be used both for configuration and as a general purpose i/o (gpio) the user must adhere to the following: ? the i/o type must remain the same, in other words if the pin is a 3.3v cmos pin (lvcmos33) during configura- tion it must remain a 3.3v cmos pin as a gpio. ? the user must select the correct config_mode setting and set the persistent bit to off in order to use the dual-purpose sysconfig pins as gpio after co nfiguration. in isplever ? these preferences can be set in the design planner. if you are using lattice diamond? design software, select tools > spreadsheet view and then select the global preferences tab in the spreadsheet view. ? the user is responsible for insuring that no internal or external logic will interfer e with device configuration. also, if slave parallel configuration mode is not being used then one or both of the parallel port chip selects (csn, cs1n) must be high or tri-state during configuration. programmable options control the direction and type of each dual-purpose configuration pin. these options are controlled via pin preferences in lattice isplever and diamond software, or as hdl source file attributes. the latticeecp2/m also supports ispjtag for configuratio n, transparent read back, and jtag testing. the follow- ing sections describe the function of the various sysconfi g and jtag pins. table 15-2 is provided for reference. table 15-2. configuration pins for the latticeecp2/m pin name i/o type pin type mode used cfg[2:0] input, weak pull-up dedicated all programn input, weak pull-up dedicated all initn bi-directional open drain, weak pull-up dedicated all done bi-directional open drain with weak pull- up, or active drive dedicated all cclk input or output dedicated all di/csspi0n 2 input, weak pull up dual-purpose serial, spi, spim dout/cson 2 output dual-purpose parallel, serial, spi csn 2 input, weak pull-up dual-purpose parallel cs1n 2 input, weak pull-up dual-purpose parallel writen 2 input, weak pull-up dual-purpose parallel busy/sispi 2 output, tri-state, weak pull-up dual-purpose serial, spi, spim d[0]/spifastn 2 input or output dual-purpose parallel, spi, spim d[1:6] 2 parallel d[7]/spid0 2 parallel, spi, spim tdi input, weak pull-up dedicated jtag tdo output, weak pull-up dedicated jtag tck input with hysteresis dedicated jtag tms input, weak pull-up dedicated jtag 1. weak pull-ups consist of a cu rrent source of 30a to 150a. the pull-ups fo r sysconfig dedicated and dual-purpose pins track v ccio8 ; the pull-ups for tdi, tdo, and tms track v ccj . 2. the sysconfig pins on the latticeecp2m50/m70/m100 are dedicated sysconfig pins. the sysconfig out put pins are actively driven during normal device operation. 15-3 lattice semiconductor latticeecp 2/m sysconfig usage guide dedicated control pins the following sub-sections describe the latticeecp2/m dedicated sysconfig pins. these pins are powered by v ccio8 . while the device is under ieee 1149.1 or 1532 jtag co ntrol the dedicated programm ing pins have no meaning. this is because a boundary scan cell w ill control each pin, per jtag 1149.1, rather than normal internal logic. cfg[2:0] the configuration mode pins, cfg[2:0], are dedicated inputs with weak pull-ups. the cfg pins are sampled on the rising edge of initn and are used to select the configuration mode, i.e. what type of device the latticeecp2/m will configure from. as a consequence the cfg pins determine which groups of dual-purpose pins will be used for device configuration (see the right-most column in table 15-2). see table 15-3 for a list of configuration modes. table 15-3. configuration modes programn the programn pin is a dedicated input with a weak pull-up . this pin is used to initiate a non-jtag sram config- uration sequence. a high to low signal applied to programn takes the device out of user mode and sets it into configuration mode. the low to high transition will initiate the configuration process. the programn pin can be used to trigger config- uration at any time. initn the initn pin is a bidirectional open drain control pin. init n is capable of driving a low pulse out as well as detect- ing a low pulse driven in. when the programn pin is driven low, or a jtag reset instruction is received, or after the internal power-on- reset signal is released during powe r-up, the initn pin will be driven low to reset the internal configuration cir- cuitry. once the programn pin is driven high, the config uration initialization begins. once the configuration ini- tialization is completed, the initn pin will go high. to delay configuration the initn pin can be held low externally. the device will not enter configuration mode as long as the initn pin is held low. a low to high transition on initn causes the cfg pins to be sampled, telling the latticeecp2/m which port to use, and starts configuration. during configuration the initn pin becomes an error detection pin. if a crc error is detected during configuration initn will be driven low. the error will be cleare d at the beginning of th e next configuration. configuration mode cfg[2] cfg[1] cfg[0] d[0]/spifastn spi normal (0x03) 0 0 0 pull-up fast (0x0b) 0 0 0 pull-down reserved 001x spim normal (0x03) 0 1 0 pull-up fast (0x0b) 0 1 0 pull-down reserved 011x reserved 100x slave serial 1 0 1 x reserved 110x slave parallel 1 1 1 d0 notes: jtag is always available for ieee 1149.1 and 1532 support. 15-4 lattice semiconductor latticeecp 2/m sysconfig usage guide done the done pin is a dedicated bi-directional open drain with a we ak pull-up (default), or it is an actively driven pin. done goes low when initn goes low, when initn and programn go high, and the internal done bit is pro- grammed at the end of configur ation, the done pin will be rele ased (or driven high, if it is an actively driven pin). the done pin can be held low externally and, dependi ng on the wake-up sequence selected, the device will not become functional until the done pin is externally brou ght high. externally delaying the wake-up sequence using the done pin is a good way to synchronize the wake-up of multiple fpgas; it is also required when configuring multiple fpgas from a single configuration device. sampling the done pin is a good way for an external device to tell if the fpga has finished configuration. how- ever, when using ieee 1532 jtag to co nfigure sram the done pin is driven by a boundary scan cell, so the state of the done pin has no meaning during ieee 1532 jtag configuration (once configur ation is complete, done reverts to internal logic and will be high). cclk cclk is a dedicated bi-directional pin; direction depends on whether a master or slave mode is selected. if a mas- ter mode (spi or spim) is selected, via the cfg pins, the cclk pin becomes an output; otherwise cclk is an input. if the cclk pin becomes an output, the in ternal programmable oscillator is connec ted to cclk and is driven out to slave devices. cclk will stop 120 cloc k cycles after the done pin is brought high. the extra clock cycles ensure that enough clocks are provided to wake-up other devices in the chain. when stopped, cclk becomes an input (tri-stated output). cclk will restart (become an output again) on the ne xt configuration init ialization sequence. the mcclk_freq parameter ( one of the global pr eferences in the design pla nner of isplever or the spread- sheet view in diamond) controls the ccl k master frequency (see data sheet on-chip oscillator section for the fre- quency selection). the software default setting for the configuration cclk is 2.5 mhz. for a complete list of the supported master clock frequencies, please see the latticeecp2/m family data sheet . one of the first operations during configuration is the mcclk_freq parameter; once this parameter is loaded the frequency changes to the selected value. care should be exercised not to exceed the frequency specification of the slave devices or the sig- nal integrity capabilities of the pcb layout. when downloading an encrypted bitstream file to the latticeecp2/m s-series devices, the user must adhere to the appropriate conditions for the cclk signal. these conditions are shown in tn1109, latticeecp2/m configuration encryption usage guide . dual-purpose sysconfig pins the following is a list of the dual-purpose sysconfig pins. if any of these pins are used for configuration and for user i/o, the user must adhere to the requirements listed at the start of the configuration pin sections. on latticeecp2m50/m70/m100 devices, the sysconfig pins described below are dedicated pins. when using the same pins to access the external boot flash, the system design must take care of tri-stating these output pins while driving these pins from a different i/o pin. these pins are powered by v ccio8 . di/csspi0n the di/csspi0n dual-purpose pi n is designated as di (data input) for se rial configurations. di has an internal weak pull-up. di captures data on the rising edge of cclk. in spi or spim mode the di/csspi0n becomes a low true chip select output that drives the spi serial flash chip select. dout/cson the dout/cson pin is an output pin and has two purposes. 15-5 lattice semiconductor latticeecp 2/m sysconfig usage guide for serial and parallel configuration modes, when bypass mode is selected, this pin becomes dout (see figure 15-9). when the device is fully configured a bypass instruction in the bitstream is executed and the data on di, or d[0:7] in the case of a parallel configuration mode, will then be rout ed to the dout pin. this allows data to be passed, serially, to the next device. in a parallel configuration mode d0 will be shifted out first followed by d1, d2, and so on. for parallel configuration mode there is a flowthrough option as well. when flowthrough mode is selected this pin becomes chip select out (cson). when the device is fully configured, and the flowthrough instruction in the bit- stream is executed, the cson pin is driven low to enable the next device. the data pins, d[0:7], are wired in paral- lel to each device in the chain (see figure 15-10). in spim mode, the sysconfig daisy chaining mode of configuration is not supported. the dout/cson drives out a high on power-up and will cont inue to do so until the execution of the bypass/flow through instruction within the bitstream, or until the i/o type is changed by the user code. csn and cs1n both csn and cs1n are active low input pins with weak pull-ups and are used in parallel mode only. these inputs are or?ed and used to enable the d[0:7] data pins to receive or output a byte of data. when csn or cs1n is high, the d[0:7], and busy pins are tri-stated. csn and cs1n are interchangeable when controlling the d[ 0:7], and busy pins. driving both csn and cs1n high causes the lattic eecp2/m to exit bypass or flowthrough mode and resets the by pass register. if bypass or flowthroug h mode will not be used then csn or cs1n may be tied low, i.e. in this case it is only required that one of thes e pins be driven. the csn and cs1n pins must remain low while the configurat ion bitstream is being sent to the device or the configuration will fail. if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve these pins as csn and cs1n. note that sram may only be read using jtag or slave parallel mode. writen the writen pin is an active low input with a weak pull-up and used for parallel mode only. the writen pin is used to determine the direction of the data pins d[0:7]. the writen pin must be driven low in order to clock a byte of data into the device and driven high to clock data out of the device. if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as writen. note that sram may only be read using jtag or slave parallel mode. busy/sispi the busy/sispi pin has two functions. in parallel configuration mode, the busy pin is a tri-stated output. the busy pin will be driven low by the device only when it is ready to receive a byte of data on d[0:7] or a byte of data is ready for reading. the busy pin allows the latticeecp2/m to pause transfers on the parallel port. if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as busy. note that sram may only be read using jtag or slave parallel mode. in spi or spim configuration modes, the busy/sispi pin becomes an output that drives control and data to the spi serial flash. control and data ar e output on the falling edge of cclk. if spi memory needs to be accessed using the spi port while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as sispi. 15-6 lattice semiconductor latticeecp 2/m sysconfig usage guide d[0]/spifastn the d[0]/spifastn pin has two functions. in parallel mode this pin is d[0] and operates in the same way as d[1:6] below. taken together d[0:7] form the par- allel data bus, d[0] is the most signif icant bit in the byte. as with d[1:6], if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as d[0]. note that sram may only be read using jtag or slave parallel mode. in spi or spim mode the d[0]/spifastn pin becomes an input. spifastn is sampled on the rising edge of initn. if spifastn is high the latticeecp2/m will use spi serial flash read op-code 03 (hex). read op-code 03 (hex) is the standard read command used by all ?25? series spi serial flash. if spifastn is low the latticeecp2/m will use spi serial flash fast read op-co de 0b (hex). the fast read op-code 0b (hex) accommo- dates higher frequency read clocks, exact clock speeds can be found in the spi serial flash manufacturer?s data sheet. if spi memory needs to be accessed using the spi port while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as spifastn. when using the spi or spim mode the spifastn pin should either be tied high or low. it must not be left floating or configuration problems will occur. not all spi serial flash support the 0b (hex) fast read op-code, consult the manufacturer?s data sheet. care must also be taken not to exceed the signal integrity capabilities of the pcb layout. d[1:6] the d[1:6] pins support parallel mode only. the d[1:6] pins are tri-statable bi-directional i/o pins used for data write and read. when the writen signal is low, and the csn and cs1n pins are low, the d[1:6] pins become data inputs. when the writen signal is driven high, and the csn and cs1n pins are low, the d[1:6] pins become data outputs. if either csn or cs1n is high d[1:6] will be tri-state. if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as d[1:6]. note that sram may only be read using jtag or slave parallel mode. care must be exercised during read back of ebr or pfu memory. it is up to the user to ensure that reading these rams will not cause data corruption; corruption may be c aused when these rams are read while being accessed by user code. d[7]/spid0 the d[7]/spid0 pin has two functions. in parallel mode this pin is d[7] and operates in the same way as d[1:6] above. taken together d[0:7] form the par- allel data bus, d[7] is the least significant bit in the byte. as with d[1:6], if sram (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as d[7]. note that sram may only be read using jtag or slave parallel mode. in spi or spim mode the d[7]/spid0 pin becomes an input and should be wired to the output data pin of the spi serial flash. the data on spid0 is clocked in on the rising edge of cclk. if spi memory needs to be accessed using the spi port while the part is in user mode (the done pin is high) then the persistent preference must be set to on to preserve this pin as spid0. ispjtag pins the ispjtag pins are standard ieee 11 49.1 tap (test access port) pins. the ispjtag pins are de dicated pins and are always accessible when the latticeecp2/m device is powered up. while the device is under 1149.1 or 1532 15-7 lattice semiconductor latticeecp 2/m sysconfig usage guide jtag control the dedicated programming pins initn, do ne, and cclk have no meaning. this is because a boundary scan cell will control each pin, per the ieee standa rd, rather than normal in ternal logic. while the latticeecp2/m is under jtag contro l the programn pin will be ignored. these pins are powered by v ccj . tdo the test data output pin is used to shift out serial test instructions and data. when tdo is not being driven by the internal circuitry, the pin will be in a high impedance state. this pin should be wired to tdo of the jtag connector, or to tdi of a downstream device in a jtag chain. an internal pull-up resistor on the tdo pin is provided. the internal resistor is pulled up to v ccj . tdi the test data input pin is used to shift in serial test in structions and data. this pin should be wired to tdi of the jtag connector, or to tdo of an upstream device in a jtag chain. an internal pull-up resistor on the tdi pin is provided. the internal resistor is pulled up to v ccj . tms the test mode select pin cont rols test operations on the tap controller. on the falling edge of tck, depending on the state of tms, a tran sition will be made in the tap controller state ma chine. an internal pu ll-up resistor on the tms pin is provided. the internal resistor is pulled up to v ccj . tck the test clock pin, tck, provides the clock to run the tap controller state machine, which loads and unloads the jtag data and instruction registers. tck can be stopped in either the high or low state and can be clocked at fre- quencies up to that indicated in the device data sheet. the tck pin supports hysteresis; the typical hysteresis is approximately 100mv when v ccj = 3.3v. the tck pin does not have a pull-up. a pull-down resistor between tck and ground on the pcb of 4.7 k is recommended to avoid inadvertent clocking of the tap controller as v cc ramps up. when downloading an encrypted bitstream file to the latticeecp2/m s-series devices, the user must adhere to the appropriate conditions for the tck signal . these conditions are shown in tn1109, latticeecp2/m configuration encryption usage guide . optional trst test reset, trst, in not supported on the latticeecp2/m. v ccj having a separate jtag v cc (v ccj ) pin lets the user apply a voltage level to the jtag port that is independent from the rest of the device. valid voltage levels are 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v, but the voltage used must match the other voltages in the jtag chain. v ccj must be connected even if jtag is not used. please see in-system programming design gu idelines for ispjtag devices for further information. configuration and jtag pi n physical description all of the sysconfig dedicated and dual-purpo se pins are part of bank 8. bank 8 v ccio determines the output voltage level of these pins, input th resholds are determined by the i/o ty pe selected in the isplever design plan- ner (default is 3.3v lvcmos) or diamond spreadsheet view. jtag voltage levels and thresholds are determined by the v ccj pin, allowing the latticeecp2/m to accommodate jtag chain voltages from 1.2v to 3.3v. configuration modes the latticeecp2/m devices sup port many different configuration modes, utilizing either serial or parallel data paths. on power-up, when a jtag refresh instruction is issued, or when the programn pin is toggled, the 15-8 lattice semiconductor latticeecp 2/m sysconfig usage guide cfg[2:0] pins are sampled to determine the configuration mode. see table 15-3 above for a list of available config- uration modes. the following sub-sections break down each configuration mode. for more information on the options for each mode, see the section below entitled configuration options. spi mode the latticeecp2/m offers a direct connection to memo ries that support the spi serial flash standard (see table 15-6). by setting the conf iguration pins, cfg[2:0], to all zeros th e latticeecp2/m will configure from the spi interface. the spi interface supports two configuration topologies: ? one fpga configured from one spi serial flash ? multiple fpgas configured from one spi serial flash the required boot memory size for each of the ecp2/m device sizes is shown in table 15-4. the values shown are for a single latticeecp2/m device. the size for a dual-boot application would be twice that shown. table 15-4. maximum configuration bits - spi flash mode bitstream file table 15-5. maximum configuration bits - serial and parallel mode bitstream file device bitstream size (mb) spi fl ash (mb) dual boot spi flash (mb) ecp2-6 1.5 2 4 / 8 2 ecp2-12 2.9 4 8 ecp2-20 4.5 8 16 ecp2-35 6.3 8 16 ecp2-50 8.9 16 32 ecp2-70 13.3 16 32 ecp2m-20 5.9 8 16 ecp2m-35 9.8 16 32 ecp2m-50 15.8 16 64 ecp2m-70 19.8 32 64 ecp2m-100 25.6 32 64 1. these values apply for both encrypted and unencrypted bi tstream files in the spi flash mode except as noted below. 2. for the latticeecp2-6 s-series device, the dual boot fl ash size required is 8 mb due to the number of sectors required. device all modes slave serial mode slave parallel mode unencrypted bitstream size (mb) encrypted bitstream size (mb) encrypted bitstream size (mb) ecp2-6 1.5 2.3 7.5 ecp2-12 2.9 4.3 14.2 ecp2-20 4.5 6.7 22.0 ecp2-35 6.3 9.4 31.2 ecp2-50 8.9 13.4 44.3 ecp2-70 13.3 20.0 66.1 ecp2m-20 5.9 8.9 29.5 ecp2m-35 9.8 14.8 48.9 ecp2m-50 15.8 23.7 78.6 ecp2m-70 19.8 29.7 98.6 ecp2m-100 25.6 38.5 127.6 15-9 lattice semiconductor latticeecp 2/m sysconfig usage guide the estimated time for configuration can be calculated by divi ding the bitstream size (in bits) from table 15-4 by the cclk frequency. the cclk frequency can be set using th e global preferences tab within the isplever design planner or the spreadsheet view (global preferences tab) in diamond. for more information on setting the cclk frequency, please see the master clock section and the d[0]/spifastn pin section of this document. when downloading an encrypted bitstream file to the latticeecp2/m s-series devices, the user must adhere to the appropriate conditions for the cclk signal. these conditions are shown in tn1109, latticeecp2/m configuration encryption usage guide . table 15-6. spi serial flash vendor list one fpga, one spi flash the simplest spi configuration consists of one spi seri al flash connected to one latticeecp2/m, as shown in figure 15-1. this is also the recommended method for use when downloading an encrypted bitstream file to the latticeecp2/m s-series devices. figure 15-1. one fpga, one spi serial flash multiple fpga, one spi flash with a sufficiently large spi flash multiple fpgas can be configured as shown in figure 15-2. the first fpga is configured in spi mode; the following fpgas are configured in slave serial mode. vendor part number st microelectronics m25pxx winbond w25pxx silicon storage technology sst25vfxx, sst25lfxx spansion s25flxx atmel at25fxx nexflash nx25pxx macronix mx25lxx note: this is not meant to be an exhaustive list and may be updated from time to time. lattice fpga spi mode cclk di/csspi0n busy/sispi d7/spid0 dout cfg1 cfg0 spifastn spi serial flash q c cfg2 d0/spifastn programn done d /cs 15-10 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-2. multiple fpgas, one spi serial flash spim mode externally, except for the cfg pins, spim mode looks like spi mode, they use the same spi serial flash devices, and are wired to the fpga in the same way (see figure 15-6). the spim mode does not support multiple fpgas being configured from one spi serial flash as shown in figure 15-2. internally the two modes are treated differ- ently. spi mode treats the spi serial flash as a single block of storage starting at address zero. the spim mode treats the spi flash memory as discrete blocks of memory rather than a single block of memory. this allows the storage of separate configuration images in separate blocks of memory. spim supports dual configuration (or boot) images, here referred to as a ?golden? image and a primary image. a golden image is used when th ere is the possibility that corrupt data co uld be inadvertently loaded into the spi serial flash, such as during remote updates. for instance, if the flash erase or program procedure is interrupted, perhaps due to a power failu re, then the flash will contain corrupt data and the system could be rendered inopera- ble. ideally the fpga should detect that the data is corrupt and boot from a known good, or golden, boot image. this is exactly what spim does. the golden image is stored at the beginning of the flash address space; the updatable, or primary, image is above the golden image. during configuration, if the fpga detects data corruption in the primar y image, it will automati- cally reboot from the golden image. each time the fpga powers up, the programn pin is toggled, or a jtag refresh instruction is issued, it will try to configure from the primary image first. note that if the latticeecp2/m detects that the data in the golden image is corrupt as well initn will be driven low and the part will stop trying to configure. dual boot image setup in order to use dual configuration files the files must firs t be properly stored within the spi serial flash. lattice ispvm? system software makes this easy. lattice fpga spi mode cclk di/csspi0n busy/sispi d7/spid0 dout cfg1 cfg0 spifastn spi serial flash q c cfg2 d0/spifastn programn done d /cs lattice fpga slave serial cclk di/csspi0n cfg1 cfg0 cfg2 dout note: this method is not available when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to the latticeecp2/m s-series configuration encryption usage guide , tn1109, for more information about using encrypted bitstream files. 15-11 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-3. ispvm main window first, create the desired files using isplever or diamond. depending on th e application, these files might be the same design or different designs. there is nothing special about these files, in other words they contain all of the information needed to fully configure the fpga. next, open ispvm (see figure 15-3), do a scan of the board by clicking on the scan button on the toolbar, and then double click on the row in the chain that has the latticeecp2/m. you will now see the device information win- dow (see figure 15-4). figure 15-4. device information window from the device options drop-down box select dual boot spi flash programming . then click on the spi flash options button to open the spi serial flash device windo w (see figure 15-5). in this window click on select and choose the spi flash that?s mounted on the board. 15-12 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-5. spi serial flash device window second, click on browse to select an output file name. third, select the operation, such as spi flash erase , program , verify . fourth, select the golden file and primary file. note that these may be encrypted for the latticeecp2/m ?s? version or non-encrypted files. if they are encrypted files they must both be encrypted with the same key. and finally, click on the generate button. when file generation is complete, click on ok to get back to the main ispvm window. to program the file into the spi serial flash just click on the go button on the toolbar. at power-up, when the programn pin is toggled, or when a jtag refresh instruction is issued, the latticeecp2/m reads the primar y file from spi serial flash. if a crc error is found then the latticeecp2/m will re- boot automatically, reading configuration data from the golden file instead of the primary file. note that if an error is found in the golden file the latticeecp2/m will drive the initn pi n low and stop trying to configure. note that the flow specified here is for initial programming of the spi serial flash. during a field update of the spi serial flash it is expected that only the primary configuration file will be updat ed, not the golden file. this is impor- tant because it guarantees the availab ility of a known good configuration file. 15-13 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-6. spim, dual configuration images programming spi serial flash the latticeecp2/m contains dedicated hardware that allows jtag to access the spi port, allowing ispvm, embed- ded hardware, or ate equipment to program the flash while it is on the board. in order to program spi serial flash using jtag, the cfg pins must be set to spi or spim (see table 15-3). please refer to the ispvm help system for more information. slave serial mode in slave serial mode the cclk pin becomes an input, receiving the clock from an external device. the latticeecp2/m accepts data on the di pin on the rising ed ge of cclk. slave serial only supports writes to the fpga, it does not support reading from the fpga. after the device is fully configured, if the bypass option has been set, any addi tional data clock ed into di will be presented to the next device via the dout pin, as shown in figure 15-7. lattice fpga spim mode cclk di/csspi0n busy/sispi d7/spid0 cfg1 cfg0 spifastn cfg2 d0/spifastn programn done spi serial flash primary boot golden boot note: the csspi1n pin should not be connected. 15-14 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-7. serial mode daisy chain slave parallel mode in slave parallel mode a host system se nds the configuration data in a byte -wide stream to the latticeecp2/m. the cclk, csn, cs1n, and writen pins are driven by t he host system. writen, csn, and cs1n must be held low to write to the device; data is input from d[0:7]. d0 is the msb and d7 is the lsb. slave parallel mode can also be used for readback of the internal configuration. by driving the writen pin low, and csn and cs1n low, the device will input the readback instructions on the d[0:7] pi ns; writen is then driven high and read data is output on d[0:7] (see figure 15-8). in order to support readback, the persistent bit must be set to on in isplever design planner or in the diam ond spreadsheet view (g lobal prefer ences tab). figure 15-8. parallel port read timing diagram lattice fpga slave serial cclk di/csspi0n done initn dout cfg1 cfg0 cpu data clk cfg2 programn program status status lattice fpga slave serial dout cfg1 cfg0 cfg2 cclk di/csspi0n done initn programn note: in the slave serial mode, the bypass option is not supported when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to the latticeecp2/m s-series configuration encryption usage guide , tn1109, for more information about using encrypted bitstream files. writen read data cclk d[0:7] busy csn cs1n send read command csn pulse width is dependent on the time required to disable the external d[0:7] driver. 15-15 lattice semiconductor latticeecp 2/m sysconfig usage guide the host sends the preamble, bdb3 (hex), and then sends the read command. the latticeecp2/m sends read data on d[0:7], driving busy high as needed to pause data flow. for an example bitstream see table 15-7. table 15-8 lists the various read commands. note that the sample bitstream and the list of read commands are for reference only; to help the user better understand the flow . the actual bitstream, containing the read commands, is generated by isplever or diamond an d ispvm, the host, toggles the cont rol signals and se nds the bitstream. table 15-7. parallel port read bitstream example table 15-8. parallel port read commands slave parallel mode can support two types of overflow, bypass and flowthrough. after the first device has received all of it?s configuration data, and the bypass command is detected in the bitstream, the data presented to the d[0:7] pins will be serialized and bypa ssed to the dout pin (see figure 15-9). if the flowthrough command is detected in the bitstream, inst ead of the bypass command, the cson signal will dr ive the following parallel mode device?s chip select low as shown in figure 15-10. if either type of ov erflow is active, driving both the csn and cs1n pins high will reset overflow, i.e. take the device out of overflow. frame contents description header 1111...1111 2 dummy bytes 10111101 10110011 2-byte preamble (bdb3) verify id 8 bytes of command and data reset address 4 bytes of command and data read increment 4 bytes of command and data command 32-bit opcode function reset address e2000000 reset address register to point to the first data frame read increment 01vvvvvv read back the configuration memory frame selected by the address register and post increment the address read usercode 83000000 read the content of the usercode register read ctrl reg 0 84000000 read the co ntent of control register 0 read crc 86000000 read crc register content read id code 87000000 read id code no op ff no operation. this is an 8-bit opcode. extra bits should not be appended to this opcode as this could cause initn to go low during configuration. note: x = don't care, v = variable. 15-16 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-9. slave parallel with bypass option lattice fpga slave parallel cclk d[0:7] done initn dout cfg1 cfg0 cfg2 cs1n program lattice fpga slave serial dout cfg1 cfg0 cfg2 cclk di/csspi0n done initn programn busy writen csn programn writen busy clock data done init select1 select2 note: in slave parallel mode, the bypass option is not supported when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to the latticeecp2/m s-series configuration encryption usage guide , tn1109, for more information about using encrypted bitstream files. 15-17 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-10. slave parallel with flowthrough to support asynchronous configuration, where the host may provide data faster than the fpga can accept it, slave parallel mode can use the busy signal. by driving the busy signal high the slave parallel device tells the host to pause sending data. please note that all data and control are still synchronous with cclk , asynchronous refers to the ability to throttle the data tran sfer using busy. see figure 15-11. figure 15-11. parallel port write timing diagram the csn and cs1n pins must remain low while the configur ation bitstream is being sent to the device or the con- figuration will fail. to temporarily stop the write proces s, the user can pause the ccl k signal and the data. an example of this is shown in figure 15-11. lattice fpga slave parallel cclk d[0:7] done initn cson cfg1 cfg0 cfg2 cs1n program busy writen csn programn lattice fpga slave parallel cclk d[0:7] done initn cfg1 cfg0 cfg2 cs1n busy writen csn programn cson initn done d[0:7] cclk busy writen ft_reset selectn note: in slave parallel mode, the flowthrough option is not supported when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to the latticeecp2/m s-series configuration encryption usage guide , tn1109, for more information about using encrypted bitstream files. d[0:7] initn programn writen cclk busy current command write write write next command csn cs1n write note: when downloading an encrypted bitstream file to the latticeecp2/m s-series devices, the user must adhere to the appropriate conditions for the cclk signal. these conditions are shown in the latticeecp2/m s-series configuration encryption usage guide , tn1109. 15-18 lattice semiconductor latticeecp 2/m sysconfig usage guide ispjtag mode the latticeecp2/m device can be configured through the ispjtag port using either fast program or ieee 1532 mode. the jtag port is always on an d available, regardless of the confi guration mode selected. the ieee 1532 mode is called erase, program, verify in ispvm system. fast program fast program can be thought of as serial configuration using the jtag port. the data file used for fast program is the same as a file used for a sysconfig serial mode configuration, in other words there is a header, a preamble, and configuration data. fast program will result in a faster configuration ti me since the bitstr eam contains crc checking so a time consuming post programming bit by bit verification is not required. the svf and vme file for- mats also support fast programming. during jtag configuration the boundary scan cells take control of the latticeecp2/m i/os. the boundary scan cells will usually drive the i/os to a tri-state level but th is can be controlled and even customized using ispvm. note that programn, initn, and done have no meaning since they are controlled by the boundary scan cells during jtag configuration. however, the initn and done do indicate configuration status after jtag configuration is completed. ieee 1532 besides fast program the latticeecp2 /m can also be configured through jtag using the i eee 1532 standard. the ieee 1532 mode is called erase, program, verify in ispvm system. ieee 1532 co nfiguration files contain jtag instructions, as well as the configuration data. ieee 1532 files, including isc, svf, and vme, can be created using ispvm?s universal file writer (ufw). these files can be used by ispvm or by third party ate equipment. these files can also be used in embedded situations, where an on-board processor provides the data while con- trolling the jtag signals (this is call ed ispvm embedded, mo re information can be found in ispvm?s help facility). ieee 1532 programming will be slower than the fast prog ram mode since it requires a post programming bit by bit verification. during jtag configuration the boundary scan cells take control of the latticeecp2/m i/os. the boundary scan cells will usually drive the i/os to a tri-state level but this can be controlled and even customized using ispvm. note that programn, initn, and done have no meaning since they are controlled by the boundary scan cells during jtag configuration. however, the done pin will indicate configuration status afte r ieee 1532 configuration is completed. transparent read back the ispjtag transparent read back mode allows the user to read the content of the device while the device remains fully functional. all i/o, as we ll at the non-jtag configuration pins, remain under internal logic control dur- ing a transparent read back. the device enters the transparent read back mode through a jtag instruction. the user must ensure that transparent read back does not access ebr or distributed ram at the same time internal logic is accessing these resources or corruption of the ram may occur. boundary scan and bsdl files the latticeecp2/m bsdl files can be found on the lattice semiconductor web site. the boundary scan ring cov- ers all of the i/o pins, as well as the dedicated and dual-purpose sysconfig pins. note that programn, cclk, and the cfg pins are observe only (bc4, jtag read-only) boundary scan cells. configuration options several configuration options are available for each configuration mode. ? when daisy chaining multiple fpga devices an overflow option is provided for serial and parallel configuration modes ? when using spi or spim mode, the master clock frequency can be set ? a security bit can be set to prevent sram readback 15-19 lattice semiconductor latticeecp 2/m sysconfig usage guide ? the bitstream can be compressed ? the persistent option can be set ? configuration pins can be protected ? done pin options can be selected by setting the proper parameter in the lattice design software the selected configuration options are set in the gen- erated bitstream. as the bitstream is loaded into the devi ce the selected configuration options take effect. these options are described in the following sections. bypass option in isplever, the bypass option can be set by using the bit gen properties. or, a chain of bitstreams can be assem- bled and bypass set using ispvm. to set the bypass option in diamond, see appendix a. the bypass option can be used in parallel and serial mode daisy chains. the bypass option is not supported when using spim configura- tion. the bypass option is not supported when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to tn1109, latticeecp2/m configuration encryption usage guide , for more information about using encrypted bitstream files. when the first device completes configuration, and a bypass command is input from the bitstream, any additional data coming into the fpga configuratio n port will overflow serially on dout. th is data is applied to the di pin of the next device (downstream devices must be set to slave serial mode). in serial configuration mode the bypass option connects di to dout via a bypass register. the bypass register is initialized with a ?1? at the beginning of configuration and will stay at that value until the bypass command is exe- cuted. in parallel configuration mode the bypass option caus es the excess data coming in on d[0:7] to be serially shifted to dout. the serialized data is shifted to dout through a bypass re gister. d0 will be shifted out first fol- lowed by d1, d2, and so on. once the bypass option star ts the device will remain in bypass until the wake-up sequence completes. in parallel mode, if bypass needs to be aborted, drive both csn and cs1n high, this acts as a bypass reset signal. flowthough option as with bypass, flowthrough can be set in the bitgen properties in isplever and in the strategy process options settings. to set the flowthrough option in diamond, see appendix a. the flowthrough option can be used with par- allel daisy chains only. the flowthrough option is not supported when using spim configuration. the flowthrough option not supported when using encrypted bitstream files with the latticeecp2/m s-series devices. please refer to tn1109, latticeecp2/m configuratio n encryption usage guide , for more information about using encrypted bit- stream files. when the first device completes configuration, and a fl owthrough command is input from the bitstream, the cson pin is driven low. in addition to driving cson low, flowthrough also tri-states the device?s d[0:7] and busy pins in order to avoid contention with the other daisy-chained devices. once the flow through option starts the device will remain in flowthrough until the wake-up sequence completes. if flowthrough needs to be aborted drive both csn and cs1n high, this acts as a flowthrough reset signal. master clock if the cfg pins indicate an spi or spim mode the cclk pin will become an out put, with the frequency set by the user. the default master clock frequency is 3.1 mhz. for a complete list of the supported master clock frequen- cies, please see the latticeecp2/m family data sheet . when using the latticeecp2/m s-series devices, the available frequencies are restricted, as shown in the data sheet. the user can change the master clock frequency by setting the mcclk_freq global preference in the lattice isplever design planner. to set this option in diamond, see appendix a. one of the first things loaded during configuration is the mcclk_freq parameter; once this parameter is loaded the frequency changes to the selected value using a glitchless switch. care should be exercised not to exceed the frequency specification of the slave devices or the signal integr ity capabilities of the pcb layout. 15-20 lattice semiconductor latticeecp 2/m sysconfig usage guide configuration time is computed by dividing the maximum number of configuration bits, as given in table 15-4 above, by the master clock frequency. security bit setting the config_secure option to on prevents readback of the sram from jtag or the sysconfig pins. when config_secure is set to on the only operations available are erase and write. the security fuse is updated as the last o peration of sram configuration. if a secu red device is read it will output all zeros. for latticeecp2/m devices the config_ secure option is accessed via the design planner in isplever. to set this option in diamond, see appendix a. the default is off. for the latticeecp2/m s-series devices (part nu mbers ecp2-xxes and ecp2mx xes) the config_secure option is accessed using the security setting option under the tools menu. compress bitstream setting the global compress _config option to on in isplever desi gn planner will cause the software to gen- erate a compressed bitstream. to set this option in dia mond, see appendix a. the latticeecp2/m will automati- cally decompress the bitstream as it comes into the device . the actual amount of compression varies according to the data pattern in the uncompressed bitstream. though unlikely, it is theoretically possible for the compressed bit- stream to be larger than the uncompressed bitstream. compressing the bitstream can result in faster configuration. the default setting is off. persistent option the persistent option is set using isplever design pla nner (default is off). to se t this option in diamond, see appendix a. persistent serves two purposes. setting persistent on tells the place and route tools that it may not use any of the sysconfig pins associated with the parallel port (all of the dual-purpose pins except di) or the spi port pins. setting persistent on also sets a hardware fuse. so, not only are the pins reserved in software, they are also reserved in hardware. persistent is set to on when the user wants to be able to read the sram configuration memory using the slave parallel port. in order to perform a read using the parallel port the user must first send a read command, set- ting persistent on allows the paralle l port to listen for this command while in user mode (the done pin is high). if the design does not require this function, the persistent option should be set to off. the persistent preference must also be set to on if the spi memory needs to be accessed using the spi port while the part is in user mode (the done pin is high) to preserve the spi port pins. configuration mode just as the cfg pins tell the hardware which port to configure from; the config_mode option tells the software which port will be used. config_mode allows the user to protect dual-purpose sysconfig pins. for example setting config_mode to spi will keep the place and route to ols from using the spi pins as general purpose i/o. the user, however, is still free to assign these pins as gpio, but a warning will be generated as a reminder that there are certain precautions (see the section above entitled configuration pins). available options are none, jtag, spi, spim, slave serial, and slave parallel. the default is slave serial. done_od, done_ex during configuration the done pin is low. once configuration is comp lete, indicated by the setting of the internal done bit, the device wake-up sequence takes place and then the done pin goes high. under most circumstances, this flow is exactly what is needed, however, if there are several devices in one configuration chain, delay of the wake-up sequence may be desirable in order to ?synchronize? the wake-up of all devices in the chain. there are two options that allow for this synchronization. these options are set in isplever design planner. to set these options in diamond, see appendix a. 15-21 lattice semiconductor latticeecp 2/m sysconfig usage guide done_od defaults to on. done_od on forces the done pin type to be open- drain. when connecting multiple done pins together all of the pins should be open- drain, however it may be advantageous to have an actively driven done pin on the last device. setting done_od to off makes the done pin an actively driven pin, rather than open-drain. done_ex defaults to off. setting done_ex to on will ca use latticeecp2/m to sample the done pin and, if the done pin is held low externally, de lay the wake-up sequence. setting done _ex to off will cause the device to wake-up as soon as the internal done bit is set. device wake-up when configuration is complete the devi ce will wake up in a predictable fash ion. wake-up occurs after successful configuration, without errors, and provides the transition from configuration mode to user mode. the wake-up pro- cess begins when the internal done bit is set. table 15-9 provides a list of the wake-up sequences su pported by the latticeecp2/m; figure 15-12 shows the wake-up timing. the wake_up defaults work fine for th e vast majority of applic ations. to set the wake_up options in diamond, see appendix a. table 15-9. wake-up options sequence phase t0 phase t1 phase t2 phase t3 1 done goe, gwdis, gsr 2 done goe, gwdis, gsr 3 done goe, gwdis, gsr 4 done goe gwdis, gsr 5 done goe gwdis, gsr 6 done goe gwdis gsr 7 done goe gsr gwdis 8 done goe, gwdis, gsr 9 done goe, gwdis, gsr 10 done gwdis, gsr goe 11 done goe gwdis, gsr 12 done goe, gwdis, gsr 13 goe, gwdis, gsr done 14 goe done gwdis, gsr 15 goe, gwdis done gsr 16 gwdis done goe, gsr 17 gwdis, gsr done goe 18 goe, gsr done gwdis 19 goe, gwdis, gsr done 20 goe, gwdis, gsr done 21 (default) goe gwdis, gsr done 22 goe, gwdis gsr done 23 gwdis goe, gsr done 24 gwdis, gsr goe done 25 goe, gsr gwdis done 15-22 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-12. wake-up timing diagram synchronizing wake-up the internal wake-up sequence clock source can be chosen as well as how the device wakes up relative to other devices. wake-up clock selection the wake-up sequence is synchronized to a clock source th at is user selectable. the clock sources are external (default) and user clock. when external is selected the latticeecp2/m will use one of two clocks during the wake-up sequence, depending on the configuration data source. if the latticeecp2/m is being configured from jtag then jtag?s tck will be used for the wake-up sequence, if configuration data is coming from a sysconfig port (serial, parallel, or spi) then cclk will be used. when user is selected, any of the clock signals in the design can be used as the clock source. synchronous to internal done bit if the latticeecp2/m is the only device in the configuratio n chain, or the last device in the chain, done_ex should be set to the default value (off). the wake-up process will be initiated by setting of the internal done bit on suc- cessful completion of configuration. synchronous to external done pin the done pin can be used to synchronize wake-up to other devices in the configuration chain. if done_ex (see the done_od, done_ex section above) is on then the done pin is a bi-directional pin. if an external device drives the done pin low then the wake-up sequence will be delayed; configuration c an complete but wake-up is delayed. once the done pin goes high the device will follow the selected wake_up sequence. in a configuration chain, a chain of devices configuring from one source (such as figure 15-2), it is usually desir- able, or even necessary, to delay wake-up of all of the devi ces until the last device finishes configuration. this is accomplished by setting done_od to off and done_ex to off on the last device while setting done_od to on and done_ex to on for the other devices. wake-up sequence options the wake-up sequence options shown in table determine the order of application for three internal signals, gsr, gwdis, and goe, and one external signal, done. ? gsr is used to set and reset the core of the device. gsr is asserted (low) during configuration and de-asserted (high) in the wake-up sequence. bclk done bit global output enable global set/reset global write disable done pin t0 t1 t2 t3 15-23 lattice semiconductor latticeecp 2/m sysconfig usage guide ? when the gwdis signal is low it safeguards the integrity of the ram blocks and luts in the device. this signal is low before the device wakes up. ? when high, the goe signal prevents the device?s i/o buffers from driving the pins. ? when high, the done pin indicates that configuration is complete and that no errors were detected. if done_ex (see done_od, done_ex above) is off then sequence 21 is the default, but the user can select any sequence from 8 to 25; if done_ex is on the defaul t sequence is 4, but the user can select any sequence from 1 to 7. configuration faqs here are some of the more common questions regarding device configuration. general ? q. other than jtag, what is the least expensive method of configuration? a . if you already have a processor and extra storage on the board you can use the processor to feed configura- tion data to the latticeecp2/m. the least expensive stand-alone configuration option is spi serial flash. ? q. i have created my bitstream, now how do i load the bitstream into the latticeecp2/m? a. use the free lattice ispvm tool (from www.latticesemi.com ), and a lattice ispdownload ? cable. ? q. i can?t read the latticeecp2/m device id using jtag. what could be wrong? a. this is the most basic of jtag operations. if you are having trouble reading the device id then something basic is wrong. check that the jtag connections are correct, and that v ccj and the download cable v cc are cor- rect (and the same). make sure that the xres pin is connected to ground through a 10k resistor. check that all latticeecp2/m v cc and ground pins are properly connected. check for noise on the jtag signals. sometimes touching a properly grounded ?scope probe to tck will change the sympto ms; if so, you have signal noise issues. check for excessive noise on the v cc pins. ? q. is there anything i can do during board design that will make debugging easier? a . bring the dedicated configurations pins, programn, in itn, done, and cclk out to accessible test points. ? q. do i need external pull-up resistors on programn, initn, or done? a . all of these signals have internal weak pull-ups, however if you have a noisy environment, or have several devices connected to these pins, adding a 10k pull-up to the signal is recommended. ? q. how can i get assistance with configuration issues? a. use the on-line assistant fe ature in ispvm. you will find it under the help menu. 15-24 lattice semiconductor latticeecp 2/m sysconfig usage guide mode specific spi/spim ? q. how do i program the spi serial flash once it?s on the board? a. connect the spi serial flash to the latticeecp2/m as shown in this document, then use ispvm, and a lattice ispdownload cable connected to the jtag port, to program the bitstream into the flash. latticeecp2/m devices have a jtag instruction for programming the spi serial flash. this jtag instruction connects the jtag tck internally to the cclk which driv es the spi clock during programming. after launching ispvm, click on the scan button to scan the devices in the jtag chain, select the latticeecp2/m device, then click edit>edit device to launch the device information window. in the device information window, select spi flash programming for the device access options to open the spi serial flash device window. select the spi serial flash device and the bitstream data file for programming the spi serial flash. ? q. are there any special requirements for wiring the spi flash to the latticeecp2/m? a. other than connecting the flash to the right pins the only other suggestion is to add a 4.7k pull-down resistor between cclk and ground. this keeps cclk quite during v cc ramp-up. ? q. can i use 2.5v to power the spi flash? a. today all spi serial flash of the ?25? type are 3.3v, so the flash, and v ccio8 , must be connected to 3.3v. ? q. can i use something other than a ?25? type spi serial flash? a. only devices that recognize a read op-code of 03h may be used with the latticeecp2/m. please refer to table 15-6 for a list of vendors. ? q. my design is small, can i use a smaller-than-recommended spi flash? a. the state of all of the device fuses is contained in the bitstream, whether they are part of the design or not. the size of the design does not affect the size of the bitstream. serial ? q. can i use a free running clock for slave serial mode? a. the latticeecp2/m clocks data in on every rising edge of cclk so there should only be one rising clock edge for each data bit. ? q. is the bitstream for the serial modes different from the bitstream for other modes? a. all sysconfig bitstreams are the same, they can be different file types, such as hex or binary, but the data is the same. parallel ? q. my processor is generating all of the proper cont rol signals but the latti ceecp2/m won?t configure, and initn goes high and stays high while done stays low. what?s wrong? a. d0 is the msb and d7 is the lsb. try reversing the bit order for each byte in the bitstream. you can do this using your processor or you can generate a bit mirrored file using ispvm. lattice recommends using your proces- sor so that you don?t have to remember to bit mirror the file. technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www.latticesemi.com 15-25 lattice semiconductor latticeecp 2/m sysconfig usage guide revision history date version change summary february 2006 01.0 initial release. february 2006 01.1 added ecp2-6 to maximum configuration bits table and changed ecp2-22 to ecp2-20. april 2006 01.2 updated section on spim. also added screen shots to spim section. september 2006 01.3 updated maximum configuration bits table with ecp2m35 data. february 2007 01.4 updated maximum configuration bits table with ecp2m data. march 2007 01.5 added information about latt iceecp2/m ?s? series to the dual boot image setup section. april 2007 01.6 added more information about spi programming using ispvm to the spi/spim q&a section. june 2007 01.7 added hysteresis value. removed support for booting from multiple spi flash devices in the spim mode. added note for spifastn pin. august 2007 01.8 added sizes for encrypted bi tstream files and new conditions for their use. removed restriction on i/o direction for dual-purpose configuration pins. september 2007 01.9 updated configuration pins text section. updated programn text section. january 2008 02.0 changed programn and initn pin descriptions. changed csn and cs1n pin description. added csn and cs1n pin restrictions in slave parallel mode section. september 2008 02.1 updated cclk text section. june 2010 02.2 updated document for lattice diamond design software support. 15-26 lattice semiconductor latticeecp 2/m sysconfig usage guide appendix a. lattice diamond usage overview this appendix discusses the use of lattice diamond design software for projects that include the latticeecp2m serdes/pcs module . for general information about the use of lattice diamond, refer to the lattice diamond tutorial. if you have been using isplever software for your fpga design projects, lattice diamond may look like a big change. but if you look closer, you will find many similariti es because lattice diamond is based on the same toolset and work flow as isplever. the changes are intended to provide a simpler, more integrated, and more enhanced user interface. converting an isplever pr oject to lattice diamond design projects created in isplever can easily be imported into la ttice diamond. the pr ocess is automatic except for the isplever process properties, which are similar to the diamond strategy settings, and pcs modules. after importing a project, you need to set up a strategy for it and regenerate any pcs modules. importing an isple ver design project make a backup copy of the isplever project or make a new copy that will become the diamond project. 1. in diamond, choose file > open > import isplever project . 2. in the isplever project dialog box, browse to the project?s .syn file and open it. 3. if desired, change the base file name or location for the diamond project. if you change the location, the new diamond files will go into the ne w location, but the original source files will not move or be copied. the diamond project will refere nce the source files in the original location . the project files are converted to diamond format with the default strategy settings. adjusting pcs modules pcs modules created with ipexpress have an unusual file structure and need additional adjustment when import- ing a project from isplever. there are two ways to do this adjustment. the preferred method is to regenerate the module in diamond. however this may upgrade the module to a more recent version. an upgrade is usually desir- able but if, for some reason, you do not want to upgrade the pcs module, you can manually adjust the module by copying its .txt file into the implementation folder. if you use this method, you must remember to copy the .txt file into any future implementation folders. regenerate pcs modules 1. find the pcs module in the input files folder of file list view. the module may be represented by an .lpc, .v, or .vhd file. 2. if the file list view shows the verilog or vhdl file for the module, and you want to regenerate the module, import the module?s .lpc file: a. in the file list view, right-click the implementation folder ( ) and choose add > existing file . b. browse for the module?s .lpc file, 15-27 lattice semiconductor latticeecp 2/m sysconfig usage guide in file list, the .lpc file is replaced with an .ipx file. the ipexpress manifest (.ipx) file is new with diamond. the .ipx file keeps track of the files needed for complex modules. using ipexpress wi th lattice diamond using ipexpress with lattice diamond is essentially same as with isplever. the configuration gui tabs are all the same except for the generation options tab. figure 15-13 shows the gener- ation options tab window. figure 15-13. generation options tab table 15-10. serdes_pcs gui attr ibutes ? generation options tab gui text description automatic automatically generates the hdl and configuration(.txt) files as needed. some changes do not require regenerating both files. force module and settings generation generates both the hdl and configuration files. force settings generation only generates only the attributes file. you ge t an error message if the hdl file also needs to be generated. force place & route process reset resets the place & route design process, forcing it to be run again with the newly generated pcs module. force place & route trace process reset resets the place & route trace process, fo rcing it to be run again with the newly generated pcs module. note: automatic is set as the default option. if ei ther automatic or force settings generati on only and no sub-options (process reset options) are checked and the hdl module is not generated, the reset pointer is set to bitstream generation automatically. after the generation is finished, the reset marks in the process window will be reset accordingly. 15-28 lattice semiconductor latticeecp 2/m sysconfig usage guide creating a new simulation proj ect using simulation wizard this section describes how to use the simulation wizard to create a simulation project (.spf) file so you can import it into a standalone simulator. 1. in project navigator, click tools > simulation wizard . the simulation wizard opens. 2. in the preparing the simulator interface page click next . 3. in the simulator project name page, enter the name of your project in the project name text box and browse to the file path location where you want to put your simulation projec t using the project location text box and browse button. when you designate a project name in this wizard page, a corresponding folder will be created in the file path you choose. click yes in the popup dialog that asks you if you wish to create a new folder. 4. click either the active-hdl ? or modelsim ? simulator check box and click next . 5. in the process stage page choose which type of process stage of simulation project you wish to create valid types are rtl, post-synthesis gate-level, post-map gate-level, and post-route gate-level+timing. only those process stages that are available are activated. note that you can make a new selection for the current strategy if you have more than one defined in your project. the software supports multiple strategies per project implementation which allow you to experiment with alternative optimization options across a common set of source files. since each strategy may have been processed to different stages, this dialog allo ws you to specify which stage you wish to load. 6. in the add source page, select from the source files listed in the source files list box or use the browse button on the right to choose another desired source file. note that if you wish to keep the source files in the local simulation project directory you just created, check the copy source to simulation directory option. 7. click next and a summary page appears and provides information on the project selections including the simulation libraries. by default, the run simulator chec k box is enabled and will launch the simulation tool you chose earlier in the wizard in the simulator project name page. 8. click finish . the simulation wizard project (.spf) file and a simulation script do file are generated after running the wizard. you can import the do file into your current project if de sired. if you are using active -hdl, the wizard will generate an .ado file and if you are using modelsim, it creates and .mdo file. note: pcs configuration file, (.txt) must be added in step 6. setting global pref erences in diamond to set any of the global preferences in table 15-11, do the following in diamond: ? invoke the spreadsheet view by selecting tools > spreadsheet view . ? select the global preferences tab beneath the spreadsheet view pane as shown in figure 15-14. ? right-click on the preference value to be set. in the drop-down menu, select the desired value. 15-29 lattice semiconductor latticeecp 2/m sysconfig usage guide table 15-11. global preferences preference name values persistent on off config_mode slave_serial jtag none slave_parallel spi spim done_od on off done_ex off mcclk_freq 2.5 5.4 10 34 41 45 config_secure off on wake_up an integer between 1 and 25 compress_config off on inbuf off on enable_ndr off on 15-30 lattice semiconductor latticeecp 2/m sysconfig usage guide figure 15-14. global preferences tab setting bitstream gener ation options in diamond to set any of the bitstream generation options listed in table 15-12, do the following: ? in the file list pane, double-click the left mouse button on a strategy to invoke the strategy settings window. ? in the process pane, left-click on bitstream . all options related to generating a bitstream can be set in this win- dow. 15-31 lattice semiconductor latticeecp 2/m sysconfig usage guide table 15-12. bitstream generation options figure 15-15. setting bitstream options in diamond ? double-click the left mouse button on the value you want to set. select the desired value from the drop-down menu. preference name values chain mode disable (default) bypass flowthrough create bit file true no header tr u e false output format bit file (binary) mask and readback file (ascii) mask and radback file (binary) raw bit file (ascii) prom data output format intel hex 32-bit motorola hex 32-bit reset config ram in re-configuation tr u e false run drc tr u e false search path enter a value or browse to specify the search path 15-32 lattice semiconductor latticeecp 2/m sysconfig usage guide note: an explanation of the option is displayed at the bottom of the window. the help button also invokes online help for the option ?select ok . you can then run the bitstream file process. setting security options in diamond prior to setting security options in diamond, you must have installed the encryption control pack. you must also have selected an encrypted device in your project. to set security settings, do the following: ? select the tools > security setting option. the following dialog box appears: ? if desired, select change and enter a password. ?select ok . a dialog window appears to enter an encryption key. ? if you do not want to enable an encryption key, select ok . ? if you do want to enable an encryption key, select the advanced secu rity settings checkbox, enter the key format , and then enter the encryption key . ?select ok to create the encryption files. www.latticesemi.com 16-1 tn1109_01.4 june 2010 technical note tn1109 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. introduction all lattice fpgas provide configuration data read security, meaning that a fuse can be set so that when the device is read all zeros will be output instead of the actual configuration data. this ki nd of protection is common in the industry and provides very good security if the configuration data storage is on-chip, such as with the latticexp? and machxo? device families. however, if the configuration bitstream comes fr om an external boot device it is quite easy to read the configuration data, allowing access to the fpga design. for this reason the ?s? versions of latticeecp2? and latticeecp2m? offer the 128-bit advanced encryption standard (aes) to protect the bitstream. the user se lects and has total control over the 128-bit key and no special voltages are required to maintain the key within the fpga. this document explains the capabilities of this new security feature and how to take advantage of it. general configuration process figure 16-1 is a block diagram describing the latticeecp2/m ?s? version bitstream encryption data paths. refer to this figure as you read the following sections. figure 16-1. latticeecp2/m ?s? version bitstream encryption block diagram lattice fpgas are configured by using the sysconfig? interface or the jtag interface (see table 16-1). sram fuses 00100101100100 10100101000101 101100101?? crc check decompress scm, spi mux pcm decrypt data jtag port cfg[2:0] disable readback enable jtag direct access (1532) user logic bitstream_burst pcm readback config_secure encryption key rawdecrypted decompressed programmer decoder key fuses jtag latticeecp2/m s-series configuration encryption usage guide 16-2 latticeecp2/m s-series lattice semiconductor configura tion encryption usage guide table 16-1. configuration ports the sysconfig interface allows the user to input data serially, using serial configuration mode (scm) or spi serial flash, or in parallel, using the parallel configuration mode (pcm). in general, the connection between the fpga and the configuration device consists of a clock, chip select(s), a write signal (in pcm), and data. during configuration all data written to the fpga is ignored until a special preamble is detected in the bitstream. every- thing after the preamble is configuration data. the normal preamble is bdb3 (hex), however encrypted bitstreams contain a different preamble. when using scm mode, an y cclk frequencies from 2.5mhz to 45mhz are sup- ported but it is required to stop the cclk after loading the bab3 (hex) encryption preamble as shown below. figure 16-2. cclk timing to ensure proper programming when using encrypted bits treams in spi mode only a subset of cclk frequencies are supported. the supported frequencies are shown in the latticeecp2/m family data sheet . the jtag port, which conforms to ieee 1149.1 and ieee 1532 standards, can input data in bitstream-burst mode (fast program) or 1532 mode. configuration bitstreams created for bitstream-burst mode (fast program) are iden- tical to the configuration bitstreams created for sysconfig mode. the bitstream contains a header, a preamble, configuration data, and frame data crc. however, 1532 mode makes use of standard jtag instructions to config- ure the device. in other words, the configuration data file contains configuration data only. because 1532 mode data files do not contain a preamble, they cannot be used to input encrypted configuration files. in addition to being a configuration interface, jtag also allows the user to program the 128-bit encryption key. in fact, jtag is the only way to program the key. interface port sysconfig spi 1 spim 1 slave serial (scm) 2 slave parallel (pcm) 2 ispjtag? ieee 1532 (erase, program, verify) 3 bitstream burst (fast program) 1. supports subset of the cclk frequencies specified in the latticeecp2/m family data sheet . 2. users must adhere to the appropriate conditions for the cclk signal as described below. 3. does not support encrypted bitstreams. programn initn di cclk done bab3 encrypted bitstream stop cclk from second clock after bab3 1ms min. 16-3 latticeecp2/m s-series lattice semiconductor configura tion encryption usage guide for detailed information on latticeecp2/m configuration including bitstream file sizes, refer to tn1108, latticeecp2/m sysconfig usage guide . note that bitstream sizes vary depending on the configuration mode. bitstream encryption/decryption flow the latticeecp2/m ?s? versions support both encrypted and non-encrypted bitstreams. since the non-encrypted flow is covered in tn1108, latticeecp2/m sysconfig usage guide , this document will conc entrate on the addi- tional steps needed for the encrypted flow. the encrypt ed flow adds only two steps to the normal fpga design flow, encryption of the configuration bitstream and programming the encryption key into the latticeecp2/m ?s? ver- sion devices. encrypting the bitstream as with any other lattice fpga design flow, the engineer must first create the design using a version of isplever ? or lattice diamond? design software which supports the encryption feature. you may need to request the encryp- tion installer to enable access to the additional encryption software. the design is synthesized, mapped, placed and routed, and verified. once the engineer is satisfied with the design a bitstream is created and loaded into the fpga for final debug. after the design has been debugged it is time to secure the design. the bitstream can be encrypted using an appropriate vers ion of isplever by going to the tools pull-down menu and selecting security features or by using the universal file writer (ufw), which is part of the lattice ispvm ? sys- tem tool suite. the file is encrypted using ispvm as follows. to encrypt a bits tream in diamond, refer to appendix a. figure 16-3. ispvm main window 1. start ispvm. you can start ispvm from within isplever or from the start -> programs menu in windows. you should see a window that looks similar to figure 16-3 . click on the ufw button on the toolbar. you will see a window similar to figure 16-4 . ispvm cannot be invoked within diamond. 16-4 latticeecp2/m s-series lattice semiconductor configura tion encryption usage guide figure 16-4. universal file writer (encryption option) 2. double click on input data file and browse to the non- encrypted bitstr eam created in isplever or dia- mond. double-click on output data file and select an output file name. right-click on encryption and select on . right-click on configuration mode and select the type of devi ce the fpga will be configuring from, such as spi serial flash. right-click on encryption key and select edit encryption key . you will see a window that looks similar to figure 16-5. figure 16-5. encryption key dialog window 3. enter the desired 128-bit key. the key can be entered in hexadecimal or ascii. hex supports 0 through f and is not case sensitive. ascii supports all alphanu meric characters, as well as spaces, and is case sen- sitive. note: be sure to remember this key. lattice c annot recover an encrypted file if the key is lost. click on ok to go back to the main ufw window. 4. from the menu bar, click on project -> generate to create the encrypted bitstream file. 5. the bitstream can now be loaded directly into non-volatile configuration storage (such as spi serial flash) using a lattice ispdownload ? cable, a third-party programmer, or any other method normally used to program a non-encrypted bitstream. however, before the latticeecp2/m can configure from the encrypted file the 128-bit key used to encrypt the file must be programmed into the one-time programmable fuses on the fpga. 16-5 latticeecp2/m s-series lattice semiconductor configura tion encryption usage guide programming the 128-bit key the next step is to program the 128-bit encryption key into the one-time programmable fuses on the latticeecp2/m. note that this step is separated from file encryption to allow flexibility in the manufacturing flow. for instance, the board manufacturer might program the encrypted file into the spi serial flash, but the key might be programmed at the user?s facility. this fl ow adds to design security and it allows the user to control over-building of a design. over-building occurs when a third party builds more boards than are authorized and sells them to grey market customers. if the key is programmed at the factory, then the factory controls the number of working boards that enter the mark et. the latticeecp2/m ?s? version will only config ure from a file that has been encrypted with the same 128-bit key that is programmed into the fpga. to program the key into the latticeecp2/m ?s? version, proceed as follows. 1. attach a lattice ispdownload cable from a pc to the jtag connector wired to the latticeecp2/m (note that the 128-bit key can only be programmed into the latticeecp2/m using the jtag port). apply power to the board. 2. start the ispvm system so ftware. ispvm can be started from withi n the isplever design tool (ispvm can- not be invoked from within diamond) or from the start -> programs menu in windows. you should see a window that looks similar to figure 16-3. if the window does not show the board?s jtag chain then proceed as follows. otherwise, proceed to step 3. a. click the scan button in the toolbar to find all lattice devices in the jtag chain. the chain shown in figure 16-3 has only one device, the latticeecp2. figure 16-6. device information window (encryption option) 16-6 latticeecp2/m s-series lattice semiconductor configura tion encryption usage guide 3. double-click on the line in the chain containing the latticeecp2. this will open the device information win- dow (see figure 5). from the device access options drop-down box select security mode , then click on the security key button to the right. the windo w will look similar to figure 16-7. figure 16-7. enter the encryption key 4. enter the desired 128-bit key. the key can be entered in hexadecimal or ascii. hex supports 0 through f and is not case sensitive. ascii supports all alphanu meric characters, as well as spaces, and is case sen- sitive. this key must be the same as the key used to encrypt the bitstream. the latticeecp2/m will only configure from an encrypted file whose encryption key matches the one loaded into the fpga?s one-time programmable fuses. note: be sure to remember this key. once the key lock is programmed, lattice semiconductor cannot read back the one-time programmable key. a. the key can be saved to a file using the save to file button. the key will be encrypted using an 8- character password that the user selects. the na me of the file will be .bek. in the future, instead of entering the 128-bit key, simply click on load from file and provide the password. 5. programming the key lock secures the 128-bit encryption key. once the key lock is programmed and the device is power cycled, the 128-bit encryption key cannot be read out of the device. when satisfied, type yes to confirm, then click apply . 6. from the main ispvm window (figure 16-3) click on the green go button on the toolbar to program the key into the latticeecp2/m one-time programmable fuses. when complete , the latticeecp 2/m will only con- figure from a bitstream encrypted with a key that exactly matches the one just programmed. verifying a configuration as an additional security step when an encrypted bitstream is used, the readback path from the sram fabric is automatically blocked. in this case, for all ports, a read operation will produc e all zeros. however, even when the configuration bitstream has b een encrypted and readback disa bled, there are still ways to verify that the bitstream was successfully downloaded into the fpga. if the sram fabric is programmed directly, the data is first decrypted and then the fpga performs a crc on the data. if all crcs pass, configuration was successful. if a crc does not pass, the done pin will stay low and initn will go from high to low (for more informati on on this type of error, refer to tn1108, latticeecp2/m sysconfig usage guide .
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